2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2003-2008 Joseph Koshy
5 * Copyright (c) 2007 The FreeBSD Foundation
8 * Portions of this software were developed by A. Joseph Koshy under
9 * sponsorship from the FreeBSD Foundation and Google, Inc.
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 /* Support for the AMD K7 and later processors */
38 #include <sys/param.h>
40 #include <sys/malloc.h>
41 #include <sys/mutex.h>
43 #include <sys/pmckern.h>
45 #include <sys/systm.h>
47 #include <machine/cpu.h>
48 #include <machine/cpufunc.h>
49 #include <machine/md_var.h>
50 #include <machine/specialreg.h>
53 enum pmc_class amd_pmc_class;
56 /* AMD K7 & K8 PMCs */
58 struct pmc_descr pm_descr; /* "base class" */
59 uint32_t pm_evsel; /* address of EVSEL register */
60 uint32_t pm_perfctr; /* address of PERFCTR register */
63 static struct amd_descr amd_pmcdesc[AMD_NPMCS] =
70 .pd_caps = AMD_PMC_CAPS,
73 .pm_evsel = AMD_PMC_EVSEL_0,
74 .pm_perfctr = AMD_PMC_PERFCTR_0
81 .pd_caps = AMD_PMC_CAPS,
84 .pm_evsel = AMD_PMC_EVSEL_1,
85 .pm_perfctr = AMD_PMC_PERFCTR_1
92 .pd_caps = AMD_PMC_CAPS,
95 .pm_evsel = AMD_PMC_EVSEL_2,
96 .pm_perfctr = AMD_PMC_PERFCTR_2
103 .pd_caps = AMD_PMC_CAPS,
106 .pm_evsel = AMD_PMC_EVSEL_3,
107 .pm_perfctr = AMD_PMC_PERFCTR_3
111 struct amd_event_code_map {
112 enum pmc_event pe_ev; /* enum value */
113 uint16_t pe_code; /* encoded event mask */
114 uint8_t pe_mask; /* bits allowed in unit mask */
117 const struct amd_event_code_map amd_event_codes[] = {
118 #if defined(__i386__) /* 32 bit Athlon (K7) only */
119 { PMC_EV_K7_DC_ACCESSES, 0x40, 0 },
120 { PMC_EV_K7_DC_MISSES, 0x41, 0 },
121 { PMC_EV_K7_DC_REFILLS_FROM_L2, 0x42, AMD_PMC_UNITMASK_MOESI },
122 { PMC_EV_K7_DC_REFILLS_FROM_SYSTEM, 0x43, AMD_PMC_UNITMASK_MOESI },
123 { PMC_EV_K7_DC_WRITEBACKS, 0x44, AMD_PMC_UNITMASK_MOESI },
124 { PMC_EV_K7_L1_DTLB_MISS_AND_L2_DTLB_HITS, 0x45, 0 },
125 { PMC_EV_K7_L1_AND_L2_DTLB_MISSES, 0x46, 0 },
126 { PMC_EV_K7_MISALIGNED_REFERENCES, 0x47, 0 },
128 { PMC_EV_K7_IC_FETCHES, 0x80, 0 },
129 { PMC_EV_K7_IC_MISSES, 0x81, 0 },
131 { PMC_EV_K7_L1_ITLB_MISSES, 0x84, 0 },
132 { PMC_EV_K7_L1_L2_ITLB_MISSES, 0x85, 0 },
134 { PMC_EV_K7_RETIRED_INSTRUCTIONS, 0xC0, 0 },
135 { PMC_EV_K7_RETIRED_OPS, 0xC1, 0 },
136 { PMC_EV_K7_RETIRED_BRANCHES, 0xC2, 0 },
137 { PMC_EV_K7_RETIRED_BRANCHES_MISPREDICTED, 0xC3, 0 },
138 { PMC_EV_K7_RETIRED_TAKEN_BRANCHES, 0xC4, 0 },
139 { PMC_EV_K7_RETIRED_TAKEN_BRANCHES_MISPREDICTED, 0xC5, 0 },
140 { PMC_EV_K7_RETIRED_FAR_CONTROL_TRANSFERS, 0xC6, 0 },
141 { PMC_EV_K7_RETIRED_RESYNC_BRANCHES, 0xC7, 0 },
142 { PMC_EV_K7_INTERRUPTS_MASKED_CYCLES, 0xCD, 0 },
143 { PMC_EV_K7_INTERRUPTS_MASKED_WHILE_PENDING_CYCLES, 0xCE, 0 },
144 { PMC_EV_K7_HARDWARE_INTERRUPTS, 0xCF, 0 },
147 { PMC_EV_K8_FP_DISPATCHED_FPU_OPS, 0x00, 0x3F },
148 { PMC_EV_K8_FP_CYCLES_WITH_NO_FPU_OPS_RETIRED, 0x01, 0x00 },
149 { PMC_EV_K8_FP_DISPATCHED_FPU_FAST_FLAG_OPS, 0x02, 0x00 },
151 { PMC_EV_K8_LS_SEGMENT_REGISTER_LOAD, 0x20, 0x7F },
152 { PMC_EV_K8_LS_MICROARCHITECTURAL_RESYNC_BY_SELF_MODIFYING_CODE,
154 { PMC_EV_K8_LS_MICROARCHITECTURAL_RESYNC_BY_SNOOP, 0x22, 0x00 },
155 { PMC_EV_K8_LS_BUFFER2_FULL, 0x23, 0x00 },
156 { PMC_EV_K8_LS_LOCKED_OPERATION, 0x24, 0x07 },
157 { PMC_EV_K8_LS_MICROARCHITECTURAL_LATE_CANCEL, 0x25, 0x00 },
158 { PMC_EV_K8_LS_RETIRED_CFLUSH_INSTRUCTIONS, 0x26, 0x00 },
159 { PMC_EV_K8_LS_RETIRED_CPUID_INSTRUCTIONS, 0x27, 0x00 },
161 { PMC_EV_K8_DC_ACCESS, 0x40, 0x00 },
162 { PMC_EV_K8_DC_MISS, 0x41, 0x00 },
163 { PMC_EV_K8_DC_REFILL_FROM_L2, 0x42, 0x1F },
164 { PMC_EV_K8_DC_REFILL_FROM_SYSTEM, 0x43, 0x1F },
165 { PMC_EV_K8_DC_COPYBACK, 0x44, 0x1F },
166 { PMC_EV_K8_DC_L1_DTLB_MISS_AND_L2_DTLB_HIT, 0x45, 0x00 },
167 { PMC_EV_K8_DC_L1_DTLB_MISS_AND_L2_DTLB_MISS, 0x46, 0x00 },
168 { PMC_EV_K8_DC_MISALIGNED_DATA_REFERENCE, 0x47, 0x00 },
169 { PMC_EV_K8_DC_MICROARCHITECTURAL_LATE_CANCEL, 0x48, 0x00 },
170 { PMC_EV_K8_DC_MICROARCHITECTURAL_EARLY_CANCEL, 0x49, 0x00 },
171 { PMC_EV_K8_DC_ONE_BIT_ECC_ERROR, 0x4A, 0x03 },
172 { PMC_EV_K8_DC_DISPATCHED_PREFETCH_INSTRUCTIONS, 0x4B, 0x07 },
173 { PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS, 0x4C, 0x03 },
175 { PMC_EV_K8_BU_CPU_CLK_UNHALTED, 0x76, 0x00 },
176 { PMC_EV_K8_BU_INTERNAL_L2_REQUEST, 0x7D, 0x1F },
177 { PMC_EV_K8_BU_FILL_REQUEST_L2_MISS, 0x7E, 0x07 },
178 { PMC_EV_K8_BU_FILL_INTO_L2, 0x7F, 0x03 },
180 { PMC_EV_K8_IC_FETCH, 0x80, 0x00 },
181 { PMC_EV_K8_IC_MISS, 0x81, 0x00 },
182 { PMC_EV_K8_IC_REFILL_FROM_L2, 0x82, 0x00 },
183 { PMC_EV_K8_IC_REFILL_FROM_SYSTEM, 0x83, 0x00 },
184 { PMC_EV_K8_IC_L1_ITLB_MISS_AND_L2_ITLB_HIT, 0x84, 0x00 },
185 { PMC_EV_K8_IC_L1_ITLB_MISS_AND_L2_ITLB_MISS, 0x85, 0x00 },
186 { PMC_EV_K8_IC_MICROARCHITECTURAL_RESYNC_BY_SNOOP, 0x86, 0x00 },
187 { PMC_EV_K8_IC_INSTRUCTION_FETCH_STALL, 0x87, 0x00 },
188 { PMC_EV_K8_IC_RETURN_STACK_HIT, 0x88, 0x00 },
189 { PMC_EV_K8_IC_RETURN_STACK_OVERFLOW, 0x89, 0x00 },
191 { PMC_EV_K8_FR_RETIRED_X86_INSTRUCTIONS, 0xC0, 0x00 },
192 { PMC_EV_K8_FR_RETIRED_UOPS, 0xC1, 0x00 },
193 { PMC_EV_K8_FR_RETIRED_BRANCHES, 0xC2, 0x00 },
194 { PMC_EV_K8_FR_RETIRED_BRANCHES_MISPREDICTED, 0xC3, 0x00 },
195 { PMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES, 0xC4, 0x00 },
196 { PMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED, 0xC5, 0x00 },
197 { PMC_EV_K8_FR_RETIRED_FAR_CONTROL_TRANSFERS, 0xC6, 0x00 },
198 { PMC_EV_K8_FR_RETIRED_RESYNCS, 0xC7, 0x00 },
199 { PMC_EV_K8_FR_RETIRED_NEAR_RETURNS, 0xC8, 0x00 },
200 { PMC_EV_K8_FR_RETIRED_NEAR_RETURNS_MISPREDICTED, 0xC9, 0x00 },
201 { PMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED_BY_ADDR_MISCOMPARE,
203 { PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS, 0xCB, 0x0F },
204 { PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS,
206 { PMC_EV_K8_FR_INTERRUPTS_MASKED_CYCLES, 0xCD, 0x00 },
207 { PMC_EV_K8_FR_INTERRUPTS_MASKED_WHILE_PENDING_CYCLES, 0xCE, 0x00 },
208 { PMC_EV_K8_FR_TAKEN_HARDWARE_INTERRUPTS, 0xCF, 0x00 },
210 { PMC_EV_K8_FR_DECODER_EMPTY, 0xD0, 0x00 },
211 { PMC_EV_K8_FR_DISPATCH_STALLS, 0xD1, 0x00 },
212 { PMC_EV_K8_FR_DISPATCH_STALL_FROM_BRANCH_ABORT_TO_RETIRE,
214 { PMC_EV_K8_FR_DISPATCH_STALL_FOR_SERIALIZATION, 0xD3, 0x00 },
215 { PMC_EV_K8_FR_DISPATCH_STALL_FOR_SEGMENT_LOAD, 0xD4, 0x00 },
216 { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_REORDER_BUFFER_IS_FULL,
218 { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_RESERVATION_STATIONS_ARE_FULL,
220 { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_FPU_IS_FULL, 0xD7, 0x00 },
221 { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_LS_IS_FULL, 0xD8, 0x00 },
222 { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_WAITING_FOR_ALL_TO_BE_QUIET,
224 { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_FAR_XFER_OR_RESYNC_BRANCH_PENDING,
226 { PMC_EV_K8_FR_FPU_EXCEPTIONS, 0xDB, 0x0F },
227 { PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR0, 0xDC, 0x00 },
228 { PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR1, 0xDD, 0x00 },
229 { PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR2, 0xDE, 0x00 },
230 { PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR3, 0xDF, 0x00 },
232 { PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT, 0xE0, 0x7 },
233 { PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_TABLE_OVERFLOW, 0xE1, 0x00 },
234 { PMC_EV_K8_NB_MEMORY_CONTROLLER_DRAM_COMMAND_SLOTS_MISSED,
236 { PMC_EV_K8_NB_MEMORY_CONTROLLER_TURNAROUND, 0xE3, 0x07 },
237 { PMC_EV_K8_NB_MEMORY_CONTROLLER_BYPASS_SATURATION, 0xE4, 0x0F },
238 { PMC_EV_K8_NB_SIZED_COMMANDS, 0xEB, 0x7F },
239 { PMC_EV_K8_NB_PROBE_RESULT, 0xEC, 0x0F },
240 { PMC_EV_K8_NB_HT_BUS0_BANDWIDTH, 0xF6, 0x0F },
241 { PMC_EV_K8_NB_HT_BUS1_BANDWIDTH, 0xF7, 0x0F },
242 { PMC_EV_K8_NB_HT_BUS2_BANDWIDTH, 0xF8, 0x0F }
246 const int amd_event_codes_size = nitems(amd_event_codes);
249 * Per-processor information
253 struct pmc_hw pc_amdpmcs[AMD_NPMCS];
256 static struct amd_cpu **amd_pcpu;
259 * read a pmc register
263 amd_read_pmc(int cpu, int ri, pmc_value_t *v)
266 const struct amd_descr *pd;
270 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
271 ("[amd,%d] illegal CPU value %d", __LINE__, cpu));
272 KASSERT(ri >= 0 && ri < AMD_NPMCS,
273 ("[amd,%d] illegal row-index %d", __LINE__, ri));
274 KASSERT(amd_pcpu[cpu],
275 ("[amd,%d] null per-cpu, cpu %d", __LINE__, cpu));
277 pm = amd_pcpu[cpu]->pc_amdpmcs[ri].phw_pmc;
278 pd = &amd_pmcdesc[ri];
281 ("[amd,%d] No owner for HWPMC [cpu%d,pmc%d]", __LINE__,
284 mode = PMC_TO_MODE(pm);
286 PMCDBG2(MDP,REA,1,"amd-read id=%d class=%d", ri, pd->pm_descr.pd_class);
289 KASSERT(pd->pm_descr.pd_class == amd_pmc_class,
290 ("[amd,%d] unknown PMC class (%d)", __LINE__,
291 pd->pm_descr.pd_class));
294 tmp = rdmsr(pd->pm_perfctr); /* RDMSR serializes */
295 PMCDBG2(MDP,REA,2,"amd-read (pre-munge) id=%d -> %jd", ri, tmp);
296 if (PMC_IS_SAMPLING_MODE(mode)) {
297 /* Sign extend 48 bit value to 64 bits. */
298 tmp = (pmc_value_t) (((int64_t) tmp << 16) >> 16);
299 tmp = AMD_PERFCTR_VALUE_TO_RELOAD_COUNT(tmp);
303 PMCDBG2(MDP,REA,2,"amd-read (post-munge) id=%d -> %jd", ri, *v);
313 amd_write_pmc(int cpu, int ri, pmc_value_t v)
315 const struct amd_descr *pd;
319 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
320 ("[amd,%d] illegal CPU value %d", __LINE__, cpu));
321 KASSERT(ri >= 0 && ri < AMD_NPMCS,
322 ("[amd,%d] illegal row-index %d", __LINE__, ri));
324 pm = amd_pcpu[cpu]->pc_amdpmcs[ri].phw_pmc;
325 pd = &amd_pmcdesc[ri];
328 ("[amd,%d] PMC not owned (cpu%d,pmc%d)", __LINE__,
331 mode = PMC_TO_MODE(pm);
334 KASSERT(pd->pm_descr.pd_class == amd_pmc_class,
335 ("[amd,%d] unknown PMC class (%d)", __LINE__,
336 pd->pm_descr.pd_class));
339 /* use 2's complement of the count for sampling mode PMCs */
340 if (PMC_IS_SAMPLING_MODE(mode))
341 v = AMD_RELOAD_COUNT_TO_PERFCTR_VALUE(v);
343 PMCDBG3(MDP,WRI,1,"amd-write cpu=%d ri=%d v=%jx", cpu, ri, v);
345 /* write the PMC value */
346 wrmsr(pd->pm_perfctr, v);
351 * configure hardware pmc according to the configuration recorded in
356 amd_config_pmc(int cpu, int ri, struct pmc *pm)
360 PMCDBG3(MDP,CFG,1, "cpu=%d ri=%d pm=%p", cpu, ri, pm);
362 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
363 ("[amd,%d] illegal CPU value %d", __LINE__, cpu));
364 KASSERT(ri >= 0 && ri < AMD_NPMCS,
365 ("[amd,%d] illegal row-index %d", __LINE__, ri));
367 phw = &amd_pcpu[cpu]->pc_amdpmcs[ri];
369 KASSERT(pm == NULL || phw->phw_pmc == NULL,
370 ("[amd,%d] pm=%p phw->pm=%p hwpmc not unconfigured",
371 __LINE__, pm, phw->phw_pmc));
378 * Retrieve a configured PMC pointer from hardware state.
382 amd_get_config(int cpu, int ri, struct pmc **ppm)
384 *ppm = amd_pcpu[cpu]->pc_amdpmcs[ri].phw_pmc;
390 * Machine dependent actions taken during the context switch in of a
395 amd_switch_in(struct pmc_cpu *pc, struct pmc_process *pp)
399 PMCDBG3(MDP,SWI,1, "pc=%p pp=%p enable-msr=%d", pc, pp,
400 (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS) != 0);
402 /* enable the RDPMC instruction if needed */
403 if (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS)
404 load_cr4(rcr4() | CR4_PCE);
410 * Machine dependent actions taken during the context switch out of a
415 amd_switch_out(struct pmc_cpu *pc, struct pmc_process *pp)
418 (void) pp; /* can be NULL */
420 PMCDBG3(MDP,SWO,1, "pc=%p pp=%p enable-msr=%d", pc, pp, pp ?
421 (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS) == 1 : 0);
423 /* always turn off the RDPMC instruction */
424 load_cr4(rcr4() & ~CR4_PCE);
430 * Check if a given allocation is feasible.
434 amd_allocate_pmc(int cpu, int ri, struct pmc *pm,
435 const struct pmc_op_pmcallocate *a)
438 uint32_t allowed_unitmask, caps, config, unitmask;
440 const struct pmc_descr *pd;
444 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
445 ("[amd,%d] illegal CPU value %d", __LINE__, cpu));
446 KASSERT(ri >= 0 && ri < AMD_NPMCS,
447 ("[amd,%d] illegal row index %d", __LINE__, ri));
449 pd = &amd_pmcdesc[ri].pm_descr;
451 /* check class match */
452 if (pd->pd_class != a->pm_class)
457 PMCDBG2(MDP,ALL,1,"amd-allocate ri=%d caps=0x%x", ri, caps);
459 if ((pd->pd_caps & caps) != caps)
461 if (strlen(pmc_cpuid) != 0) {
462 pm->pm_md.pm_amd.pm_amd_evsel =
463 a->pm_md.pm_amd.pm_amd_config;
464 PMCDBG2(MDP,ALL,2,"amd-allocate ri=%d -> config=0x%x", ri, a->pm_md.pm_amd.pm_amd_config);
470 /* map ev to the correct event mask code */
471 config = allowed_unitmask = 0;
472 for (i = 0; i < amd_event_codes_size; i++)
473 if (amd_event_codes[i].pe_ev == pe) {
475 AMD_PMC_TO_EVENTMASK(amd_event_codes[i].pe_code);
477 AMD_PMC_TO_UNITMASK(amd_event_codes[i].pe_mask);
480 if (i == amd_event_codes_size)
483 unitmask = a->pm_md.pm_amd.pm_amd_config & AMD_PMC_UNITMASK;
484 if (unitmask & ~allowed_unitmask) /* disallow reserved bits */
487 if (unitmask && (caps & PMC_CAP_QUALIFIER))
490 if (caps & PMC_CAP_THRESHOLD)
491 config |= a->pm_md.pm_amd.pm_amd_config & AMD_PMC_COUNTERMASK;
493 /* set at least one of the 'usr' or 'os' caps */
494 if (caps & PMC_CAP_USER)
495 config |= AMD_PMC_USR;
496 if (caps & PMC_CAP_SYSTEM)
497 config |= AMD_PMC_OS;
498 if ((caps & (PMC_CAP_USER|PMC_CAP_SYSTEM)) == 0)
499 config |= (AMD_PMC_USR|AMD_PMC_OS);
501 if (caps & PMC_CAP_EDGE)
502 config |= AMD_PMC_EDGE;
503 if (caps & PMC_CAP_INVERT)
504 config |= AMD_PMC_INVERT;
505 if (caps & PMC_CAP_INTERRUPT)
506 config |= AMD_PMC_INT;
508 pm->pm_md.pm_amd.pm_amd_evsel = config; /* save config value */
510 PMCDBG2(MDP,ALL,2,"amd-allocate ri=%d -> config=0x%x", ri, config);
516 * Release machine dependent state associated with a PMC. This is a
517 * no-op on this architecture.
523 amd_release_pmc(int cpu, int ri, struct pmc *pmc)
526 const struct amd_descr *pd;
532 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
533 ("[amd,%d] illegal CPU value %d", __LINE__, cpu));
534 KASSERT(ri >= 0 && ri < AMD_NPMCS,
535 ("[amd,%d] illegal row-index %d", __LINE__, ri));
537 phw = &amd_pcpu[cpu]->pc_amdpmcs[ri];
539 KASSERT(phw->phw_pmc == NULL,
540 ("[amd,%d] PHW pmc %p non-NULL", __LINE__, phw->phw_pmc));
543 pd = &amd_pmcdesc[ri];
544 if (pd->pm_descr.pd_class == amd_pmc_class)
545 KASSERT(AMD_PMC_IS_STOPPED(pd->pm_evsel),
546 ("[amd,%d] PMC %d released while active", __LINE__, ri));
557 amd_start_pmc(int cpu, int ri)
562 const struct amd_descr *pd;
564 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
565 ("[amd,%d] illegal CPU value %d", __LINE__, cpu));
566 KASSERT(ri >= 0 && ri < AMD_NPMCS,
567 ("[amd,%d] illegal row-index %d", __LINE__, ri));
569 phw = &amd_pcpu[cpu]->pc_amdpmcs[ri];
571 pd = &amd_pmcdesc[ri];
574 ("[amd,%d] starting cpu%d,pmc%d with null pmc record", __LINE__,
577 PMCDBG2(MDP,STA,1,"amd-start cpu=%d ri=%d", cpu, ri);
579 KASSERT(AMD_PMC_IS_STOPPED(pd->pm_evsel),
580 ("[amd,%d] pmc%d,cpu%d: Starting active PMC \"%s\"", __LINE__,
581 ri, cpu, pd->pm_descr.pd_name));
583 /* turn on the PMC ENABLE bit */
584 config = pm->pm_md.pm_amd.pm_amd_evsel | AMD_PMC_ENABLE;
586 PMCDBG1(MDP,STA,2,"amd-start config=0x%x", config);
588 wrmsr(pd->pm_evsel, config);
597 amd_stop_pmc(int cpu, int ri)
601 const struct amd_descr *pd;
604 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
605 ("[amd,%d] illegal CPU value %d", __LINE__, cpu));
606 KASSERT(ri >= 0 && ri < AMD_NPMCS,
607 ("[amd,%d] illegal row-index %d", __LINE__, ri));
609 phw = &amd_pcpu[cpu]->pc_amdpmcs[ri];
611 pd = &amd_pmcdesc[ri];
614 ("[amd,%d] cpu%d,pmc%d no PMC to stop", __LINE__,
616 KASSERT(!AMD_PMC_IS_STOPPED(pd->pm_evsel),
617 ("[amd,%d] PMC%d, CPU%d \"%s\" already stopped",
618 __LINE__, ri, cpu, pd->pm_descr.pd_name));
620 PMCDBG1(MDP,STO,1,"amd-stop ri=%d", ri);
622 /* turn off the PMC ENABLE bit */
623 config = pm->pm_md.pm_amd.pm_amd_evsel & ~AMD_PMC_ENABLE;
624 wrmsr(pd->pm_evsel, config);
629 * Interrupt handler. This function needs to return '1' if the
630 * interrupt was this CPU's PMCs or '0' otherwise. It is not allowed
631 * to sleep or do anything a 'fast' interrupt handler is not allowed
636 amd_intr(struct trapframe *tf)
638 int i, error, retval, cpu;
639 uint32_t config, evsel, perfctr;
645 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
646 ("[amd,%d] out of range CPU %d", __LINE__, cpu));
648 PMCDBG3(MDP,INT,1, "cpu=%d tf=%p um=%d", cpu, (void *) tf,
656 * look for all PMCs that have interrupted:
657 * - look for a running, sampling PMC which has overflowed
658 * and which has a valid 'struct pmc' association
660 * If found, we call a helper to process the interrupt.
662 * If multiple PMCs interrupt at the same time, the AMD64
663 * processor appears to deliver as many NMIs as there are
664 * outstanding PMC interrupts. So we process only one NMI
665 * interrupt at a time.
668 for (i = 0; retval == 0 && i < AMD_NPMCS; i++) {
670 if ((pm = pac->pc_amdpmcs[i].phw_pmc) == NULL ||
671 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) {
675 if (!AMD_PMC_HAS_OVERFLOWED(i))
678 retval = 1; /* Found an interrupting PMC. */
680 if (pm->pm_state != PMC_STATE_RUNNING)
683 /* Stop the PMC, reload count. */
684 evsel = AMD_PMC_EVSEL_0 + i;
685 perfctr = AMD_PMC_PERFCTR_0 + i;
686 v = pm->pm_sc.pm_reloadcount;
687 config = rdmsr(evsel);
689 KASSERT((config & ~AMD_PMC_ENABLE) ==
690 (pm->pm_md.pm_amd.pm_amd_evsel & ~AMD_PMC_ENABLE),
691 ("[amd,%d] config mismatch reg=0x%x pm=0x%x", __LINE__,
692 config, pm->pm_md.pm_amd.pm_amd_evsel));
694 wrmsr(evsel, config & ~AMD_PMC_ENABLE);
695 wrmsr(perfctr, AMD_RELOAD_COUNT_TO_PERFCTR_VALUE(v));
697 /* Restart the counter if logging succeeded. */
698 error = pmc_process_interrupt(PMC_HR, pm, tf);
700 wrmsr(evsel, config);
704 counter_u64_add(pmc_stats.pm_intr_processed, 1);
706 counter_u64_add(pmc_stats.pm_intr_ignored, 1);
708 PMCDBG1(MDP,INT,2, "retval=%d", retval);
716 amd_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
720 const struct amd_descr *pd;
723 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
724 ("[amd,%d] illegal CPU %d", __LINE__, cpu));
725 KASSERT(ri >= 0 && ri < AMD_NPMCS,
726 ("[amd,%d] row-index %d out of range", __LINE__, ri));
728 phw = &amd_pcpu[cpu]->pc_amdpmcs[ri];
729 pd = &amd_pmcdesc[ri];
731 if ((error = copystr(pd->pm_descr.pd_name, pi->pm_name,
732 PMC_NAME_MAX, &copied)) != 0)
735 pi->pm_class = pd->pm_descr.pd_class;
737 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
738 pi->pm_enabled = TRUE;
739 *ppmc = phw->phw_pmc;
741 pi->pm_enabled = FALSE;
749 * i386 specific entry points
753 * return the MSR address of the given PMC.
757 amd_get_msr(int ri, uint32_t *msr)
759 KASSERT(ri >= 0 && ri < AMD_NPMCS,
760 ("[amd,%d] ri %d out of range", __LINE__, ri));
762 *msr = amd_pmcdesc[ri].pm_perfctr - AMD_PMC_PERFCTR_0;
768 * processor dependent initialization.
772 amd_pcpu_init(struct pmc_mdep *md, int cpu)
774 int classindex, first_ri, n;
779 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
780 ("[amd,%d] insane cpu number %d", __LINE__, cpu));
782 PMCDBG1(MDP,INI,1,"amd-init cpu=%d", cpu);
784 amd_pcpu[cpu] = pac = malloc(sizeof(struct amd_cpu), M_PMC,
788 * Set the content of the hardware descriptors to a known
789 * state and initialize pointers in the MI per-cpu descriptor.
792 #if defined(__amd64__)
793 classindex = PMC_MDEP_CLASS_INDEX_K8;
794 #elif defined(__i386__)
795 classindex = md->pmd_cputype == PMC_CPU_AMD_K8 ?
796 PMC_MDEP_CLASS_INDEX_K8 : PMC_MDEP_CLASS_INDEX_K7;
798 first_ri = md->pmd_classdep[classindex].pcd_ri;
800 KASSERT(pc != NULL, ("[amd,%d] NULL per-cpu pointer", __LINE__));
802 for (n = 0, phw = pac->pc_amdpmcs; n < AMD_NPMCS; n++, phw++) {
803 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED |
804 PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(n);
806 pc->pc_hwpmcs[n + first_ri] = phw;
814 * processor dependent cleanup prior to the KLD
819 amd_pcpu_fini(struct pmc_mdep *md, int cpu)
821 int classindex, first_ri, i;
826 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
827 ("[amd,%d] insane cpu number (%d)", __LINE__, cpu));
829 PMCDBG1(MDP,INI,1,"amd-cleanup cpu=%d", cpu);
832 * First, turn off all PMCs on this CPU.
834 for (i = 0; i < 4; i++) { /* XXX this loop is now not needed */
835 evsel = rdmsr(AMD_PMC_EVSEL_0 + i);
836 evsel &= ~AMD_PMC_ENABLE;
837 wrmsr(AMD_PMC_EVSEL_0 + i, evsel);
841 * Next, free up allocated space.
843 if ((pac = amd_pcpu[cpu]) == NULL)
846 amd_pcpu[cpu] = NULL;
849 for (i = 0; i < AMD_NPMCS; i++) {
850 KASSERT(pac->pc_amdpmcs[i].phw_pmc == NULL,
851 ("[amd,%d] CPU%d/PMC%d in use", __LINE__, cpu, i));
852 KASSERT(AMD_PMC_IS_STOPPED(AMD_PMC_EVSEL_0 + i),
853 ("[amd,%d] CPU%d/PMC%d not stopped", __LINE__, cpu, i));
858 KASSERT(pc != NULL, ("[amd,%d] NULL per-cpu state", __LINE__));
860 #if defined(__amd64__)
861 classindex = PMC_MDEP_CLASS_INDEX_K8;
862 #elif defined(__i386__)
863 classindex = md->pmd_cputype == PMC_CPU_AMD_K8 ? PMC_MDEP_CLASS_INDEX_K8 :
864 PMC_MDEP_CLASS_INDEX_K7;
866 first_ri = md->pmd_classdep[classindex].pcd_ri;
869 * Reset pointers in the MI 'per-cpu' state.
871 for (i = 0; i < AMD_NPMCS; i++) {
872 pc->pc_hwpmcs[i + first_ri] = NULL;
882 * Initialize ourselves.
886 pmc_amd_initialize(void)
888 int classindex, error, i, ncpus;
889 struct pmc_classdep *pcd;
890 enum pmc_cputype cputype;
891 struct pmc_mdep *pmc_mdep;
892 enum pmc_class class;
897 * The presence of hardware performance counters on the AMD
898 * Athlon, Duron or later processors, is _not_ indicated by
899 * any of the processor feature flags set by the 'CPUID'
900 * instruction, so we only check the 'instruction family'
901 * field returned by CPUID for instruction family >= 6.
905 model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4);
906 if (CPUID_TO_FAMILY(cpu_id) == 0x17)
907 snprintf(pmc_cpuid, sizeof(pmc_cpuid), "AuthenticAMD-%d-%02X",
908 CPUID_TO_FAMILY(cpu_id), model);
910 switch (cpu_id & 0xF00) {
911 #if defined(__i386__)
912 case 0x600: /* Athlon(tm) processor */
913 classindex = PMC_MDEP_CLASS_INDEX_K7;
914 cputype = PMC_CPU_AMD_K7;
915 class = PMC_CLASS_K7;
919 case 0xF00: /* Athlon64/Opteron processor */
920 classindex = PMC_MDEP_CLASS_INDEX_K8;
921 cputype = PMC_CPU_AMD_K8;
922 class = PMC_CLASS_K8;
927 (void) printf("pmc: Unknown AMD CPU %x %d-%d.\n", cpu_id, (cpu_id & 0xF00) >> 8, model);
932 amd_pmc_class = class;
936 * Allocate space for pointers to PMC HW descriptors and for
937 * the MDEP structure used by MI code.
939 amd_pcpu = malloc(sizeof(struct amd_cpu *) * pmc_cpu_max(), M_PMC,
943 * These processors have two classes of PMCs: the TSC and
946 pmc_mdep = pmc_mdep_alloc(2);
948 pmc_mdep->pmd_cputype = cputype;
950 ncpus = pmc_cpu_max();
952 /* Initialize the TSC. */
953 error = pmc_tsc_initialize(pmc_mdep, ncpus);
957 /* Initialize AMD K7 and K8 PMC handling. */
958 pcd = &pmc_mdep->pmd_classdep[classindex];
960 pcd->pcd_caps = AMD_PMC_CAPS;
961 pcd->pcd_class = class;
962 pcd->pcd_num = AMD_NPMCS;
963 pcd->pcd_ri = pmc_mdep->pmd_npmc;
966 /* fill in the correct pmc name and class */
967 for (i = 0; i < AMD_NPMCS; i++) {
968 (void) snprintf(amd_pmcdesc[i].pm_descr.pd_name,
969 sizeof(amd_pmcdesc[i].pm_descr.pd_name), "%s-%d",
971 amd_pmcdesc[i].pm_descr.pd_class = class;
974 pcd->pcd_allocate_pmc = amd_allocate_pmc;
975 pcd->pcd_config_pmc = amd_config_pmc;
976 pcd->pcd_describe = amd_describe;
977 pcd->pcd_get_config = amd_get_config;
978 pcd->pcd_get_msr = amd_get_msr;
979 pcd->pcd_pcpu_fini = amd_pcpu_fini;
980 pcd->pcd_pcpu_init = amd_pcpu_init;
981 pcd->pcd_read_pmc = amd_read_pmc;
982 pcd->pcd_release_pmc = amd_release_pmc;
983 pcd->pcd_start_pmc = amd_start_pmc;
984 pcd->pcd_stop_pmc = amd_stop_pmc;
985 pcd->pcd_write_pmc = amd_write_pmc;
987 pmc_mdep->pmd_pcpu_init = NULL;
988 pmc_mdep->pmd_pcpu_fini = NULL;
989 pmc_mdep->pmd_intr = amd_intr;
990 pmc_mdep->pmd_switch_in = amd_switch_in;
991 pmc_mdep->pmd_switch_out = amd_switch_out;
993 pmc_mdep->pmd_npmc += AMD_NPMCS;
995 PMCDBG0(MDP,INI,0,"amd-initialize");
1001 free(pmc_mdep, M_PMC);
1009 * Finalization code for AMD CPUs.
1013 pmc_amd_finalize(struct pmc_mdep *md)
1015 #if defined(INVARIANTS)
1016 int classindex, i, ncpus, pmcclass;
1019 pmc_tsc_finalize(md);
1021 KASSERT(amd_pcpu != NULL, ("[amd,%d] NULL per-cpu array pointer",
1024 #if defined(INVARIANTS)
1025 switch (md->pmd_cputype) {
1026 #if defined(__i386__)
1027 case PMC_CPU_AMD_K7:
1028 classindex = PMC_MDEP_CLASS_INDEX_K7;
1029 pmcclass = PMC_CLASS_K7;
1033 classindex = PMC_MDEP_CLASS_INDEX_K8;
1034 pmcclass = PMC_CLASS_K8;
1037 KASSERT(md->pmd_classdep[classindex].pcd_class == pmcclass,
1038 ("[amd,%d] pmc class mismatch", __LINE__));
1040 ncpus = pmc_cpu_max();
1042 for (i = 0; i < ncpus; i++)
1043 KASSERT(amd_pcpu[i] == NULL, ("[amd,%d] non-null pcpu",
1047 free(amd_pcpu, M_PMC);