2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2005, Joseph Koshy
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8 * modification, are permitted provided that the following conditions
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19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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31 /* Machine dependent interfaces */
33 #ifndef _DEV_HWPMC_AMD_H_
34 #define _DEV_HWPMC_AMD_H_ 1
36 /* AMD K7 and K8 PMCs */
38 #define AMD_PMC_EVSEL_0 0xC0010000
39 #define AMD_PMC_EVSEL_1 0xC0010001
40 #define AMD_PMC_EVSEL_2 0xC0010002
41 #define AMD_PMC_EVSEL_3 0xC0010003
43 #define AMD_PMC_PERFCTR_0 0xC0010004
44 #define AMD_PMC_PERFCTR_1 0xC0010005
45 #define AMD_PMC_PERFCTR_2 0xC0010006
46 #define AMD_PMC_PERFCTR_3 0xC0010007
48 #define AMD_PMC_EVSEL_4 0xC0010208
49 #define AMD_PMC_EVSEL_5 0xC001020A
51 #define AMD_PMC_PERFCTR_4 0xC0010209
52 #define AMD_PMC_PERFCTR_5 0xC001020B
54 #define AMD_PMC_EVSEL_EP_L3_0 0xC0010230
55 #define AMD_PMC_EVSEL_EP_L3_1 0xC0010232
56 #define AMD_PMC_EVSEL_EP_L3_2 0xC0010234
57 #define AMD_PMC_EVSEL_EP_L3_3 0xC0010236
58 #define AMD_PMC_EVSEL_EP_L3_4 0xC0010238
59 #define AMD_PMC_EVSEL_EP_L3_5 0xC001023A
61 #define AMD_PMC_PERFCTR_EP_L3_0 0xC0010231
62 #define AMD_PMC_PERFCTR_EP_L3_1 0xC0010233
63 #define AMD_PMC_PERFCTR_EP_L3_2 0xC0010235
64 #define AMD_PMC_PERFCTR_EP_L3_3 0xC0010237
65 #define AMD_PMC_PERFCTR_EP_L3_4 0xC0010239
66 #define AMD_PMC_PERFCTR_EP_L3_5 0xC001023B
68 #define AMD_PMC_EVSEL_EP_DF_0 0xC0010240
69 #define AMD_PMC_EVSEL_EP_DF_1 0xC0010242
70 #define AMD_PMC_EVSEL_EP_DF_2 0xC0010244
71 #define AMD_PMC_EVSEL_EP_DF_3 0xC0010246
73 #define AMD_PMC_PERFCTR_EP_DF_0 0xC0010241
74 #define AMD_PMC_PERFCTR_EP_DF_1 0xC0010243
75 #define AMD_PMC_PERFCTR_EP_DF_2 0xC0010245
76 #define AMD_PMC_PERFCTR_EP_DF_3 0xC0010247
79 #define AMD_CORE_NPMCS 6
82 #define AMD_PMC_COUNTERMASK 0xFF000000
83 #define AMD_PMC_TO_COUNTER(x) (((x) << 24) & AMD_PMC_COUNTERMASK)
84 #define AMD_PMC_INVERT (1 << 23)
85 #define AMD_PMC_ENABLE (1 << 22)
86 #define AMD_PMC_INT (1 << 20)
87 #define AMD_PMC_PC (1 << 19)
88 #define AMD_PMC_EDGE (1 << 18)
89 #define AMD_PMC_OS (1 << 17)
90 #define AMD_PMC_USR (1 << 16)
91 #define AMD_PMC_L3SLICEMASK (0x000F000000000000)
92 #define AMD_PMC_L3COREMASK (0xFF00000000000000)
93 #define AMD_PMC_TO_L3SLICE(x) (((x) << 48) & AMD_PMC_L3SLICEMASK)
94 #define AMD_PMC_TO_L3CORE(x) (((x) << 56) & AMD_PMC_L3COREMASK)
96 #define AMD_PMC_UNITMASK_M 0x10
97 #define AMD_PMC_UNITMASK_O 0x08
98 #define AMD_PMC_UNITMASK_E 0x04
99 #define AMD_PMC_UNITMASK_S 0x02
100 #define AMD_PMC_UNITMASK_I 0x01
101 #define AMD_PMC_UNITMASK_MOESI 0x1F
103 #define AMD_PMC_UNITMASK 0xFF00
104 #define AMD_PMC_EVENTMASK 0xF000000FF
106 #define AMD_PMC_TO_UNITMASK(x) (((x) << 8) & AMD_PMC_UNITMASK)
107 #define AMD_PMC_TO_EVENTMASK(x) (((x) & 0xFF) | (((uint64_t)(x) & 0xF00) << 24))
108 #define AMD_PMC_TO_EVENTMASK_DF(x) (((x) & 0xFF) | (((uint64_t)(x) & 0x0F00) << 24)) | (((uint64_t)(x) & 0x3000) << 47)
109 #define AMD_VALID_BITS (AMD_PMC_COUNTERMASK | AMD_PMC_INVERT | \
110 AMD_PMC_ENABLE | AMD_PMC_INT | AMD_PMC_PC | AMD_PMC_EDGE | \
111 AMD_PMC_OS | AMD_PMC_USR | AMD_PMC_UNITMASK | AMD_PMC_EVENTMASK)
113 #define AMD_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | \
114 PMC_CAP_SYSTEM | PMC_CAP_EDGE | PMC_CAP_THRESHOLD | \
115 PMC_CAP_READ | PMC_CAP_WRITE | PMC_CAP_INVERT | PMC_CAP_QUALIFIER)
117 #define AMD_PMC_IS_STOPPED(evsel) ((rdmsr((evsel)) & AMD_PMC_ENABLE) == 0)
118 #define AMD_PMC_HAS_OVERFLOWED(pmc) ((rdpmc(pmc) & (1ULL << 47)) == 0)
120 #define AMD_RELOAD_COUNT_TO_PERFCTR_VALUE(V) (-(V))
121 #define AMD_PERFCTR_VALUE_TO_RELOAD_COUNT(P) (-(P))
124 PMC_AMD_SUB_CLASS_CORE,
125 PMC_AMD_SUB_CLASS_L3_CACHE,
126 PMC_AMD_SUB_CLASS_DATA_FABRIC
129 struct pmc_md_amd_op_pmcallocate {
130 uint64_t pm_amd_config;
131 uint32_t pm_amd_sub_class;
136 /* MD extension for 'struct pmc' */
137 struct pmc_md_amd_pmc {
138 uint64_t pm_amd_evsel;
142 #endif /* _DEV_HWPMC_AMD_H_ */