2 * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com>
5 * This software was developed by the University of Cambridge Computer
6 * Laboratory with support from ARM Ltd.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
36 #include <sys/pmckern.h>
38 #include <machine/pmc_mdep.h>
39 #include <machine/cpu.h>
41 static int arm64_npmcs;
43 struct arm64_event_code_map {
49 * Per-processor information.
52 struct pmc_hw *pc_arm64pmcs;
55 static struct arm64_cpu **arm64_pcpu;
58 * Interrupt Enable Set Register
61 arm64_interrupt_enable(uint32_t pmc)
66 WRITE_SPECIALREG(pmintenset_el1, reg);
72 * Interrupt Clear Set Register
75 arm64_interrupt_disable(uint32_t pmc)
80 WRITE_SPECIALREG(pmintenclr_el1, reg);
86 * Counter Set Enable Register
89 arm64_counter_enable(unsigned int pmc)
94 WRITE_SPECIALREG(pmcntenset_el0, reg);
100 * Counter Clear Enable Register
103 arm64_counter_disable(unsigned int pmc)
108 WRITE_SPECIALREG(pmcntenclr_el0, reg);
114 * Performance Monitors Control Register
117 arm64_pmcr_read(void)
121 reg = READ_SPECIALREG(pmcr_el0);
127 arm64_pmcr_write(uint32_t reg)
130 WRITE_SPECIALREG(pmcr_el0, reg);
136 * Performance Count Register N
139 arm64_pmcn_read(unsigned int pmc)
142 KASSERT(pmc < arm64_npmcs, ("%s: illegal PMC number %d", __func__, pmc));
144 WRITE_SPECIALREG(pmselr_el0, pmc);
148 return (READ_SPECIALREG(pmxevcntr_el0));
152 arm64_pmcn_write(unsigned int pmc, uint32_t reg)
155 KASSERT(pmc < arm64_npmcs, ("%s: illegal PMC number %d", __func__, pmc));
157 WRITE_SPECIALREG(pmselr_el0, pmc);
158 WRITE_SPECIALREG(pmxevcntr_el0, reg);
164 arm64_allocate_pmc(int cpu, int ri, struct pmc *pm,
165 const struct pmc_op_pmcallocate *a)
168 struct arm64_cpu *pac;
171 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
172 ("[arm64,%d] illegal CPU value %d", __LINE__, cpu));
173 KASSERT(ri >= 0 && ri < arm64_npmcs,
174 ("[arm64,%d] illegal row index %d", __LINE__, ri));
176 pac = arm64_pcpu[cpu];
178 if (a->pm_class != PMC_CLASS_ARMV8) {
183 /* Adjust the config value if needed. */
184 config = a->pm_md.pm_md_config;
185 if ((a->pm_md.pm_md_flags & PM_MD_RAW_EVENT) == 0) {
186 config = (uint32_t)pe - PMC_EV_ARMV8_FIRST;
187 if (config > (PMC_EV_ARMV8_LAST - PMC_EV_ARMV8_FIRST))
190 pm->pm_md.pm_arm64.pm_arm64_evsel = config;
191 PMCDBG2(MDP, ALL, 2, "arm64-allocate ri=%d -> config=0x%x", ri, config);
198 arm64_read_pmc(int cpu, int ri, pmc_value_t *v)
205 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
206 ("[arm64,%d] illegal CPU value %d", __LINE__, cpu));
207 KASSERT(ri >= 0 && ri < arm64_npmcs,
208 ("[arm64,%d] illegal row index %d", __LINE__, ri));
210 pm = arm64_pcpu[cpu]->pc_arm64pmcs[ri].phw_pmc;
213 * Ensure we don't get interrupted while updating the overflow count.
216 tmp = arm64_pmcn_read(ri);
218 if ((READ_SPECIALREG(pmovsclr_el0) & reg) != 0) {
219 /* Clear Overflow Flag */
220 WRITE_SPECIALREG(pmovsclr_el0, reg);
221 if (!PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
222 pm->pm_pcpu_state[cpu].pps_overflowcnt++;
224 /* Reread counter in case we raced. */
225 tmp = arm64_pmcn_read(ri);
227 tmp += 0x100000000llu * pm->pm_pcpu_state[cpu].pps_overflowcnt;
230 PMCDBG2(MDP, REA, 2, "arm64-read id=%d -> %jd", ri, tmp);
231 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
232 *v = ARMV8_PERFCTR_VALUE_TO_RELOAD_COUNT(tmp);
240 arm64_write_pmc(int cpu, int ri, pmc_value_t v)
244 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
245 ("[arm64,%d] illegal CPU value %d", __LINE__, cpu));
246 KASSERT(ri >= 0 && ri < arm64_npmcs,
247 ("[arm64,%d] illegal row-index %d", __LINE__, ri));
249 pm = arm64_pcpu[cpu]->pc_arm64pmcs[ri].phw_pmc;
251 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
252 v = ARMV8_RELOAD_COUNT_TO_PERFCTR_VALUE(v);
254 PMCDBG3(MDP, WRI, 1, "arm64-write cpu=%d ri=%d v=%jx", cpu, ri, v);
256 pm->pm_pcpu_state[cpu].pps_overflowcnt = v >> 32;
257 arm64_pmcn_write(ri, v);
263 arm64_config_pmc(int cpu, int ri, struct pmc *pm)
267 PMCDBG3(MDP, CFG, 1, "cpu=%d ri=%d pm=%p", cpu, ri, pm);
269 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
270 ("[arm64,%d] illegal CPU value %d", __LINE__, cpu));
271 KASSERT(ri >= 0 && ri < arm64_npmcs,
272 ("[arm64,%d] illegal row-index %d", __LINE__, ri));
274 phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri];
276 KASSERT(pm == NULL || phw->phw_pmc == NULL,
277 ("[arm64,%d] pm=%p phw->pm=%p hwpmc not unconfigured",
278 __LINE__, pm, phw->phw_pmc));
286 arm64_start_pmc(int cpu, int ri)
292 phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri];
294 config = pm->pm_md.pm_arm64.pm_arm64_evsel;
297 * Configure the event selection.
299 WRITE_SPECIALREG(pmselr_el0, ri);
300 WRITE_SPECIALREG(pmxevtyper_el0, config);
307 arm64_interrupt_enable(ri);
308 arm64_counter_enable(ri);
314 arm64_stop_pmc(int cpu, int ri)
319 phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri];
325 arm64_counter_disable(ri);
326 arm64_interrupt_disable(ri);
332 arm64_release_pmc(int cpu, int ri, struct pmc *pmc)
336 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
337 ("[arm64,%d] illegal CPU value %d", __LINE__, cpu));
338 KASSERT(ri >= 0 && ri < arm64_npmcs,
339 ("[arm64,%d] illegal row-index %d", __LINE__, ri));
341 phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri];
342 KASSERT(phw->phw_pmc == NULL,
343 ("[arm64,%d] PHW pmc %p non-NULL", __LINE__, phw->phw_pmc));
349 arm64_intr(struct trapframe *tf)
351 struct arm64_cpu *pc;
358 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
359 ("[arm64,%d] CPU %d out of range", __LINE__, cpu));
361 PMCDBG3(MDP,INT,1, "cpu=%d tf=%p um=%d", cpu, (void *)tf,
365 pc = arm64_pcpu[cpu];
367 for (ri = 0; ri < arm64_npmcs; ri++) {
368 pm = arm64_pcpu[cpu]->pc_arm64pmcs[ri].phw_pmc;
371 /* Check if counter is overflowed */
373 if ((READ_SPECIALREG(pmovsclr_el0) & reg) == 0)
375 /* Clear Overflow Flag */
376 WRITE_SPECIALREG(pmovsclr_el0, reg);
380 retval = 1; /* Found an interrupting PMC. */
382 if (!PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) {
383 pm->pm_pcpu_state[cpu].pps_overflowcnt += 1;
387 if (pm->pm_state != PMC_STATE_RUNNING)
390 error = pmc_process_interrupt(PMC_HR, pm, tf);
392 arm64_stop_pmc(cpu, ri);
394 /* Reload sampling count */
395 arm64_write_pmc(cpu, ri, pm->pm_sc.pm_reloadcount);
402 arm64_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
404 char arm64_name[PMC_NAME_MAX];
408 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
409 ("[arm64,%d], illegal CPU %d", __LINE__, cpu));
410 KASSERT(ri >= 0 && ri < arm64_npmcs,
411 ("[arm64,%d] row-index %d out of range", __LINE__, ri));
413 phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri];
414 snprintf(arm64_name, sizeof(arm64_name), "ARMV8-%d", ri);
415 if ((error = copystr(arm64_name, pi->pm_name, PMC_NAME_MAX,
418 pi->pm_class = PMC_CLASS_ARMV8;
419 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
420 pi->pm_enabled = TRUE;
421 *ppmc = phw->phw_pmc;
423 pi->pm_enabled = FALSE;
431 arm64_get_config(int cpu, int ri, struct pmc **ppm)
434 *ppm = arm64_pcpu[cpu]->pc_arm64pmcs[ri].phw_pmc;
440 * XXX don't know what we should do here.
443 arm64_switch_in(struct pmc_cpu *pc, struct pmc_process *pp)
450 arm64_switch_out(struct pmc_cpu *pc, struct pmc_process *pp)
457 arm64_pcpu_init(struct pmc_mdep *md, int cpu)
459 struct arm64_cpu *pac;
466 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
467 ("[arm64,%d] wrong cpu number %d", __LINE__, cpu));
468 PMCDBG1(MDP, INI, 1, "arm64-init cpu=%d", cpu);
470 arm64_pcpu[cpu] = pac = malloc(sizeof(struct arm64_cpu), M_PMC,
473 pac->pc_arm64pmcs = malloc(sizeof(struct pmc_hw) * arm64_npmcs,
474 M_PMC, M_WAITOK | M_ZERO);
476 first_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_ARMV8].pcd_ri;
477 KASSERT(pc != NULL, ("[arm64,%d] NULL per-cpu pointer", __LINE__));
479 for (i = 0, phw = pac->pc_arm64pmcs; i < arm64_npmcs; i++, phw++) {
480 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED |
481 PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(i);
483 pc->pc_hwpmcs[i + first_ri] = phw;
487 * Disable all counters and overflow interrupts. Upon reset they are in
488 * an undefined state.
490 * Don't issue an isb here, just wait for the one in arm64_pmcr_write()
491 * to make the writes visible.
493 WRITE_SPECIALREG(pmcntenclr_el0, 0xffffffff);
494 WRITE_SPECIALREG(pmintenclr_el1, 0xffffffff);
497 pmcr = arm64_pmcr_read();
499 arm64_pmcr_write(pmcr);
505 arm64_pcpu_fini(struct pmc_mdep *md, int cpu)
509 pmcr = arm64_pmcr_read();
511 arm64_pmcr_write(pmcr);
517 pmc_arm64_initialize()
519 struct pmc_mdep *pmc_mdep;
520 struct pmc_classdep *pcd;
525 reg = arm64_pmcr_read();
526 arm64_npmcs = (reg & PMCR_N_MASK) >> PMCR_N_SHIFT;
527 impcode = (reg & PMCR_IMP_MASK) >> PMCR_IMP_SHIFT;
528 idcode = (reg & PMCR_IDCODE_MASK) >> PMCR_IDCODE_SHIFT;
530 PMCDBG1(MDP, INI, 1, "arm64-init npmcs=%d", arm64_npmcs);
533 * Write the CPU model to kern.hwpmc.cpuid.
535 * We zero the variant and revision fields.
537 * TODO: how to handle differences between cores due to big.LITTLE?
538 * For now, just use MIDR from CPU 0.
540 midr = (uint64_t)(pcpu_find(0)->pc_midr);
541 midr &= ~(CPU_VAR_MASK | CPU_REV_MASK);
542 snprintf(pmc_cpuid, sizeof(pmc_cpuid), "0x%016lx", midr);
545 * Allocate space for pointers to PMC HW descriptors and for
546 * the MDEP structure used by MI code.
548 arm64_pcpu = malloc(sizeof(struct arm64_cpu *) * pmc_cpu_max(),
549 M_PMC, M_WAITOK | M_ZERO);
552 pmc_mdep = pmc_mdep_alloc(1);
557 case PMCR_IDCODE_CORTEX_A76:
558 case PMCR_IDCODE_NEOVERSE_N1:
559 pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A76;
561 case PMCR_IDCODE_CORTEX_A57:
562 case PMCR_IDCODE_CORTEX_A72:
563 pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A57;
566 case PMCR_IDCODE_CORTEX_A53:
567 pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A53;
572 pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A53;
576 pcd = &pmc_mdep->pmd_classdep[PMC_MDEP_CLASS_INDEX_ARMV8];
577 pcd->pcd_caps = ARMV8_PMC_CAPS;
578 pcd->pcd_class = PMC_CLASS_ARMV8;
579 pcd->pcd_num = arm64_npmcs;
580 pcd->pcd_ri = pmc_mdep->pmd_npmc;
583 pcd->pcd_allocate_pmc = arm64_allocate_pmc;
584 pcd->pcd_config_pmc = arm64_config_pmc;
585 pcd->pcd_pcpu_fini = arm64_pcpu_fini;
586 pcd->pcd_pcpu_init = arm64_pcpu_init;
587 pcd->pcd_describe = arm64_describe;
588 pcd->pcd_get_config = arm64_get_config;
589 pcd->pcd_read_pmc = arm64_read_pmc;
590 pcd->pcd_release_pmc = arm64_release_pmc;
591 pcd->pcd_start_pmc = arm64_start_pmc;
592 pcd->pcd_stop_pmc = arm64_stop_pmc;
593 pcd->pcd_write_pmc = arm64_write_pmc;
595 pmc_mdep->pmd_intr = arm64_intr;
596 pmc_mdep->pmd_switch_in = arm64_switch_in;
597 pmc_mdep->pmd_switch_out = arm64_switch_out;
599 pmc_mdep->pmd_npmc += arm64_npmcs;
605 pmc_arm64_finalize(struct pmc_mdep *md)