2 * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com>
5 * This software was developed by the University of Cambridge Computer
6 * Laboratory with support from ARM Ltd.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
36 #include <sys/pmckern.h>
38 #include <machine/pmc_mdep.h>
39 #include <machine/cpu.h>
41 static int arm64_npmcs;
43 struct arm64_event_code_map {
49 * Per-processor information.
52 struct pmc_hw *pc_arm64pmcs;
55 static struct arm64_cpu **arm64_pcpu;
58 * Interrupt Enable Set Register
61 arm64_interrupt_enable(uint32_t pmc)
66 WRITE_SPECIALREG(PMINTENSET_EL1, reg);
72 * Interrupt Clear Set Register
75 arm64_interrupt_disable(uint32_t pmc)
80 WRITE_SPECIALREG(PMINTENCLR_EL1, reg);
86 * Counter Set Enable Register
89 arm64_counter_enable(unsigned int pmc)
94 WRITE_SPECIALREG(PMCNTENSET_EL0, reg);
100 * Counter Clear Enable Register
103 arm64_counter_disable(unsigned int pmc)
108 WRITE_SPECIALREG(PMCNTENCLR_EL0, reg);
114 * Performance Monitors Control Register
117 arm64_pmcr_read(void)
121 reg = READ_SPECIALREG(PMCR_EL0);
127 arm64_pmcr_write(uint32_t reg)
130 WRITE_SPECIALREG(PMCR_EL0, reg);
136 * Performance Count Register N
139 arm64_pmcn_read(unsigned int pmc)
142 KASSERT(pmc < arm64_npmcs, ("%s: illegal PMC number %d", __func__, pmc));
144 WRITE_SPECIALREG(PMSELR_EL0, pmc);
148 return (READ_SPECIALREG(PMXEVCNTR_EL0));
152 arm64_pmcn_write(unsigned int pmc, uint32_t reg)
155 KASSERT(pmc < arm64_npmcs, ("%s: illegal PMC number %d", __func__, pmc));
157 WRITE_SPECIALREG(PMSELR_EL0, pmc);
158 WRITE_SPECIALREG(PMXEVCNTR_EL0, reg);
164 arm64_allocate_pmc(int cpu, int ri, struct pmc *pm,
165 const struct pmc_op_pmcallocate *a)
167 uint32_t caps, config;
168 struct arm64_cpu *pac;
171 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
172 ("[arm64,%d] illegal CPU value %d", __LINE__, cpu));
173 KASSERT(ri >= 0 && ri < arm64_npmcs,
174 ("[arm64,%d] illegal row index %d", __LINE__, ri));
176 pac = arm64_pcpu[cpu];
179 if (a->pm_class != PMC_CLASS_ARMV8) {
184 config = (pe & EVENT_ID_MASK);
185 pm->pm_md.pm_arm64.pm_arm64_evsel = config;
187 PMCDBG2(MDP, ALL, 2, "arm64-allocate ri=%d -> config=0x%x", ri, config);
194 arm64_read_pmc(int cpu, int ri, pmc_value_t *v)
199 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
200 ("[arm64,%d] illegal CPU value %d", __LINE__, cpu));
201 KASSERT(ri >= 0 && ri < arm64_npmcs,
202 ("[arm64,%d] illegal row index %d", __LINE__, ri));
204 pm = arm64_pcpu[cpu]->pc_arm64pmcs[ri].phw_pmc;
206 tmp = arm64_pmcn_read(ri);
208 PMCDBG2(MDP, REA, 2, "arm64-read id=%d -> %jd", ri, tmp);
209 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
210 *v = ARMV8_PERFCTR_VALUE_TO_RELOAD_COUNT(tmp);
218 arm64_write_pmc(int cpu, int ri, pmc_value_t v)
222 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
223 ("[arm64,%d] illegal CPU value %d", __LINE__, cpu));
224 KASSERT(ri >= 0 && ri < arm64_npmcs,
225 ("[arm64,%d] illegal row-index %d", __LINE__, ri));
227 pm = arm64_pcpu[cpu]->pc_arm64pmcs[ri].phw_pmc;
229 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
230 v = ARMV8_RELOAD_COUNT_TO_PERFCTR_VALUE(v);
232 PMCDBG3(MDP, WRI, 1, "arm64-write cpu=%d ri=%d v=%jx", cpu, ri, v);
234 arm64_pmcn_write(ri, v);
240 arm64_config_pmc(int cpu, int ri, struct pmc *pm)
244 PMCDBG3(MDP, CFG, 1, "cpu=%d ri=%d pm=%p", cpu, ri, pm);
246 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
247 ("[arm64,%d] illegal CPU value %d", __LINE__, cpu));
248 KASSERT(ri >= 0 && ri < arm64_npmcs,
249 ("[arm64,%d] illegal row-index %d", __LINE__, ri));
251 phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri];
253 KASSERT(pm == NULL || phw->phw_pmc == NULL,
254 ("[arm64,%d] pm=%p phw->pm=%p hwpmc not unconfigured",
255 __LINE__, pm, phw->phw_pmc));
263 arm64_start_pmc(int cpu, int ri)
269 phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri];
271 config = pm->pm_md.pm_arm64.pm_arm64_evsel;
274 * Configure the event selection.
276 WRITE_SPECIALREG(PMSELR_EL0, ri);
277 WRITE_SPECIALREG(PMXEVTYPER_EL0, config);
284 arm64_interrupt_enable(ri);
285 arm64_counter_enable(ri);
291 arm64_stop_pmc(int cpu, int ri)
296 phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri];
302 arm64_counter_disable(ri);
303 arm64_interrupt_disable(ri);
309 arm64_release_pmc(int cpu, int ri, struct pmc *pmc)
313 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
314 ("[arm64,%d] illegal CPU value %d", __LINE__, cpu));
315 KASSERT(ri >= 0 && ri < arm64_npmcs,
316 ("[arm64,%d] illegal row-index %d", __LINE__, ri));
318 phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri];
319 KASSERT(phw->phw_pmc == NULL,
320 ("[arm64,%d] PHW pmc %p non-NULL", __LINE__, phw->phw_pmc));
326 arm64_intr(int cpu, struct trapframe *tf)
328 struct arm64_cpu *pc;
334 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
335 ("[arm64,%d] CPU %d out of range", __LINE__, cpu));
338 pc = arm64_pcpu[cpu];
340 for (ri = 0; ri < arm64_npmcs; ri++) {
341 pm = arm64_pcpu[cpu]->pc_arm64pmcs[ri].phw_pmc;
344 if (!PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
347 /* Check if counter is overflowed */
349 if ((READ_SPECIALREG(PMOVSCLR_EL0) & reg) == 0)
351 /* Clear Overflow Flag */
352 WRITE_SPECIALREG(PMOVSCLR_EL0, reg);
356 retval = 1; /* Found an interrupting PMC. */
357 if (pm->pm_state != PMC_STATE_RUNNING)
360 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf,
363 arm64_stop_pmc(cpu, ri);
365 /* Reload sampling count */
366 arm64_write_pmc(cpu, ri, pm->pm_sc.pm_reloadcount);
373 arm64_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
375 char arm64_name[PMC_NAME_MAX];
379 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
380 ("[arm64,%d], illegal CPU %d", __LINE__, cpu));
381 KASSERT(ri >= 0 && ri < arm64_npmcs,
382 ("[arm64,%d] row-index %d out of range", __LINE__, ri));
384 phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri];
385 snprintf(arm64_name, sizeof(arm64_name), "ARMV8-%d", ri);
386 if ((error = copystr(arm64_name, pi->pm_name, PMC_NAME_MAX,
389 pi->pm_class = PMC_CLASS_ARMV8;
390 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
391 pi->pm_enabled = TRUE;
392 *ppmc = phw->phw_pmc;
394 pi->pm_enabled = FALSE;
402 arm64_get_config(int cpu, int ri, struct pmc **ppm)
405 *ppm = arm64_pcpu[cpu]->pc_arm64pmcs[ri].phw_pmc;
411 * XXX don't know what we should do here.
414 arm64_switch_in(struct pmc_cpu *pc, struct pmc_process *pp)
421 arm64_switch_out(struct pmc_cpu *pc, struct pmc_process *pp)
428 arm64_pcpu_init(struct pmc_mdep *md, int cpu)
430 struct arm64_cpu *pac;
437 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
438 ("[arm64,%d] wrong cpu number %d", __LINE__, cpu));
439 PMCDBG1(MDP, INI, 1, "arm64-init cpu=%d", cpu);
441 arm64_pcpu[cpu] = pac = malloc(sizeof(struct arm64_cpu), M_PMC,
444 pac->pc_arm64pmcs = malloc(sizeof(struct pmc_hw) * arm64_npmcs,
445 M_PMC, M_WAITOK | M_ZERO);
447 first_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_ARMV8].pcd_ri;
448 KASSERT(pc != NULL, ("[arm64,%d] NULL per-cpu pointer", __LINE__));
450 for (i = 0, phw = pac->pc_arm64pmcs; i < arm64_npmcs; i++, phw++) {
451 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED |
452 PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(i);
454 pc->pc_hwpmcs[i + first_ri] = phw;
458 pmcr = arm64_pmcr_read();
460 arm64_pmcr_write(pmcr);
466 arm64_pcpu_fini(struct pmc_mdep *md, int cpu)
470 pmcr = arm64_pmcr_read();
472 arm64_pmcr_write(pmcr);
478 pmc_arm64_initialize()
480 struct pmc_mdep *pmc_mdep;
481 struct pmc_classdep *pcd;
485 reg = arm64_pmcr_read();
486 arm64_npmcs = (reg & PMCR_N_MASK) >> PMCR_N_SHIFT;
487 idcode = (reg & PMCR_IDCODE_MASK) >> PMCR_IDCODE_SHIFT;
489 PMCDBG1(MDP, INI, 1, "arm64-init npmcs=%d", arm64_npmcs);
492 * Allocate space for pointers to PMC HW descriptors and for
493 * the MDEP structure used by MI code.
495 arm64_pcpu = malloc(sizeof(struct arm64_cpu *) * pmc_cpu_max(),
496 M_PMC, M_WAITOK | M_ZERO);
499 pmc_mdep = pmc_mdep_alloc(1);
502 case PMCR_IDCODE_CORTEX_A57:
503 case PMCR_IDCODE_CORTEX_A72:
504 pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A57;
507 case PMCR_IDCODE_CORTEX_A53:
508 pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A53;
512 pcd = &pmc_mdep->pmd_classdep[PMC_MDEP_CLASS_INDEX_ARMV8];
513 pcd->pcd_caps = ARMV8_PMC_CAPS;
514 pcd->pcd_class = PMC_CLASS_ARMV8;
515 pcd->pcd_num = arm64_npmcs;
516 pcd->pcd_ri = pmc_mdep->pmd_npmc;
519 pcd->pcd_allocate_pmc = arm64_allocate_pmc;
520 pcd->pcd_config_pmc = arm64_config_pmc;
521 pcd->pcd_pcpu_fini = arm64_pcpu_fini;
522 pcd->pcd_pcpu_init = arm64_pcpu_init;
523 pcd->pcd_describe = arm64_describe;
524 pcd->pcd_get_config = arm64_get_config;
525 pcd->pcd_read_pmc = arm64_read_pmc;
526 pcd->pcd_release_pmc = arm64_release_pmc;
527 pcd->pcd_start_pmc = arm64_start_pmc;
528 pcd->pcd_stop_pmc = arm64_stop_pmc;
529 pcd->pcd_write_pmc = arm64_write_pmc;
531 pmc_mdep->pmd_intr = arm64_intr;
532 pmc_mdep->pmd_switch_in = arm64_switch_in;
533 pmc_mdep->pmd_switch_out = arm64_switch_out;
535 pmc_mdep->pmd_npmc += arm64_npmcs;
541 pmc_arm64_finalize(struct pmc_mdep *md)