sys/dev/hwpmc/hwpmc_arm64.c

   1 /*-
   2  * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com>
   3  * All rights reserved.
   4  *
   5  * This software was developed by the University of Cambridge Computer
   6  * Laboratory with support from ARM Ltd.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  27  * SUCH DAMAGE.
  28  */
  29
  30 #include <sys/cdefs.h>
  31 __FBSDID("$FreeBSD$");
  32
  33 #include <sys/param.h>
  34 #include <sys/systm.h>
  35 #include <sys/pmc.h>
  36 #include <sys/pmckern.h>
  37
  38 #include <machine/pmc_mdep.h>
  39 #include <machine/cpu.h>
  40
  41 static int arm64_npmcs;
  42
  43 struct arm64_event_code_map {
  44         enum pmc_event  pe_ev;
  45         uint8_t         pe_code;
  46 };
  47
  48 /*
  49  * Per-processor information.
  50  */
  51 struct arm64_cpu {
  52         struct pmc_hw   *pc_arm64pmcs;
  53 };
  54
  55 static struct arm64_cpu **arm64_pcpu;
  56
  57 /*
  58  * Interrupt Enable Set Register
  59  */
  60 static __inline void
  61 arm64_interrupt_enable(uint32_t pmc)
  62 {
  63         uint32_t reg;
  64
  65         reg = (1 << pmc);
  66         WRITE_SPECIALREG(pmintenset_el1, reg);
  67
  68         isb();
  69 }
  70
  71 /*
  72  * Interrupt Clear Set Register
  73  */
  74 static __inline void
  75 arm64_interrupt_disable(uint32_t pmc)
  76 {
  77         uint32_t reg;
  78
  79         reg = (1 << pmc);
  80         WRITE_SPECIALREG(pmintenclr_el1, reg);
  81
  82         isb();
  83 }
  84
  85 /*
  86  * Counter Set Enable Register
  87  */
  88 static __inline void
  89 arm64_counter_enable(unsigned int pmc)
  90 {
  91         uint32_t reg;
  92
  93         reg = (1 << pmc);
  94         WRITE_SPECIALREG(pmcntenset_el0, reg);
  95
  96         isb();
  97 }
  98
  99 /*
 100  * Counter Clear Enable Register
 101  */
 102 static __inline void
 103 arm64_counter_disable(unsigned int pmc)
 104 {
 105         uint32_t reg;
 106
 107         reg = (1 << pmc);
 108         WRITE_SPECIALREG(pmcntenclr_el0, reg);
 109
 110         isb();
 111 }
 112
 113 /*
 114  * Performance Monitors Control Register
 115  */
 116 static uint32_t
 117 arm64_pmcr_read(void)
 118 {
 119         uint32_t reg;
 120
 121         reg = READ_SPECIALREG(pmcr_el0);
 122
 123         return (reg);
 124 }
 125
 126 static void
 127 arm64_pmcr_write(uint32_t reg)
 128 {
 129
 130         WRITE_SPECIALREG(pmcr_el0, reg);
 131
 132         isb();
 133 }
 134
 135 /*
 136  * Performance Count Register N
 137  */
 138 static uint32_t
 139 arm64_pmcn_read(unsigned int pmc)
 140 {
 141
 142         KASSERT(pmc < arm64_npmcs, ("%s: illegal PMC number %d", __func__, pmc));
 143
 144         WRITE_SPECIALREG(pmselr_el0, pmc);
 145
 146         isb();
 147
 148         return (READ_SPECIALREG(pmxevcntr_el0));
 149 }
 150
 151 static void
 152 arm64_pmcn_write(unsigned int pmc, uint32_t reg)
 153 {
 154
 155         KASSERT(pmc < arm64_npmcs, ("%s: illegal PMC number %d", __func__, pmc));
 156
 157         WRITE_SPECIALREG(pmselr_el0, pmc);
 158         WRITE_SPECIALREG(pmxevcntr_el0, reg);
 159
 160         isb();
 161 }
 162
 163 static int
 164 arm64_allocate_pmc(int cpu, int ri, struct pmc *pm,
 165   const struct pmc_op_pmcallocate *a)
 166 {
 167         uint32_t caps, config;
 168         struct arm64_cpu *pac;
 169         enum pmc_event pe;
 170
 171         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 172             ("[arm64,%d] illegal CPU value %d", __LINE__, cpu));
 173         KASSERT(ri >= 0 && ri < arm64_npmcs,
 174             ("[arm64,%d] illegal row index %d", __LINE__, ri));
 175
 176         pac = arm64_pcpu[cpu];
 177
 178         caps = a->pm_caps;
 179         if (a->pm_class != PMC_CLASS_ARMV8) {
 180                 return (EINVAL);
 181         }
 182         pe = a->pm_ev;
 183
 184         config = (pe & EVENT_ID_MASK);
 185         pm->pm_md.pm_arm64.pm_arm64_evsel = config;
 186
 187         PMCDBG2(MDP, ALL, 2, "arm64-allocate ri=%d -> config=0x%x", ri, config);
 188
 189         return 0;
 190 }
 191
 192
 193 static int
 194 arm64_read_pmc(int cpu, int ri, pmc_value_t *v)
 195 {
 196         pmc_value_t tmp;
 197         struct pmc *pm;
 198         register_t s;
 199         int reg;
 200
 201         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 202             ("[arm64,%d] illegal CPU value %d", __LINE__, cpu));
 203         KASSERT(ri >= 0 && ri < arm64_npmcs,
 204             ("[arm64,%d] illegal row index %d", __LINE__, ri));
 205
 206         pm  = arm64_pcpu[cpu]->pc_arm64pmcs[ri].phw_pmc;
 207
 208         /*
 209          * Ensure we don't get interrupted while updating the overflow count.
 210          */
 211         s = intr_disable();
 212         tmp = arm64_pmcn_read(ri);
 213         reg = (1 << ri);
 214         if ((READ_SPECIALREG(pmovsclr_el0) & reg) != 0) {
 215                 /* Clear Overflow Flag */
 216                 WRITE_SPECIALREG(pmovsclr_el0, reg);
 217                 if (!PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
 218                         pm->pm_pcpu_state[cpu].pps_overflowcnt++;
 219
 220                 /* Reread counter in case we raced. */
 221                 tmp = arm64_pmcn_read(ri);
 222         }
 223         tmp += 0x100000000llu * pm->pm_pcpu_state[cpu].pps_overflowcnt;
 224         intr_restore(s);
 225
 226         PMCDBG2(MDP, REA, 2, "arm64-read id=%d -> %jd", ri, tmp);
 227         if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
 228                 *v = ARMV8_PERFCTR_VALUE_TO_RELOAD_COUNT(tmp);
 229         else
 230                 *v = tmp;
 231
 232         return 0;
 233 }
 234
 235 static int
 236 arm64_write_pmc(int cpu, int ri, pmc_value_t v)
 237 {
 238         struct pmc *pm;
 239
 240         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 241             ("[arm64,%d] illegal CPU value %d", __LINE__, cpu));
 242         KASSERT(ri >= 0 && ri < arm64_npmcs,
 243             ("[arm64,%d] illegal row-index %d", __LINE__, ri));
 244
 245         pm  = arm64_pcpu[cpu]->pc_arm64pmcs[ri].phw_pmc;
 246
 247         if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
 248                 v = ARMV8_RELOAD_COUNT_TO_PERFCTR_VALUE(v);
 249
 250         PMCDBG3(MDP, WRI, 1, "arm64-write cpu=%d ri=%d v=%jx", cpu, ri, v);
 251
 252         pm->pm_pcpu_state[cpu].pps_overflowcnt = v >> 32;
 253         arm64_pmcn_write(ri, v);
 254
 255         return 0;
 256 }
 257
 258 static int
 259 arm64_config_pmc(int cpu, int ri, struct pmc *pm)
 260 {
 261         struct pmc_hw *phw;
 262
 263         PMCDBG3(MDP, CFG, 1, "cpu=%d ri=%d pm=%p", cpu, ri, pm);
 264
 265         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 266             ("[arm64,%d] illegal CPU value %d", __LINE__, cpu));
 267         KASSERT(ri >= 0 && ri < arm64_npmcs,
 268             ("[arm64,%d] illegal row-index %d", __LINE__, ri));
 269
 270         phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri];
 271
 272         KASSERT(pm == NULL || phw->phw_pmc == NULL,
 273             ("[arm64,%d] pm=%p phw->pm=%p hwpmc not unconfigured",
 274             __LINE__, pm, phw->phw_pmc));
 275
 276         phw->phw_pmc = pm;
 277
 278         return 0;
 279 }
 280
 281 static int
 282 arm64_start_pmc(int cpu, int ri)
 283 {
 284         struct pmc_hw *phw;
 285         uint32_t config;
 286         struct pmc *pm;
 287
 288         phw    = &arm64_pcpu[cpu]->pc_arm64pmcs[ri];
 289         pm     = phw->phw_pmc;
 290         config = pm->pm_md.pm_arm64.pm_arm64_evsel;
 291
 292         /*
 293          * Configure the event selection.
 294          */
 295         WRITE_SPECIALREG(pmselr_el0, ri);
 296         WRITE_SPECIALREG(pmxevtyper_el0, config);
 297
 298         isb();
 299
 300         /*
 301          * Enable the PMC.
 302          */
 303         arm64_interrupt_enable(ri);
 304         arm64_counter_enable(ri);
 305
 306         return 0;
 307 }
 308
 309 static int
 310 arm64_stop_pmc(int cpu, int ri)
 311 {
 312         struct pmc_hw *phw;
 313         struct pmc *pm;
 314
 315         phw    = &arm64_pcpu[cpu]->pc_arm64pmcs[ri];
 316         pm     = phw->phw_pmc;
 317
 318         /*
 319          * Disable the PMCs.
 320          */
 321         arm64_counter_disable(ri);
 322         arm64_interrupt_disable(ri);
 323
 324         return 0;
 325 }
 326
 327 static int
 328 arm64_release_pmc(int cpu, int ri, struct pmc *pmc)
 329 {
 330         struct pmc_hw *phw;
 331
 332         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 333             ("[arm64,%d] illegal CPU value %d", __LINE__, cpu));
 334         KASSERT(ri >= 0 && ri < arm64_npmcs,
 335             ("[arm64,%d] illegal row-index %d", __LINE__, ri));
 336
 337         phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri];
 338         KASSERT(phw->phw_pmc == NULL,
 339             ("[arm64,%d] PHW pmc %p non-NULL", __LINE__, phw->phw_pmc));
 340
 341         return 0;
 342 }
 343
 344 static int
 345 arm64_intr(struct trapframe *tf)
 346 {
 347         struct arm64_cpu *pc;
 348         int retval, ri;
 349         struct pmc *pm;
 350         int error;
 351         int reg, cpu;
 352
 353         cpu = curcpu;
 354         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 355             ("[arm64,%d] CPU %d out of range", __LINE__, cpu));
 356
 357         retval = 0;
 358         pc = arm64_pcpu[cpu];
 359
 360         for (ri = 0; ri < arm64_npmcs; ri++) {
 361                 pm = arm64_pcpu[cpu]->pc_arm64pmcs[ri].phw_pmc;
 362                 if (pm == NULL)
 363                         continue;
 364                 /* Check if counter is overflowed */
 365                 reg = (1 << ri);
 366                 if ((READ_SPECIALREG(pmovsclr_el0) & reg) == 0)
 367                         continue;
 368                 /* Clear Overflow Flag */
 369                 WRITE_SPECIALREG(pmovsclr_el0, reg);
 370
 371                 isb();
 372
 373                 retval = 1; /* Found an interrupting PMC. */
 374
 375                 if (!PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) {
 376                         pm->pm_pcpu_state[cpu].pps_overflowcnt += 1;
 377                         continue;
 378                 }
 379
 380                 if (pm->pm_state != PMC_STATE_RUNNING)
 381                         continue;
 382
 383                 error = pmc_process_interrupt(PMC_HR, pm, tf);
 384                 if (error)
 385                         arm64_stop_pmc(cpu, ri);
 386
 387                 /* Reload sampling count */
 388                 arm64_write_pmc(cpu, ri, pm->pm_sc.pm_reloadcount);
 389         }
 390
 391         return (retval);
 392 }
 393
 394 static int
 395 arm64_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
 396 {
 397         char arm64_name[PMC_NAME_MAX];
 398         struct pmc_hw *phw;
 399         int error;
 400
 401         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 402             ("[arm64,%d], illegal CPU %d", __LINE__, cpu));
 403         KASSERT(ri >= 0 && ri < arm64_npmcs,
 404             ("[arm64,%d] row-index %d out of range", __LINE__, ri));
 405
 406         phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri];
 407         snprintf(arm64_name, sizeof(arm64_name), "ARMV8-%d", ri);
 408         if ((error = copystr(arm64_name, pi->pm_name, PMC_NAME_MAX,
 409             NULL)) != 0)
 410                 return (error);
 411         pi->pm_class = PMC_CLASS_ARMV8;
 412         if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
 413                 pi->pm_enabled = TRUE;
 414                 *ppmc = phw->phw_pmc;
 415         } else {
 416                 pi->pm_enabled = FALSE;
 417                 *ppmc = NULL;
 418         }
 419
 420         return (0);
 421 }
 422
 423 static int
 424 arm64_get_config(int cpu, int ri, struct pmc **ppm)
 425 {
 426
 427         *ppm = arm64_pcpu[cpu]->pc_arm64pmcs[ri].phw_pmc;
 428
 429         return (0);
 430 }
 431
 432 /*
 433  * XXX don't know what we should do here.
 434  */
 435 static int
 436 arm64_switch_in(struct pmc_cpu *pc, struct pmc_process *pp)
 437 {
 438
 439         return (0);
 440 }
 441
 442 static int
 443 arm64_switch_out(struct pmc_cpu *pc, struct pmc_process *pp)
 444 {
 445
 446         return (0);
 447 }
 448
 449 static int
 450 arm64_pcpu_init(struct pmc_mdep *md, int cpu)
 451 {
 452         struct arm64_cpu *pac;
 453         struct pmc_hw  *phw;
 454         struct pmc_cpu *pc;
 455         uint64_t pmcr;
 456         int first_ri;
 457         int i;
 458
 459         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 460             ("[arm64,%d] wrong cpu number %d", __LINE__, cpu));
 461         PMCDBG1(MDP, INI, 1, "arm64-init cpu=%d", cpu);
 462
 463         arm64_pcpu[cpu] = pac = malloc(sizeof(struct arm64_cpu), M_PMC,
 464             M_WAITOK | M_ZERO);
 465
 466         pac->pc_arm64pmcs = malloc(sizeof(struct pmc_hw) * arm64_npmcs,
 467             M_PMC, M_WAITOK | M_ZERO);
 468         pc = pmc_pcpu[cpu];
 469         first_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_ARMV8].pcd_ri;
 470         KASSERT(pc != NULL, ("[arm64,%d] NULL per-cpu pointer", __LINE__));
 471
 472         for (i = 0, phw = pac->pc_arm64pmcs; i < arm64_npmcs; i++, phw++) {
 473                 phw->phw_state    = PMC_PHW_FLAG_IS_ENABLED |
 474                     PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(i);
 475                 phw->phw_pmc      = NULL;
 476                 pc->pc_hwpmcs[i + first_ri] = phw;
 477         }
 478
 479         /* Enable unit */
 480         pmcr = arm64_pmcr_read();
 481         pmcr |= PMCR_E;
 482         arm64_pmcr_write(pmcr);
 483
 484         return (0);
 485 }
 486
 487 static int
 488 arm64_pcpu_fini(struct pmc_mdep *md, int cpu)
 489 {
 490         uint32_t pmcr;
 491
 492         pmcr = arm64_pmcr_read();
 493         pmcr &= ~PMCR_E;
 494         arm64_pmcr_write(pmcr);
 495
 496         return (0);
 497 }
 498
 499 struct pmc_mdep *
 500 pmc_arm64_initialize()
 501 {
 502         struct pmc_mdep *pmc_mdep;
 503         struct pmc_classdep *pcd;
 504         int idcode, impcode;
 505         int reg;
 506
 507         reg = arm64_pmcr_read();
 508         arm64_npmcs = (reg & PMCR_N_MASK) >> PMCR_N_SHIFT;
 509         impcode = (reg & PMCR_IMP_MASK) >> PMCR_IMP_SHIFT;
 510         idcode = (reg & PMCR_IDCODE_MASK) >> PMCR_IDCODE_SHIFT;
 511
 512         PMCDBG1(MDP, INI, 1, "arm64-init npmcs=%d", arm64_npmcs);
 513
 514         /*
 515          * Allocate space for pointers to PMC HW descriptors and for
 516          * the MDEP structure used by MI code.
 517          */
 518         arm64_pcpu = malloc(sizeof(struct arm64_cpu *) * pmc_cpu_max(),
 519                 M_PMC, M_WAITOK | M_ZERO);
 520
 521         /* Just one class */
 522         pmc_mdep = pmc_mdep_alloc(1);
 523
 524         switch(impcode) {
 525         case PMCR_IMP_ARM:
 526                 switch (idcode) {
 527                 case PMCR_IDCODE_CORTEX_A76:
 528                 case PMCR_IDCODE_NEOVERSE_N1:
 529                         pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A76;
 530                         break;
 531                 case PMCR_IDCODE_CORTEX_A57:
 532                 case PMCR_IDCODE_CORTEX_A72:
 533                         pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A57;
 534                         break;
 535                 default:
 536                 case PMCR_IDCODE_CORTEX_A53:
 537                         pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A53;
 538                         break;
 539                 }
 540                 break;
 541         default:
 542                 pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A53;
 543                 break;
 544         }
 545
 546         pcd = &pmc_mdep->pmd_classdep[PMC_MDEP_CLASS_INDEX_ARMV8];
 547         pcd->pcd_caps  = ARMV8_PMC_CAPS;
 548         pcd->pcd_class = PMC_CLASS_ARMV8;
 549         pcd->pcd_num   = arm64_npmcs;
 550         pcd->pcd_ri    = pmc_mdep->pmd_npmc;
 551         pcd->pcd_width = 32;
 552
 553         pcd->pcd_allocate_pmc   = arm64_allocate_pmc;
 554         pcd->pcd_config_pmc     = arm64_config_pmc;
 555         pcd->pcd_pcpu_fini      = arm64_pcpu_fini;
 556         pcd->pcd_pcpu_init      = arm64_pcpu_init;
 557         pcd->pcd_describe       = arm64_describe;
 558         pcd->pcd_get_config     = arm64_get_config;
 559         pcd->pcd_read_pmc       = arm64_read_pmc;
 560         pcd->pcd_release_pmc    = arm64_release_pmc;
 561         pcd->pcd_start_pmc      = arm64_start_pmc;
 562         pcd->pcd_stop_pmc       = arm64_stop_pmc;
 563         pcd->pcd_write_pmc      = arm64_write_pmc;
 564
 565         pmc_mdep->pmd_intr       = arm64_intr;
 566         pmc_mdep->pmd_switch_in  = arm64_switch_in;
 567         pmc_mdep->pmd_switch_out = arm64_switch_out;
 568
 569         pmc_mdep->pmd_npmc   += arm64_npmcs;
 570
 571         return (pmc_mdep);
 572 }
 573
 574 void
 575 pmc_arm64_finalize(struct pmc_mdep *md)
 576 {
 577
 578 }