2 * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com>
5 * This software was developed by SRI International and the University of
6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
7 * ("CTSRD"), as part of the DARPA CRASH research programme.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/systm.h>
37 #include <sys/pmckern.h>
39 #include <machine/pmc_mdep.h>
40 #include <machine/cpu.h>
42 static int armv7_npmcs;
44 struct armv7_event_code_map {
49 #define PMC_EV_CPU_CYCLES 0xFF
52 * Per-processor information.
55 struct pmc_hw *pc_armv7pmcs;
58 static struct armv7_cpu **armv7_pcpu;
61 * Interrupt Enable Set Register
64 armv7_interrupt_enable(uint32_t pmc)
69 cp15_pminten_set(reg);
73 * Interrupt Clear Set Register
76 armv7_interrupt_disable(uint32_t pmc)
81 cp15_pminten_clr(reg);
85 * Counter Set Enable Register
88 armv7_counter_enable(unsigned int pmc)
93 cp15_pmcnten_set(reg);
97 * Counter Clear Enable Register
100 armv7_counter_disable(unsigned int pmc)
105 cp15_pmcnten_clr(reg);
109 * Performance Count Register N
112 armv7_pmcn_read(unsigned int pmc, uint32_t evsel)
115 if (evsel == PMC_EV_CPU_CYCLES) {
116 return ((uint32_t)cp15_pmccntr_get());
119 KASSERT(pmc < armv7_npmcs, ("%s: illegal PMC number %d", __func__, pmc));
121 cp15_pmselr_set(pmc);
122 return (cp15_pmxevcntr_get());
126 armv7_pmcn_write(unsigned int pmc, uint32_t reg)
129 KASSERT(pmc < armv7_npmcs, ("%s: illegal PMC number %d", __func__, pmc));
131 cp15_pmselr_set(pmc);
132 cp15_pmxevcntr_set(reg);
138 armv7_allocate_pmc(int cpu, int ri, struct pmc *pm,
139 const struct pmc_op_pmcallocate *a)
141 struct armv7_cpu *pac;
145 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
146 ("[armv7,%d] illegal CPU value %d", __LINE__, cpu));
147 KASSERT(ri >= 0 && ri < armv7_npmcs,
148 ("[armv7,%d] illegal row index %d", __LINE__, ri));
150 pac = armv7_pcpu[cpu];
152 if (a->pm_class != PMC_CLASS_ARMV7)
156 config = (pe & EVENT_ID_MASK);
157 pm->pm_md.pm_armv7.pm_armv7_evsel = config;
159 PMCDBG2(MDP, ALL, 2, "armv7-allocate ri=%d -> config=0x%x", ri, config);
166 armv7_read_pmc(int cpu, int ri, pmc_value_t *v)
173 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
174 ("[armv7,%d] illegal CPU value %d", __LINE__, cpu));
175 KASSERT(ri >= 0 && ri < armv7_npmcs,
176 ("[armv7,%d] illegal row index %d", __LINE__, ri));
178 pm = armv7_pcpu[cpu]->pc_armv7pmcs[ri].phw_pmc;
181 tmp = armv7_pmcn_read(ri, pm->pm_md.pm_armv7.pm_armv7_evsel);
183 /* Check if counter has overflowed */
184 if (pm->pm_md.pm_armv7.pm_armv7_evsel == PMC_EV_CPU_CYCLES)
189 if ((cp15_pmovsr_get() & reg) != 0) {
190 /* Clear Overflow Flag */
191 cp15_pmovsr_set(reg);
192 pm->pm_pcpu_state[cpu].pps_overflowcnt++;
194 /* Reread counter in case we raced. */
195 tmp = armv7_pmcn_read(ri, pm->pm_md.pm_armv7.pm_armv7_evsel);
197 tmp += 0x100000000llu * pm->pm_pcpu_state[cpu].pps_overflowcnt;
200 PMCDBG2(MDP, REA, 2, "armv7-read id=%d -> %jd", ri, tmp);
201 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) {
203 * Clamp value to 0 if the counter just overflowed,
204 * otherwise the returned reload count would wrap to a
207 if ((tmp & (1ull << 63)) == 0)
210 tmp = ARMV7_PERFCTR_VALUE_TO_RELOAD_COUNT(tmp);
218 armv7_write_pmc(int cpu, int ri, pmc_value_t v)
222 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
223 ("[armv7,%d] illegal CPU value %d", __LINE__, cpu));
224 KASSERT(ri >= 0 && ri < armv7_npmcs,
225 ("[armv7,%d] illegal row-index %d", __LINE__, ri));
227 pm = armv7_pcpu[cpu]->pc_armv7pmcs[ri].phw_pmc;
229 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
230 v = ARMV7_RELOAD_COUNT_TO_PERFCTR_VALUE(v);
232 PMCDBG3(MDP, WRI, 1, "armv7-write cpu=%d ri=%d v=%jx", cpu, ri, v);
234 pm->pm_pcpu_state[cpu].pps_overflowcnt = v >> 32;
235 if (pm->pm_md.pm_armv7.pm_armv7_evsel == PMC_EV_CPU_CYCLES)
238 armv7_pmcn_write(ri, v);
244 armv7_config_pmc(int cpu, int ri, struct pmc *pm)
248 PMCDBG3(MDP, CFG, 1, "cpu=%d ri=%d pm=%p", cpu, ri, pm);
250 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
251 ("[armv7,%d] illegal CPU value %d", __LINE__, cpu));
252 KASSERT(ri >= 0 && ri < armv7_npmcs,
253 ("[armv7,%d] illegal row-index %d", __LINE__, ri));
255 phw = &armv7_pcpu[cpu]->pc_armv7pmcs[ri];
257 KASSERT(pm == NULL || phw->phw_pmc == NULL,
258 ("[armv7,%d] pm=%p phw->pm=%p hwpmc not unconfigured",
259 __LINE__, pm, phw->phw_pmc));
267 armv7_start_pmc(int cpu, int ri)
273 phw = &armv7_pcpu[cpu]->pc_armv7pmcs[ri];
275 config = pm->pm_md.pm_armv7.pm_armv7_evsel;
278 * Configure the event selection.
280 if (config != PMC_EV_CPU_CYCLES) {
282 cp15_pmxevtyper_set(config);
289 armv7_interrupt_enable(ri);
290 armv7_counter_enable(ri);
296 armv7_stop_pmc(int cpu, int ri)
302 phw = &armv7_pcpu[cpu]->pc_armv7pmcs[ri];
304 config = pm->pm_md.pm_armv7.pm_armv7_evsel;
305 if (config == PMC_EV_CPU_CYCLES)
311 armv7_counter_disable(ri);
312 armv7_interrupt_disable(ri);
318 armv7_release_pmc(int cpu, int ri, struct pmc *pmc)
322 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
323 ("[armv7,%d] illegal CPU value %d", __LINE__, cpu));
324 KASSERT(ri >= 0 && ri < armv7_npmcs,
325 ("[armv7,%d] illegal row-index %d", __LINE__, ri));
327 phw = &armv7_pcpu[cpu]->pc_armv7pmcs[ri];
328 KASSERT(phw->phw_pmc == NULL,
329 ("[armv7,%d] PHW pmc %p non-NULL", __LINE__, phw->phw_pmc));
335 armv7_intr(struct trapframe *tf)
337 struct armv7_cpu *pc;
344 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
345 ("[armv7,%d] CPU %d out of range", __LINE__, cpu));
348 pc = armv7_pcpu[cpu];
350 for (ri = 0; ri < armv7_npmcs; ri++) {
351 pm = armv7_pcpu[cpu]->pc_armv7pmcs[ri].phw_pmc;
355 /* Check if counter has overflowed */
356 if (pm->pm_md.pm_armv7.pm_armv7_evsel == PMC_EV_CPU_CYCLES)
361 if ((cp15_pmovsr_get() & reg) == 0) {
365 /* Clear Overflow Flag */
366 cp15_pmovsr_set(reg);
368 retval = 1; /* Found an interrupting PMC. */
370 pm->pm_pcpu_state[cpu].pps_overflowcnt += 1;
372 if (!PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
375 if (pm->pm_state != PMC_STATE_RUNNING)
378 error = pmc_process_interrupt(PMC_HR, pm, tf);
380 armv7_stop_pmc(cpu, ri);
382 /* Reload sampling count */
383 armv7_write_pmc(cpu, ri, pm->pm_sc.pm_reloadcount);
390 armv7_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
392 char armv7_name[PMC_NAME_MAX];
396 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
397 ("[armv7,%d], illegal CPU %d", __LINE__, cpu));
398 KASSERT(ri >= 0 && ri < armv7_npmcs,
399 ("[armv7,%d] row-index %d out of range", __LINE__, ri));
401 phw = &armv7_pcpu[cpu]->pc_armv7pmcs[ri];
402 snprintf(armv7_name, sizeof(armv7_name), "ARMV7-%d", ri);
403 if ((error = copystr(armv7_name, pi->pm_name, PMC_NAME_MAX,
406 pi->pm_class = PMC_CLASS_ARMV7;
407 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
408 pi->pm_enabled = TRUE;
409 *ppmc = phw->phw_pmc;
411 pi->pm_enabled = FALSE;
419 armv7_get_config(int cpu, int ri, struct pmc **ppm)
422 *ppm = armv7_pcpu[cpu]->pc_armv7pmcs[ri].phw_pmc;
428 * XXX don't know what we should do here.
431 armv7_switch_in(struct pmc_cpu *pc, struct pmc_process *pp)
438 armv7_switch_out(struct pmc_cpu *pc, struct pmc_process *pp)
445 armv7_pcpu_init(struct pmc_mdep *md, int cpu)
447 struct armv7_cpu *pac;
454 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
455 ("[armv7,%d] wrong cpu number %d", __LINE__, cpu));
456 PMCDBG1(MDP, INI, 1, "armv7-init cpu=%d", cpu);
458 armv7_pcpu[cpu] = pac = malloc(sizeof(struct armv7_cpu), M_PMC,
461 pac->pc_armv7pmcs = malloc(sizeof(struct pmc_hw) * armv7_npmcs,
462 M_PMC, M_WAITOK|M_ZERO);
464 first_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_ARMV7].pcd_ri;
465 KASSERT(pc != NULL, ("[armv7,%d] NULL per-cpu pointer", __LINE__));
467 for (i = 0, phw = pac->pc_armv7pmcs; i < armv7_npmcs; i++, phw++) {
468 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED |
469 PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(i);
471 pc->pc_hwpmcs[i + first_ri] = phw;
475 cp15_pmcnten_clr(pmnc);
476 cp15_pminten_clr(pmnc);
477 cp15_pmovsr_set(pmnc);
480 pmnc = cp15_pmcr_get();
481 pmnc |= ARMV7_PMNC_ENABLE;
488 armv7_pcpu_fini(struct pmc_mdep *md, int cpu)
492 pmnc = cp15_pmcr_get();
493 pmnc &= ~ARMV7_PMNC_ENABLE;
497 cp15_pmcnten_clr(pmnc);
498 cp15_pminten_clr(pmnc);
499 cp15_pmovsr_set(pmnc);
505 pmc_armv7_initialize()
507 struct pmc_mdep *pmc_mdep;
508 struct pmc_classdep *pcd;
512 reg = cp15_pmcr_get();
513 armv7_npmcs = (reg >> ARMV7_PMNC_N_SHIFT) & \
515 idcode = (reg & ARMV7_IDCODE_MASK) >> ARMV7_IDCODE_SHIFT;
517 PMCDBG1(MDP, INI, 1, "armv7-init npmcs=%d", armv7_npmcs);
520 * Allocate space for pointers to PMC HW descriptors and for
521 * the MDEP structure used by MI code.
523 armv7_pcpu = malloc(sizeof(struct armv7_cpu *) * pmc_cpu_max(),
524 M_PMC, M_WAITOK | M_ZERO);
527 pmc_mdep = pmc_mdep_alloc(1);
530 case ARMV7_IDCODE_CORTEX_A9:
531 pmc_mdep->pmd_cputype = PMC_CPU_ARMV7_CORTEX_A9;
534 case ARMV7_IDCODE_CORTEX_A8:
536 * On A8 we implemented common events only,
537 * so use it for the rest of machines.
539 pmc_mdep->pmd_cputype = PMC_CPU_ARMV7_CORTEX_A8;
543 pcd = &pmc_mdep->pmd_classdep[PMC_MDEP_CLASS_INDEX_ARMV7];
544 pcd->pcd_caps = ARMV7_PMC_CAPS;
545 pcd->pcd_class = PMC_CLASS_ARMV7;
546 pcd->pcd_num = armv7_npmcs;
547 pcd->pcd_ri = pmc_mdep->pmd_npmc;
550 pcd->pcd_allocate_pmc = armv7_allocate_pmc;
551 pcd->pcd_config_pmc = armv7_config_pmc;
552 pcd->pcd_pcpu_fini = armv7_pcpu_fini;
553 pcd->pcd_pcpu_init = armv7_pcpu_init;
554 pcd->pcd_describe = armv7_describe;
555 pcd->pcd_get_config = armv7_get_config;
556 pcd->pcd_read_pmc = armv7_read_pmc;
557 pcd->pcd_release_pmc = armv7_release_pmc;
558 pcd->pcd_start_pmc = armv7_start_pmc;
559 pcd->pcd_stop_pmc = armv7_stop_pmc;
560 pcd->pcd_write_pmc = armv7_write_pmc;
562 pmc_mdep->pmd_intr = armv7_intr;
563 pmc_mdep->pmd_switch_in = armv7_switch_in;
564 pmc_mdep->pmd_switch_out = armv7_switch_out;
566 pmc_mdep->pmd_npmc += armv7_npmcs;
572 pmc_armv7_finalize(struct pmc_mdep *md)