2 * Copyright (c) 2008 Joseph Koshy
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * Intel Core, Core 2 and Atom PMCs.
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
37 #include <sys/pmckern.h>
38 #include <sys/systm.h>
40 #include <machine/intr_machdep.h>
41 #include <machine/apicvar.h>
42 #include <machine/cpu.h>
43 #include <machine/cpufunc.h>
44 #include <machine/specialreg.h>
46 #define CORE_CPUID_REQUEST 0xA
47 #define CORE_CPUID_REQUEST_SIZE 0x4
48 #define CORE_CPUID_EAX 0x0
49 #define CORE_CPUID_EBX 0x1
50 #define CORE_CPUID_ECX 0x2
51 #define CORE_CPUID_EDX 0x3
53 #define IAF_PMC_CAPS \
54 (PMC_CAP_READ | PMC_CAP_WRITE | PMC_CAP_INTERRUPT)
55 #define IAF_RI_TO_MSR(RI) ((RI) + (1 << 30))
57 #define IAP_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | PMC_CAP_SYSTEM | \
58 PMC_CAP_EDGE | PMC_CAP_THRESHOLD | PMC_CAP_READ | PMC_CAP_WRITE | \
59 PMC_CAP_INVERT | PMC_CAP_QUALIFIER | PMC_CAP_PRECISE)
62 * "Architectural" events defined by Intel. The values of these
63 * symbols correspond to positions in the bitmask returned by
64 * the CPUID.0AH instruction.
66 enum core_arch_events {
67 CORE_AE_BRANCH_INSTRUCTION_RETIRED = 5,
68 CORE_AE_BRANCH_MISSES_RETIRED = 6,
69 CORE_AE_INSTRUCTION_RETIRED = 1,
70 CORE_AE_LLC_MISSES = 4,
71 CORE_AE_LLC_REFERENCE = 3,
72 CORE_AE_UNHALTED_REFERENCE_CYCLES = 2,
73 CORE_AE_UNHALTED_CORE_CYCLES = 0
76 static enum pmc_cputype core_cputype;
79 volatile uint32_t pc_resync;
80 volatile uint32_t pc_iafctrl; /* Fixed function control. */
81 volatile uint64_t pc_globalctrl; /* Global control register. */
82 struct pmc_hw pc_corepmcs[];
85 static struct core_cpu **core_pcpu;
87 static uint32_t core_architectural_events;
88 static uint64_t core_pmcmask;
90 static int core_iaf_ri; /* relative index of fixed counters */
91 static int core_iaf_width;
92 static int core_iaf_npmc;
94 static int core_iap_width;
95 static int core_iap_npmc;
98 core_pcpu_noop(struct pmc_mdep *md, int cpu)
106 core_pcpu_init(struct pmc_mdep *md, int cpu)
111 int core_ri, n, npmc;
113 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
114 ("[iaf,%d] insane cpu number %d", __LINE__, cpu));
116 PMCDBG(MDP,INI,1,"core-init cpu=%d", cpu);
118 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri;
119 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num;
121 if (core_cputype != PMC_CPU_INTEL_CORE)
122 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num;
124 cc = malloc(sizeof(struct core_cpu) + npmc * sizeof(struct pmc_hw),
125 M_PMC, M_WAITOK | M_ZERO);
130 KASSERT(pc != NULL && cc != NULL,
131 ("[core,%d] NULL per-cpu structures cpu=%d", __LINE__, cpu));
133 for (n = 0, phw = cc->pc_corepmcs; n < npmc; n++, phw++) {
134 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED |
135 PMC_PHW_CPU_TO_STATE(cpu) |
136 PMC_PHW_INDEX_TO_STATE(n + core_ri);
138 pc->pc_hwpmcs[n + core_ri] = phw;
145 core_pcpu_fini(struct pmc_mdep *md, int cpu)
147 int core_ri, n, npmc;
152 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
153 ("[core,%d] insane cpu number (%d)", __LINE__, cpu));
155 PMCDBG(MDP,INI,1,"core-pcpu-fini cpu=%d", cpu);
157 if ((cc = core_pcpu[cpu]) == NULL)
160 core_pcpu[cpu] = NULL;
164 KASSERT(pc != NULL, ("[core,%d] NULL per-cpu %d state", __LINE__,
167 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num;
168 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri;
170 for (n = 0; n < npmc; n++) {
171 msr = rdmsr(IAP_EVSEL0 + n) & ~IAP_EVSEL_MASK;
172 wrmsr(IAP_EVSEL0 + n, msr);
175 if (core_cputype != PMC_CPU_INTEL_CORE) {
176 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK;
177 wrmsr(IAF_CTRL, msr);
178 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num;
181 for (n = 0; n < npmc; n++)
182 pc->pc_hwpmcs[n + core_ri] = NULL;
190 * Fixed function counters.
194 iaf_perfctr_value_to_reload_count(pmc_value_t v)
196 v &= (1ULL << core_iaf_width) - 1;
197 return (1ULL << core_iaf_width) - v;
201 iaf_reload_count_to_perfctr_value(pmc_value_t rlc)
203 return (1ULL << core_iaf_width) - rlc;
207 iaf_allocate_pmc(int cpu, int ri, struct pmc *pm,
208 const struct pmc_op_pmcallocate *a)
211 uint32_t caps, flags, validflags;
213 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
214 ("[core,%d] illegal CPU %d", __LINE__, cpu));
216 PMCDBG(MDP,ALL,1, "iaf-allocate ri=%d reqcaps=0x%x", ri, pm->pm_caps);
218 if (ri < 0 || ri > core_iaf_npmc)
223 if (a->pm_class != PMC_CLASS_IAF ||
224 (caps & IAF_PMC_CAPS) != caps)
228 if (ev < PMC_EV_IAF_FIRST || ev > PMC_EV_IAF_LAST)
231 if (ev == PMC_EV_IAF_INSTR_RETIRED_ANY && ri != 0)
233 if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_CORE && ri != 1)
235 if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_REF && ri != 2)
238 flags = a->pm_md.pm_iaf.pm_iaf_flags;
240 validflags = IAF_MASK;
242 if (core_cputype != PMC_CPU_INTEL_ATOM)
243 validflags &= ~IAF_ANY;
245 if ((flags & ~validflags) != 0)
248 if (caps & PMC_CAP_INTERRUPT)
250 if (caps & PMC_CAP_SYSTEM)
252 if (caps & PMC_CAP_USER)
254 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0)
255 flags |= (IAF_OS | IAF_USR);
257 pm->pm_md.pm_iaf.pm_iaf_ctrl = (flags << (ri * 4));
259 PMCDBG(MDP,ALL,2, "iaf-allocate config=0x%jx",
260 (uintmax_t) pm->pm_md.pm_iaf.pm_iaf_ctrl);
266 iaf_config_pmc(int cpu, int ri, struct pmc *pm)
268 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
269 ("[core,%d] illegal CPU %d", __LINE__, cpu));
271 KASSERT(ri >= 0 && ri < core_iaf_npmc,
272 ("[core,%d] illegal row-index %d", __LINE__, ri));
274 PMCDBG(MDP,CFG,1, "iaf-config cpu=%d ri=%d pm=%p", cpu, ri, pm);
276 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__,
279 core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc = pm;
285 iaf_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
289 char iaf_name[PMC_NAME_MAX];
291 phw = &core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri];
293 (void) snprintf(iaf_name, sizeof(iaf_name), "IAF-%d", ri);
294 if ((error = copystr(iaf_name, pi->pm_name, PMC_NAME_MAX,
298 pi->pm_class = PMC_CLASS_IAF;
300 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
301 pi->pm_enabled = TRUE;
302 *ppmc = phw->phw_pmc;
304 pi->pm_enabled = FALSE;
312 iaf_get_config(int cpu, int ri, struct pmc **ppm)
314 *ppm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc;
320 iaf_get_msr(int ri, uint32_t *msr)
322 KASSERT(ri >= 0 && ri < core_iaf_npmc,
323 ("[iaf,%d] ri %d out of range", __LINE__, ri));
325 *msr = IAF_RI_TO_MSR(ri);
331 iaf_read_pmc(int cpu, int ri, pmc_value_t *v)
336 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
337 ("[core,%d] illegal cpu value %d", __LINE__, cpu));
338 KASSERT(ri >= 0 && ri < core_iaf_npmc,
339 ("[core,%d] illegal row-index %d", __LINE__, ri));
341 pm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc;
344 ("[core,%d] cpu %d ri %d(%d) pmc not configured", __LINE__, cpu,
345 ri, ri + core_iaf_ri));
347 tmp = rdpmc(IAF_RI_TO_MSR(ri));
349 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
350 *v = iaf_perfctr_value_to_reload_count(tmp);
354 PMCDBG(MDP,REA,1, "iaf-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri,
355 IAF_RI_TO_MSR(ri), *v);
361 iaf_release_pmc(int cpu, int ri, struct pmc *pmc)
363 PMCDBG(MDP,REL,1, "iaf-release cpu=%d ri=%d pm=%p", cpu, ri, pmc);
365 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
366 ("[core,%d] illegal CPU value %d", __LINE__, cpu));
367 KASSERT(ri >= 0 && ri < core_iaf_npmc,
368 ("[core,%d] illegal row-index %d", __LINE__, ri));
370 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc == NULL,
371 ("[core,%d] PHW pmc non-NULL", __LINE__));
377 iaf_start_pmc(int cpu, int ri)
380 struct core_cpu *iafc;
383 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
384 ("[core,%d] illegal CPU value %d", __LINE__, cpu));
385 KASSERT(ri >= 0 && ri < core_iaf_npmc,
386 ("[core,%d] illegal row-index %d", __LINE__, ri));
388 PMCDBG(MDP,STA,1,"iaf-start cpu=%d ri=%d", cpu, ri);
390 iafc = core_pcpu[cpu];
391 pm = iafc->pc_corepmcs[ri + core_iaf_ri].phw_pmc;
393 iafc->pc_iafctrl |= pm->pm_md.pm_iaf.pm_iaf_ctrl;
395 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK;
396 wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK));
400 iafc->pc_globalctrl |= (1ULL << (ri + IAF_OFFSET));
401 msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK;
402 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl &
403 IAF_GLOBAL_CTRL_MASK));
404 } while (iafc->pc_resync != 0);
406 PMCDBG(MDP,STA,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)",
407 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL),
408 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL));
414 iaf_stop_pmc(int cpu, int ri)
417 struct core_cpu *iafc;
420 PMCDBG(MDP,STO,1,"iaf-stop cpu=%d ri=%d", cpu, ri);
422 iafc = core_pcpu[cpu];
424 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
425 ("[core,%d] illegal CPU value %d", __LINE__, cpu));
426 KASSERT(ri >= 0 && ri < core_iaf_npmc,
427 ("[core,%d] illegal row-index %d", __LINE__, ri));
429 fc = (IAF_MASK << (ri * 4));
431 if (core_cputype != PMC_CPU_INTEL_ATOM)
434 iafc->pc_iafctrl &= ~fc;
436 PMCDBG(MDP,STO,1,"iaf-stop iafctrl=%x", iafc->pc_iafctrl);
437 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK;
438 wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK));
442 iafc->pc_globalctrl &= ~(1ULL << (ri + IAF_OFFSET));
443 msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK;
444 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl &
445 IAF_GLOBAL_CTRL_MASK));
446 } while (iafc->pc_resync != 0);
448 PMCDBG(MDP,STO,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)",
449 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL),
450 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL));
456 iaf_write_pmc(int cpu, int ri, pmc_value_t v)
462 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
463 ("[core,%d] illegal cpu value %d", __LINE__, cpu));
464 KASSERT(ri >= 0 && ri < core_iaf_npmc,
465 ("[core,%d] illegal row-index %d", __LINE__, ri));
468 pm = cc->pc_corepmcs[ri + core_iaf_ri].phw_pmc;
471 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, ri));
473 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
474 v = iaf_reload_count_to_perfctr_value(v);
476 /* Turn off fixed counters */
477 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK;
478 wrmsr(IAF_CTRL, msr);
480 wrmsr(IAF_CTR0 + ri, v & ((1ULL << core_iaf_width) - 1));
482 /* Turn on fixed counters */
483 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK;
484 wrmsr(IAF_CTRL, msr | (cc->pc_iafctrl & IAF_CTRL_MASK));
486 PMCDBG(MDP,WRI,1, "iaf-write cpu=%d ri=%d msr=0x%x v=%jx iafctrl=%jx "
487 "pmc=%jx", cpu, ri, IAF_RI_TO_MSR(ri), v,
488 (uintmax_t) rdmsr(IAF_CTRL),
489 (uintmax_t) rdpmc(IAF_RI_TO_MSR(ri)));
496 iaf_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth)
498 struct pmc_classdep *pcd;
500 KASSERT(md != NULL, ("[iaf,%d] md is NULL", __LINE__));
502 PMCDBG(MDP,INI,1, "%s", "iaf-initialize");
504 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF];
506 pcd->pcd_caps = IAF_PMC_CAPS;
507 pcd->pcd_class = PMC_CLASS_IAF;
509 pcd->pcd_ri = md->pmd_npmc;
510 pcd->pcd_width = pmcwidth;
512 pcd->pcd_allocate_pmc = iaf_allocate_pmc;
513 pcd->pcd_config_pmc = iaf_config_pmc;
514 pcd->pcd_describe = iaf_describe;
515 pcd->pcd_get_config = iaf_get_config;
516 pcd->pcd_get_msr = iaf_get_msr;
517 pcd->pcd_pcpu_fini = core_pcpu_noop;
518 pcd->pcd_pcpu_init = core_pcpu_noop;
519 pcd->pcd_read_pmc = iaf_read_pmc;
520 pcd->pcd_release_pmc = iaf_release_pmc;
521 pcd->pcd_start_pmc = iaf_start_pmc;
522 pcd->pcd_stop_pmc = iaf_stop_pmc;
523 pcd->pcd_write_pmc = iaf_write_pmc;
525 md->pmd_npmc += npmc;
529 * Intel programmable PMCs.
533 * Event descriptor tables.
535 * For each event id, we track:
537 * 1. The CPUs that the event is valid for.
539 * 2. If the event uses a fixed UMASK, the value of the umask field.
540 * If the event doesn't use a fixed UMASK, a mask of legal bits
544 struct iap_event_descr {
545 enum pmc_event iap_ev;
546 unsigned char iap_evcode;
547 unsigned char iap_umask;
548 unsigned char iap_flags;
551 #define IAP_F_CC (1 << 0) /* CPU: Core */
552 #define IAP_F_CC2 (1 << 1) /* CPU: Core2 family */
553 #define IAP_F_CC2E (1 << 2) /* CPU: Core2 Extreme only */
554 #define IAP_F_CA (1 << 3) /* CPU: Atom */
555 #define IAP_F_I7 (1 << 4) /* CPU: Core i7 */
556 #define IAP_F_I7O (1 << 4) /* CPU: Core i7 (old) */
557 #define IAP_F_WM (1 << 5) /* CPU: Westmere */
558 #define IAP_F_FM (1 << 6) /* Fixed mask */
560 #define IAP_F_ALLCPUSCORE2 \
561 (IAP_F_CC | IAP_F_CC2 | IAP_F_CC2E | IAP_F_CA)
563 /* Sub fields of UMASK that this event supports. */
564 #define IAP_M_CORE (1 << 0) /* Core specificity */
565 #define IAP_M_AGENT (1 << 1) /* Agent specificity */
566 #define IAP_M_PREFETCH (1 << 2) /* Prefetch */
567 #define IAP_M_MESI (1 << 3) /* MESI */
568 #define IAP_M_SNOOPRESPONSE (1 << 4) /* Snoop response */
569 #define IAP_M_SNOOPTYPE (1 << 5) /* Snoop type */
570 #define IAP_M_TRANSITION (1 << 6) /* Transition */
572 #define IAP_F_CORE (0x3 << 14) /* Core specificity */
573 #define IAP_F_AGENT (0x1 << 13) /* Agent specificity */
574 #define IAP_F_PREFETCH (0x3 << 12) /* Prefetch */
575 #define IAP_F_MESI (0xF << 8) /* MESI */
576 #define IAP_F_SNOOPRESPONSE (0xB << 8) /* Snoop response */
577 #define IAP_F_SNOOPTYPE (0x3 << 8) /* Snoop type */
578 #define IAP_F_TRANSITION (0x1 << 12) /* Transition */
580 #define IAP_PREFETCH_RESERVED (0x2 << 12)
581 #define IAP_CORE_THIS (0x1 << 14)
582 #define IAP_CORE_ALL (0x3 << 14)
583 #define IAP_F_CMASK 0xFF000000
585 static struct iap_event_descr iap_events[] = {
587 #define IAPDESCR(N,EV,UM,FLAGS) { \
588 .iap_ev = PMC_EV_IAP_EVENT_##N, \
589 .iap_evcode = (EV), \
591 .iap_flags = (FLAGS) \
594 IAPDESCR(02H_01H, 0x02, 0x01, IAP_F_FM | IAP_F_I7O),
595 IAPDESCR(02H_81H, 0x02, 0x81, IAP_F_FM | IAP_F_CA),
597 IAPDESCR(03H_00H, 0x03, 0x00, IAP_F_FM | IAP_F_CC),
598 IAPDESCR(03H_01H, 0x03, 0x01, IAP_F_FM | IAP_F_I7O),
599 IAPDESCR(03H_02H, 0x03, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_WM),
600 IAPDESCR(03H_04H, 0x03, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O),
601 IAPDESCR(03H_08H, 0x03, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
602 IAPDESCR(03H_10H, 0x03, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
603 IAPDESCR(03H_20H, 0x03, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
605 IAPDESCR(04H_00H, 0x04, 0x00, IAP_F_FM | IAP_F_CC),
606 IAPDESCR(04H_01H, 0x04, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O),
607 IAPDESCR(04H_02H, 0x04, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
608 IAPDESCR(04H_07H, 0x04, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
609 IAPDESCR(04H_08H, 0x04, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
611 IAPDESCR(05H_00H, 0x05, 0x00, IAP_F_FM | IAP_F_CC),
612 IAPDESCR(05H_01H, 0x05, 0x01, IAP_F_FM | IAP_F_I7O),
613 IAPDESCR(05H_02H, 0x05, 0x02, IAP_F_FM | IAP_F_I7O | IAP_F_WM),
614 IAPDESCR(05H_03H, 0x05, 0x03, IAP_F_FM | IAP_F_I7O),
616 IAPDESCR(06H_00H, 0x06, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2 |
617 IAP_F_CC2E | IAP_F_CA),
618 IAPDESCR(06H_01H, 0x06, 0x01, IAP_F_FM | IAP_F_I7O),
619 IAPDESCR(06H_02H, 0x06, 0x02, IAP_F_FM | IAP_F_I7O),
620 IAPDESCR(06H_04H, 0x06, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
621 IAPDESCR(06H_08H, 0x06, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
622 IAPDESCR(06H_0FH, 0x06, 0x0F, IAP_F_FM | IAP_F_I7O),
624 IAPDESCR(07H_00H, 0x07, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2),
625 IAPDESCR(07H_01H, 0x07, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 | IAP_F_WM),
626 IAPDESCR(07H_02H, 0x07, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2),
627 IAPDESCR(07H_03H, 0x07, 0x03, IAP_F_FM | IAP_F_ALLCPUSCORE2),
628 IAPDESCR(07H_06H, 0x07, 0x06, IAP_F_FM | IAP_F_CA),
629 IAPDESCR(07H_08H, 0x07, 0x08, IAP_F_FM | IAP_F_CA),
631 IAPDESCR(08H_01H, 0x08, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
632 IAP_F_I7 | IAP_F_WM),
633 IAPDESCR(08H_02H, 0x08, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
634 IAP_F_I7 | IAP_F_WM),
635 IAPDESCR(08H_04H, 0x08, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
637 IAPDESCR(08H_05H, 0x08, 0x05, IAP_F_FM | IAP_F_CA),
638 IAPDESCR(08H_06H, 0x08, 0x06, IAP_F_FM | IAP_F_CA),
639 IAPDESCR(08H_07H, 0x08, 0x07, IAP_F_FM | IAP_F_CA),
640 IAPDESCR(08H_08H, 0x08, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
641 IAPDESCR(08H_09H, 0x08, 0x09, IAP_F_FM | IAP_F_CA),
642 IAPDESCR(08H_10H, 0x08, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
643 IAPDESCR(08H_20H, 0x08, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
644 IAPDESCR(08H_40H, 0x08, 0x40, IAP_F_FM | IAP_F_I7),
645 IAPDESCR(08H_80H, 0x08, 0x80, IAP_F_FM | IAP_F_I7),
647 IAPDESCR(09H_01H, 0x09, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O),
648 IAPDESCR(09H_02H, 0x09, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O),
649 IAPDESCR(09H_04H, 0x09, 0x04, IAP_F_FM | IAP_F_I7O),
650 IAPDESCR(09H_08H, 0x09, 0x08, IAP_F_FM | IAP_F_I7O),
652 IAPDESCR(0BH_01H, 0x0B, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
653 IAPDESCR(0BH_02H, 0x0B, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
654 IAPDESCR(0BH_10H, 0x0B, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
656 IAPDESCR(0CH_01H, 0x0C, 0x01, IAP_F_FM | IAP_F_CC2 | IAP_F_I7 |
658 IAPDESCR(0CH_02H, 0x0C, 0x02, IAP_F_FM | IAP_F_CC2),
659 IAPDESCR(0CH_03H, 0x0C, 0x03, IAP_F_FM | IAP_F_CA),
661 IAPDESCR(0EH_01H, 0x0E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
662 IAPDESCR(0EH_02H, 0x0E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
664 IAPDESCR(0FH_01H, 0x0F, 0x01, IAP_F_FM | IAP_F_I7),
665 IAPDESCR(0FH_02H, 0x0F, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
666 IAPDESCR(0FH_08H, 0x0F, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
667 IAPDESCR(0FH_10H, 0x0F, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
668 IAPDESCR(0FH_20H, 0x0F, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
669 IAPDESCR(0FH_80H, 0x0F, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
671 IAPDESCR(10H_00H, 0x10, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
672 IAPDESCR(10H_01H, 0x10, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM),
673 IAPDESCR(10H_02H, 0x10, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
674 IAPDESCR(10H_04H, 0x10, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
675 IAPDESCR(10H_08H, 0x10, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
676 IAPDESCR(10H_10H, 0x10, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
677 IAPDESCR(10H_20H, 0x10, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
678 IAPDESCR(10H_40H, 0x10, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
679 IAPDESCR(10H_80H, 0x10, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
680 IAPDESCR(10H_81H, 0x10, 0x81, IAP_F_FM | IAP_F_CA),
682 IAPDESCR(11H_00H, 0x11, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2),
683 IAPDESCR(11H_01H, 0x11, 0x01, IAP_F_FM | IAP_F_CA),
684 IAPDESCR(11H_81H, 0x11, 0x81, IAP_F_FM | IAP_F_CA),
686 IAPDESCR(12H_00H, 0x12, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
687 IAPDESCR(12H_01H, 0x12, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM),
688 IAPDESCR(12H_02H, 0x12, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
689 IAPDESCR(12H_04H, 0x12, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
690 IAPDESCR(12H_08H, 0x12, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
691 IAPDESCR(12H_10H, 0x12, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
692 IAPDESCR(12H_20H, 0x12, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
693 IAPDESCR(12H_40H, 0x12, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
694 IAPDESCR(12H_81H, 0x12, 0x81, IAP_F_FM | IAP_F_CA),
696 IAPDESCR(13H_00H, 0x13, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
697 IAPDESCR(13H_01H, 0x13, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM),
698 IAPDESCR(13H_02H, 0x13, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
699 IAPDESCR(13H_04H, 0x13, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
700 IAPDESCR(13H_07H, 0x13, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
701 IAPDESCR(13H_81H, 0x13, 0x81, IAP_F_FM | IAP_F_CA),
703 IAPDESCR(14H_00H, 0x14, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2),
704 IAPDESCR(14H_01H, 0x14, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM),
705 IAPDESCR(14H_02H, 0x14, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
707 IAPDESCR(17H_01H, 0x17, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
709 IAPDESCR(18H_00H, 0x18, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
710 IAPDESCR(18H_01H, 0x18, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
712 IAPDESCR(19H_00H, 0x19, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
713 IAPDESCR(19H_01H, 0x19, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
714 IAP_F_I7 | IAP_F_WM),
715 IAPDESCR(19H_02H, 0x19, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
717 IAPDESCR(1DH_01H, 0x1D, 0x01, IAP_F_FM | IAP_F_I7O),
718 IAPDESCR(1DH_02H, 0x1D, 0x02, IAP_F_FM | IAP_F_I7O),
719 IAPDESCR(1DH_04H, 0x1D, 0x04, IAP_F_FM | IAP_F_I7O),
721 IAPDESCR(1EH_01H, 0x1E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
723 IAPDESCR(20H_01H, 0x20, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
724 IAPDESCR(21H, 0x21, IAP_M_CORE, IAP_F_ALLCPUSCORE2),
725 IAPDESCR(22H, 0x22, IAP_M_CORE, IAP_F_CC2),
726 IAPDESCR(23H, 0x23, IAP_M_CORE, IAP_F_ALLCPUSCORE2),
728 IAPDESCR(24H, 0x24, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2),
729 IAPDESCR(24H_01H, 0x24, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
730 IAPDESCR(24H_02H, 0x24, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
731 IAPDESCR(24H_03H, 0x24, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
732 IAPDESCR(24H_04H, 0x24, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
733 IAPDESCR(24H_08H, 0x24, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
734 IAPDESCR(24H_0CH, 0x24, 0x0C, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
735 IAPDESCR(24H_10H, 0x24, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
736 IAPDESCR(24H_20H, 0x24, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
737 IAPDESCR(24H_30H, 0x24, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
738 IAPDESCR(24H_40H, 0x24, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
739 IAPDESCR(24H_80H, 0x24, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
740 IAPDESCR(24H_C0H, 0x24, 0xC0, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
741 IAPDESCR(24H_AAH, 0x24, 0xAA, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
742 IAPDESCR(24H_FFH, 0x24, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
744 IAPDESCR(25H, 0x25, IAP_M_CORE, IAP_F_ALLCPUSCORE2),
746 IAPDESCR(26H, 0x26, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2),
747 IAPDESCR(26H_01H, 0x26, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
748 IAPDESCR(26H_02H, 0x26, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
749 IAPDESCR(26H_04H, 0x26, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
750 IAPDESCR(26H_08H, 0x26, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
751 IAPDESCR(26H_0FH, 0x26, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
752 IAPDESCR(26H_10H, 0x26, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
753 IAPDESCR(26H_20H, 0x26, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
754 IAPDESCR(26H_40H, 0x26, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
755 IAPDESCR(26H_80H, 0x26, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
756 IAPDESCR(26H_F0H, 0x26, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
757 IAPDESCR(26H_FFH, 0x26, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
759 IAPDESCR(27H, 0x27, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2),
760 IAPDESCR(27H_01H, 0x27, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
761 IAPDESCR(27H_02H, 0x27, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
762 IAPDESCR(27H_04H, 0x27, 0x04, IAP_F_FM | IAP_F_I7O),
763 IAPDESCR(27H_08H, 0x27, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
764 IAPDESCR(27H_0EH, 0x27, 0x0E, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
765 IAPDESCR(27H_0FH, 0x27, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
766 IAPDESCR(27H_10H, 0x27, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
767 IAPDESCR(27H_20H, 0x27, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
768 IAPDESCR(27H_40H, 0x27, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
769 IAPDESCR(27H_80H, 0x27, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
770 IAPDESCR(27H_E0H, 0x27, 0xE0, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
771 IAPDESCR(27H_F0H, 0x27, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
773 IAPDESCR(28H, 0x28, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2),
774 IAPDESCR(28H_01H, 0x28, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
775 IAPDESCR(28H_02H, 0x28, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
776 IAPDESCR(28H_04H, 0x28, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
777 IAPDESCR(28H_08H, 0x28, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
778 IAPDESCR(28H_0FH, 0x28, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
780 IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI, IAP_F_CC),
781 IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH,
782 IAP_F_CA | IAP_F_CC2),
783 IAPDESCR(2AH, 0x2A, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2),
784 IAPDESCR(2BH, 0x2B, IAP_M_CORE | IAP_M_MESI, IAP_F_CA | IAP_F_CC2),
786 IAPDESCR(2EH, 0x2E, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH,
788 IAPDESCR(2EH_01H, 0x2E, 0x01, IAP_F_FM | IAP_F_WM),
789 IAPDESCR(2EH_02H, 0x2E, 0x02, IAP_F_FM | IAP_F_WM),
790 IAPDESCR(2EH_41H, 0x2E, 0x41, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7),
791 IAPDESCR(2EH_4FH, 0x2E, 0x4F, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7),
793 IAPDESCR(30H, 0x30, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH,
795 IAPDESCR(32H, 0x32, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, IAP_F_CC),
796 IAPDESCR(32H, 0x32, IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
798 IAPDESCR(3AH, 0x3A, IAP_M_TRANSITION, IAP_F_CC),
799 IAPDESCR(3AH_00H, 0x3A, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
801 IAPDESCR(3BH_C0H, 0x3B, 0xC0, IAP_F_FM | IAP_F_ALLCPUSCORE2),
803 IAPDESCR(3CH_00H, 0x3C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
804 IAP_F_I7 | IAP_F_WM),
805 IAPDESCR(3CH_01H, 0x3C, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
806 IAP_F_I7 | IAP_F_WM),
807 IAPDESCR(3CH_02H, 0x3C, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2),
809 IAPDESCR(3DH_01H, 0x3D, 0x01, IAP_F_FM | IAP_F_I7O),
811 IAPDESCR(40H, 0x40, IAP_M_MESI, IAP_F_CC | IAP_F_CC2),
812 IAPDESCR(40H_01H, 0x40, 0x01, IAP_F_FM | IAP_F_I7),
813 IAPDESCR(40H_02H, 0x40, 0x02, IAP_F_FM | IAP_F_I7),
814 IAPDESCR(40H_04H, 0x40, 0x04, IAP_F_FM | IAP_F_I7),
815 IAPDESCR(40H_08H, 0x40, 0x08, IAP_F_FM | IAP_F_I7),
816 IAPDESCR(40H_0FH, 0x40, 0x0F, IAP_F_FM | IAP_F_I7),
817 IAPDESCR(40H_21H, 0x40, 0x21, IAP_F_FM | IAP_F_CA),
819 IAPDESCR(41H, 0x41, IAP_M_MESI, IAP_F_CC | IAP_F_CC2),
820 IAPDESCR(41H_01H, 0x41, 0x01, IAP_F_FM | IAP_F_I7O),
821 IAPDESCR(41H_02H, 0x41, 0x02, IAP_F_FM | IAP_F_I7),
822 IAPDESCR(41H_04H, 0x41, 0x04, IAP_F_FM | IAP_F_I7),
823 IAPDESCR(41H_08H, 0x41, 0x08, IAP_F_FM | IAP_F_I7),
824 IAPDESCR(41H_0FH, 0x41, 0x0F, IAP_F_FM | IAP_F_I7O),
825 IAPDESCR(41H_22H, 0x41, 0x22, IAP_F_FM | IAP_F_CA),
827 IAPDESCR(42H, 0x42, IAP_M_MESI, IAP_F_ALLCPUSCORE2),
828 IAPDESCR(42H_01H, 0x42, 0x01, IAP_F_FM | IAP_F_I7),
829 IAPDESCR(42H_02H, 0x42, 0x02, IAP_F_FM | IAP_F_I7),
830 IAPDESCR(42H_04H, 0x42, 0x04, IAP_F_FM | IAP_F_I7),
831 IAPDESCR(42H_08H, 0x42, 0x08, IAP_F_FM | IAP_F_I7),
832 IAPDESCR(42H_10H, 0x42, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
834 IAPDESCR(43H_01H, 0x43, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
836 IAPDESCR(43H_02H, 0x43, 0x02, IAP_F_FM | IAP_F_CA |
837 IAP_F_CC2 | IAP_F_I7),
839 IAPDESCR(44H_02H, 0x44, 0x02, IAP_F_FM | IAP_F_CC),
841 IAPDESCR(45H_0FH, 0x45, 0x0F, IAP_F_FM | IAP_F_ALLCPUSCORE2),
843 IAPDESCR(46H_00H, 0x46, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
844 IAPDESCR(47H_00H, 0x47, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
846 IAPDESCR(48H_00H, 0x48, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
847 IAPDESCR(48H_02H, 0x48, 0x02, IAP_F_FM | IAP_F_I7),
849 IAPDESCR(49H_00H, 0x49, 0x00, IAP_F_FM | IAP_F_CC),
850 IAPDESCR(49H_01H, 0x49, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
851 IAP_F_I7 | IAP_F_WM),
852 IAPDESCR(49H_02H, 0x49, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
853 IAP_F_I7 | IAP_F_WM),
854 IAPDESCR(49H_04H, 0x49, 0x04, IAP_F_FM | IAP_F_WM),
855 IAPDESCR(49H_10H, 0x49, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
856 IAPDESCR(49H_20H, 0x49, 0x20, IAP_F_FM | IAP_F_I7O),
857 IAPDESCR(49H_40H, 0x49, 0x40, IAP_F_FM | IAP_F_I7O),
858 IAPDESCR(49H_80H, 0x49, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
860 IAPDESCR(4BH_00H, 0x4B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
861 IAPDESCR(4BH_01H, 0x4B, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7O),
862 IAPDESCR(4BH_02H, 0x4B, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2),
863 IAPDESCR(4BH_03H, 0x4B, 0x03, IAP_F_FM | IAP_F_CC),
864 IAPDESCR(4BH_08H, 0x4B, 0x08, IAP_F_FM | IAP_F_I7O),
866 IAPDESCR(4CH_00H, 0x4C, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
867 IAPDESCR(4CH_01H, 0x4C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
869 IAPDESCR(4DH_01H, 0x4D, 0x01, IAP_F_FM | IAP_F_I7O),
871 IAPDESCR(4EH_01H, 0x4E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
872 IAPDESCR(4EH_02H, 0x4E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
873 IAPDESCR(4EH_04H, 0x4E, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
874 IAPDESCR(4EH_10H, 0x4E, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
876 IAPDESCR(4FH_00H, 0x4F, 0x00, IAP_F_FM | IAP_F_CC),
877 IAPDESCR(4FH_02H, 0x4F, 0x02, IAP_F_FM | IAP_F_I7O),
878 IAPDESCR(4FH_04H, 0x4F, 0x04, IAP_F_FM | IAP_F_I7O),
879 IAPDESCR(4FH_08H, 0x4F, 0x08, IAP_F_FM | IAP_F_I7O),
880 IAPDESCR(4FH_10H, 0x4F, 0x10, IAP_F_FM | IAP_F_WM),
882 IAPDESCR(51H_01H, 0x51, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
883 IAPDESCR(51H_02H, 0x51, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
884 IAPDESCR(51H_04H, 0x51, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
885 IAPDESCR(51H_08H, 0x51, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
887 IAPDESCR(52H_01H, 0x52, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
888 IAPDESCR(53H_01H, 0x53, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
890 IAPDESCR(60H, 0x60, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
891 IAPDESCR(60H_01H, 0x60, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
892 IAPDESCR(60H_02H, 0x60, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
893 IAPDESCR(60H_04H, 0x60, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
894 IAPDESCR(60H_08H, 0x60, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
896 IAPDESCR(61H, 0x61, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2),
897 IAPDESCR(61H_00H, 0x61, 0x00, IAP_F_FM | IAP_F_CC),
899 IAPDESCR(62H, 0x62, IAP_M_AGENT, IAP_F_ALLCPUSCORE2),
900 IAPDESCR(62H_00H, 0x62, 0x00, IAP_F_FM | IAP_F_CC),
902 IAPDESCR(63H, 0x63, IAP_M_AGENT | IAP_M_CORE,
903 IAP_F_CA | IAP_F_CC2),
904 IAPDESCR(63H, 0x63, IAP_M_CORE, IAP_F_CC),
905 IAPDESCR(63H_01H, 0x63, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
906 IAPDESCR(63H_02H, 0x63, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
908 IAPDESCR(64H, 0x64, IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
909 IAPDESCR(64H_40H, 0x64, 0x40, IAP_F_FM | IAP_F_CC),
911 IAPDESCR(65H, 0x65, IAP_M_AGENT | IAP_M_CORE,
912 IAP_F_CA | IAP_F_CC2),
913 IAPDESCR(65H, 0x65, IAP_M_CORE, IAP_F_CC),
915 IAPDESCR(66H, 0x66, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
917 IAPDESCR(67H, 0x67, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
918 IAPDESCR(67H, 0x67, IAP_M_AGENT, IAP_F_CC),
920 IAPDESCR(68H, 0x68, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
921 IAPDESCR(69H, 0x69, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
922 IAPDESCR(6AH, 0x6A, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
923 IAPDESCR(6BH, 0x6B, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
925 IAPDESCR(6CH, 0x6C, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2),
926 IAPDESCR(6CH_01H, 0x6C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
928 IAPDESCR(6DH, 0x6D, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
929 IAPDESCR(6DH, 0x6D, IAP_M_CORE, IAP_F_CC),
931 IAPDESCR(6EH, 0x6E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
932 IAPDESCR(6EH, 0x6E, IAP_M_CORE, IAP_F_CC),
934 IAPDESCR(6FH, 0x6F, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
935 IAPDESCR(6FH, 0x6F, IAP_M_CORE, IAP_F_CC),
937 IAPDESCR(70H, 0x70, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
938 IAPDESCR(70H, 0x70, IAP_M_CORE, IAP_F_CC),
940 IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_SNOOPRESPONSE,
941 IAP_F_CA | IAP_F_CC2),
942 IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_MESI, IAP_F_CC),
944 IAPDESCR(78H, 0x78, IAP_M_CORE, IAP_F_CC),
945 IAPDESCR(78H, 0x78, IAP_M_CORE | IAP_M_SNOOPTYPE, IAP_F_CA | IAP_F_CC2),
947 IAPDESCR(7AH, 0x7A, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2),
949 IAPDESCR(7BH, 0x7B, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2),
951 IAPDESCR(7DH, 0x7D, IAP_M_CORE, IAP_F_ALLCPUSCORE2),
953 IAPDESCR(7EH, 0x7E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
954 IAPDESCR(7EH_00H, 0x7E, 0x00, IAP_F_FM | IAP_F_CC),
956 IAPDESCR(7FH, 0x7F, IAP_M_CORE, IAP_F_CA | IAP_F_CC2),
958 IAPDESCR(80H_00H, 0x80, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
959 IAPDESCR(80H_01H, 0x80, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
960 IAPDESCR(80H_02H, 0x80, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
962 IAPDESCR(80H_03H, 0x80, 0x03, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
964 IAPDESCR(80H_04H, 0x80, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
966 IAPDESCR(81H_00H, 0x81, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
967 IAPDESCR(81H_01H, 0x81, 0x01, IAP_F_FM | IAP_F_I7O),
968 IAPDESCR(81H_02H, 0x81, 0x02, IAP_F_FM | IAP_F_I7O),
970 IAPDESCR(82H_01H, 0x82, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
971 IAPDESCR(82H_02H, 0x82, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
972 IAPDESCR(82H_04H, 0x82, 0x04, IAP_F_FM | IAP_F_CA),
973 IAPDESCR(82H_10H, 0x82, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
974 IAPDESCR(82H_12H, 0x82, 0x12, IAP_F_FM | IAP_F_CC2),
975 IAPDESCR(82H_40H, 0x82, 0x40, IAP_F_FM | IAP_F_CC2),
977 IAPDESCR(83H_01H, 0x83, 0x01, IAP_F_FM | IAP_F_I7O),
978 IAPDESCR(83H_02H, 0x83, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
980 IAPDESCR(85H_00H, 0x85, 0x00, IAP_F_FM | IAP_F_CC),
981 IAPDESCR(85H_01H, 0x85, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
982 IAPDESCR(85H_02H, 0x85, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
983 IAPDESCR(85H_04H, 0x85, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
984 IAPDESCR(85H_10H, 0x85, 0x10, IAP_F_FM | IAP_F_I7O),
985 IAPDESCR(85H_20H, 0x85, 0x20, IAP_F_FM | IAP_F_I7O),
986 IAPDESCR(85H_40H, 0x85, 0x40, IAP_F_FM | IAP_F_I7O),
987 IAPDESCR(85H_80H, 0x85, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
989 IAPDESCR(86H_00H, 0x86, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
991 IAPDESCR(87H_00H, 0x87, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
992 IAPDESCR(87H_01H, 0x87, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
993 IAPDESCR(87H_02H, 0x87, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
994 IAPDESCR(87H_04H, 0x87, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
995 IAPDESCR(87H_08H, 0x87, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
996 IAPDESCR(87H_0FH, 0x87, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
998 IAPDESCR(88H_00H, 0x88, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
999 IAPDESCR(88H_01H, 0x88, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1000 IAPDESCR(88H_02H, 0x88, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1001 IAPDESCR(88H_04H, 0x88, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1002 IAPDESCR(88H_07H, 0x88, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1003 IAPDESCR(88H_08H, 0x88, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1004 IAPDESCR(88H_10H, 0x88, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1005 IAPDESCR(88H_20H, 0x88, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1006 IAPDESCR(88H_30H, 0x88, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1007 IAPDESCR(88H_40H, 0x88, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1008 IAPDESCR(88H_7FH, 0x88, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1010 IAPDESCR(89H_00H, 0x89, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1011 IAPDESCR(89H_01H, 0x89, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1012 IAPDESCR(89H_02H, 0x89, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1013 IAPDESCR(89H_04H, 0x89, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1014 IAPDESCR(89H_07H, 0x89, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1015 IAPDESCR(89H_08H, 0x89, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1016 IAPDESCR(89H_10H, 0x89, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1017 IAPDESCR(89H_20H, 0x89, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1018 IAPDESCR(89H_30H, 0x89, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1019 IAPDESCR(89H_40H, 0x89, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1020 IAPDESCR(89H_7FH, 0x89, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1022 IAPDESCR(8AH_00H, 0x8A, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1023 IAPDESCR(8BH_00H, 0x8B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1024 IAPDESCR(8CH_00H, 0x8C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1025 IAPDESCR(8DH_00H, 0x8D, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1026 IAPDESCR(8EH_00H, 0x8E, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1027 IAPDESCR(8FH_00H, 0x8F, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1029 IAPDESCR(90H_00H, 0x90, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1030 IAPDESCR(91H_00H, 0x91, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1031 IAPDESCR(92H_00H, 0x92, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1032 IAPDESCR(93H_00H, 0x93, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1033 IAPDESCR(94H_00H, 0x94, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1035 IAPDESCR(97H_00H, 0x97, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1036 IAPDESCR(98H_00H, 0x98, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1037 IAPDESCR(A0H_00H, 0xA0, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1039 IAPDESCR(A1H_01H, 0xA1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1040 IAPDESCR(A1H_02H, 0xA1, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1041 IAPDESCR(A1H_04H, 0xA1, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1042 IAPDESCR(A1H_08H, 0xA1, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1043 IAPDESCR(A1H_10H, 0xA1, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1044 IAPDESCR(A1H_20H, 0xA1, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1046 IAPDESCR(A2H_00H, 0xA2, 0x00, IAP_F_FM | IAP_F_CC),
1047 IAPDESCR(A2H_01H, 0xA2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1048 IAPDESCR(A2H_02H, 0xA2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1049 IAPDESCR(A2H_04H, 0xA2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1050 IAPDESCR(A2H_08H, 0xA2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1051 IAPDESCR(A2H_10H, 0xA2, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1052 IAPDESCR(A2H_20H, 0xA2, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1053 IAPDESCR(A2H_40H, 0xA2, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1054 IAPDESCR(A2H_80H, 0xA2, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1056 IAPDESCR(A6H_01H, 0xA6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1057 IAPDESCR(A7H_01H, 0xA7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1058 IAPDESCR(A8H_01H, 0xA8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1060 IAPDESCR(AAH_01H, 0xAA, 0x01, IAP_F_FM | IAP_F_CC2),
1061 IAPDESCR(AAH_02H, 0xAA, 0x02, IAP_F_FM | IAP_F_CA),
1062 IAPDESCR(AAH_03H, 0xAA, 0x03, IAP_F_FM | IAP_F_CA),
1063 IAPDESCR(AAH_08H, 0xAA, 0x08, IAP_F_FM | IAP_F_CC2),
1065 IAPDESCR(ABH_01H, 0xAB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1066 IAPDESCR(ABH_02H, 0xAB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1068 IAPDESCR(AEH_01H, 0xAE, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1070 IAPDESCR(B0H_00H, 0xB0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1071 IAPDESCR(B0H_01H, 0xB0, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
1072 IAPDESCR(B0H_02H, 0xB0, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
1073 IAPDESCR(B0H_04H, 0xB0, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
1074 IAPDESCR(B0H_08H, 0xB0, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
1075 IAPDESCR(B0H_10H, 0xB0, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
1076 IAPDESCR(B0H_20H, 0xB0, 0x20, IAP_F_FM | IAP_F_I7O),
1077 IAPDESCR(B0H_40H, 0xB0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1078 IAPDESCR(B0H_80H, 0xB0, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_WM | IAP_F_I7O),
1080 IAPDESCR(B1H_00H, 0xB1, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1081 IAPDESCR(B1H_01H, 0xB1, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1082 IAPDESCR(B1H_02H, 0xB1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1083 IAPDESCR(B1H_04H, 0xB1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1084 IAPDESCR(B1H_08H, 0xB1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1085 IAPDESCR(B1H_10H, 0xB1, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1086 IAPDESCR(B1H_1FH, 0xB1, 0x1F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1087 IAPDESCR(B1H_20H, 0xB1, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1088 IAPDESCR(B1H_3FH, 0xB1, 0x3F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1089 IAPDESCR(B1H_40H, 0xB1, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1090 IAPDESCR(B1H_80H, 0xB1, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
1093 IAPDESCR(B2H_01H, 0xB2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1095 IAPDESCR(B3H_01H, 0xB3, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
1096 IAP_F_WM | IAP_F_I7O),
1097 IAPDESCR(B3H_02H, 0xB3, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
1098 IAP_F_WM | IAP_F_I7O),
1099 IAPDESCR(B3H_04H, 0xB3, 0x04, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
1100 IAP_F_WM | IAP_F_I7O),
1101 IAPDESCR(B3H_08H, 0xB3, 0x08, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1102 IAPDESCR(B3H_10H, 0xB3, 0x10, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1103 IAPDESCR(B3H_20H, 0xB3, 0x20, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1104 IAPDESCR(B3H_81H, 0xB3, 0x81, IAP_F_FM | IAP_F_CA),
1105 IAPDESCR(B3H_82H, 0xB3, 0x82, IAP_F_FM | IAP_F_CA),
1106 IAPDESCR(B3H_84H, 0xB3, 0x84, IAP_F_FM | IAP_F_CA),
1107 IAPDESCR(B3H_88H, 0xB3, 0x88, IAP_F_FM | IAP_F_CA),
1108 IAPDESCR(B3H_90H, 0xB3, 0x90, IAP_F_FM | IAP_F_CA),
1109 IAPDESCR(B3H_A0H, 0xB3, 0xA0, IAP_F_FM | IAP_F_CA),
1111 IAPDESCR(B4H_01H, 0xB4, 0x01, IAP_F_FM | IAP_F_WM),
1112 IAPDESCR(B4H_02H, 0xB4, 0x02, IAP_F_FM | IAP_F_WM),
1113 IAPDESCR(B4H_04H, 0xB4, 0x04, IAP_F_FM | IAP_F_WM),
1115 IAPDESCR(B7H_01H, 0xB7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1117 IAPDESCR(B8H_01H, 0xB8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1118 IAPDESCR(B8H_02H, 0xB8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1119 IAPDESCR(B8H_04H, 0xB8, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1121 IAPDESCR(BAH_01H, 0xBA, 0x01, IAP_F_FM | IAP_F_I7O),
1122 IAPDESCR(BAH_02H, 0xBA, 0x02, IAP_F_FM | IAP_F_I7O),
1124 IAPDESCR(BBH_01H, 0xBB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1126 IAPDESCR(C0H_00H, 0xC0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1127 IAPDESCR(C0H_01H, 0xC0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1128 IAP_F_I7 | IAP_F_WM),
1129 IAPDESCR(C0H_02H, 0xC0, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1130 IAP_F_I7 | IAP_F_WM),
1131 IAPDESCR(C0H_04H, 0xC0, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1132 IAP_F_I7 | IAP_F_WM),
1133 IAPDESCR(C0H_08H, 0xC0, 0x08, IAP_F_FM | IAP_F_CC2E),
1135 IAPDESCR(C1H_00H, 0xC1, 0x00, IAP_F_FM | IAP_F_CC),
1136 IAPDESCR(C1H_01H, 0xC1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1137 IAPDESCR(C1H_FEH, 0xC1, 0xFE, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1139 IAPDESCR(C2H_00H, 0xC2, 0x00, IAP_F_FM | IAP_F_CC),
1140 IAPDESCR(C2H_01H, 0xC2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1141 IAP_F_I7 | IAP_F_WM),
1142 IAPDESCR(C2H_02H, 0xC2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1143 IAP_F_I7 | IAP_F_WM),
1144 IAPDESCR(C2H_04H, 0xC2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1145 IAP_F_I7 | IAP_F_WM),
1146 IAPDESCR(C2H_07H, 0xC2, 0x07, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1147 IAPDESCR(C2H_08H, 0xC2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1148 IAPDESCR(C2H_0FH, 0xC2, 0x0F, IAP_F_FM | IAP_F_CC2),
1149 IAPDESCR(C2H_10H, 0xC2, 0x10, IAP_F_FM | IAP_F_CA),
1151 IAPDESCR(C3H_00H, 0xC3, 0x00, IAP_F_FM | IAP_F_CC),
1152 IAPDESCR(C3H_01H, 0xC3, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1153 IAP_F_I7 | IAP_F_WM),
1154 IAPDESCR(C3H_02H, 0xC3, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1155 IAPDESCR(C3H_04H, 0xC3, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1156 IAP_F_I7 | IAP_F_WM),
1157 IAPDESCR(C3H_10H, 0xC3, 0x10, IAP_F_FM | IAP_F_I7O),
1159 IAPDESCR(C4H_00H, 0xC4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
1160 IAP_F_I7 | IAP_F_WM),
1161 IAPDESCR(C4H_01H, 0xC4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1162 IAP_F_I7 | IAP_F_WM),
1163 IAPDESCR(C4H_02H, 0xC4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1164 IAP_F_I7 | IAP_F_WM),
1165 IAPDESCR(C4H_04H, 0xC4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1166 IAP_F_I7 | IAP_F_WM),
1167 IAPDESCR(C4H_08H, 0xC4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1168 IAPDESCR(C4H_0CH, 0xC4, 0x0C, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1169 IAPDESCR(C4H_0FH, 0xC4, 0x0F, IAP_F_FM | IAP_F_CA),
1171 IAPDESCR(C5H_00H, 0xC5, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
1172 IAP_F_I7 | IAP_F_WM),
1173 IAPDESCR(C5H_01H, 0xC5, 0x01, IAP_F_FM | IAP_F_WM),
1174 IAPDESCR(C5H_02H, 0xC5, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1175 IAPDESCR(C5H_04H, 0xC5, 0x04, IAP_F_FM | IAP_F_WM),
1177 IAPDESCR(C6H_00H, 0xC6, 0x00, IAP_F_FM | IAP_F_CC),
1178 IAPDESCR(C6H_01H, 0xC6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1179 IAPDESCR(C6H_02H, 0xC6, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1181 IAPDESCR(C7H_00H, 0xC7, 0x00, IAP_F_FM | IAP_F_CC),
1182 IAPDESCR(C7H_01H, 0xC7, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1183 IAP_F_I7 | IAP_F_WM),
1184 IAPDESCR(C7H_02H, 0xC7, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1185 IAP_F_I7 | IAP_F_WM),
1186 IAPDESCR(C7H_04H, 0xC7, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1187 IAP_F_I7 | IAP_F_WM),
1188 IAPDESCR(C7H_08H, 0xC7, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1189 IAP_F_I7 | IAP_F_WM),
1190 IAPDESCR(C7H_10H, 0xC7, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1191 IAP_F_I7 | IAP_F_WM),
1192 IAPDESCR(C7H_1FH, 0xC7, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1194 IAPDESCR(C8H_00H, 0xC8, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1195 IAPDESCR(C8H_20H, 0xC8, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1197 IAPDESCR(C9H_00H, 0xC9, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1199 IAPDESCR(CAH_00H, 0xCA, 0x00, IAP_F_FM | IAP_F_CC),
1200 IAPDESCR(CAH_01H, 0xCA, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1201 IAPDESCR(CAH_02H, 0xCA, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1202 IAPDESCR(CAH_04H, 0xCA, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1203 IAPDESCR(CAH_08H, 0xCA, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1205 IAPDESCR(CBH_01H, 0xCB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1206 IAP_F_I7 | IAP_F_WM),
1207 IAPDESCR(CBH_02H, 0xCB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1208 IAP_F_I7 | IAP_F_WM),
1209 IAPDESCR(CBH_04H, 0xCB, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1210 IAP_F_I7 | IAP_F_WM),
1211 IAPDESCR(CBH_08H, 0xCB, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1212 IAP_F_I7 | IAP_F_WM),
1213 IAPDESCR(CBH_10H, 0xCB, 0x10, IAP_F_FM | IAP_F_CC2 | IAP_F_I7 |
1215 IAPDESCR(CBH_40H, 0xCB, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1216 IAPDESCR(CBH_80H, 0xCB, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1218 IAPDESCR(CCH_00H, 0xCC, 0x00, IAP_F_FM | IAP_F_CC),
1219 IAPDESCR(CCH_01H, 0xCC, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 |
1220 IAP_F_I7 | IAP_F_WM),
1221 IAPDESCR(CCH_02H, 0xCC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1222 IAP_F_I7 | IAP_F_WM),
1223 IAPDESCR(CCH_03H, 0xCC, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1225 IAPDESCR(CDH_00H, 0xCD, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1226 IAPDESCR(CEH_00H, 0xCE, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1227 IAPDESCR(CFH_00H, 0xCF, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1229 IAPDESCR(D0H_00H, 0xD0, 0x00, IAP_F_FM | IAP_F_CC),
1230 IAPDESCR(D0H_01H, 0xD0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1232 IAPDESCR(D1H_01H, 0xD1, 0x01, IAP_F_FM | IAP_F_WM),
1233 IAPDESCR(D1H_02H, 0xD1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1234 IAPDESCR(D1H_04H, 0xD1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1235 IAPDESCR(D1H_08H, 0xD1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1237 IAPDESCR(D2H_01H, 0xD2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1238 IAP_F_I7 | IAP_F_WM),
1239 IAPDESCR(D2H_02H, 0xD2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1240 IAP_F_I7 | IAP_F_WM),
1241 IAPDESCR(D2H_04H, 0xD2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1242 IAP_F_I7 | IAP_F_WM),
1243 IAPDESCR(D2H_08H, 0xD2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1244 IAP_F_I7 | IAP_F_WM),
1245 IAPDESCR(D2H_0FH, 0xD2, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1246 IAP_F_I7 | IAP_F_WM),
1247 IAPDESCR(D2H_10H, 0xD2, 0x10, IAP_F_FM | IAP_F_CC2E),
1249 IAPDESCR(D4H_01H, 0xD4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1250 IAP_F_I7 | IAP_F_WM),
1251 IAPDESCR(D4H_02H, 0xD4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1252 IAPDESCR(D4H_04H, 0xD4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1253 IAPDESCR(D4H_08H, 0xD4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1254 IAPDESCR(D4H_0FH, 0xD4, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1256 IAPDESCR(D5H_01H, 0xD5, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
1257 IAP_F_I7 | IAP_F_WM),
1258 IAPDESCR(D5H_02H, 0xD5, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1259 IAPDESCR(D5H_04H, 0xD5, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1260 IAPDESCR(D5H_08H, 0xD5, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1261 IAPDESCR(D5H_0FH, 0xD5, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1263 IAPDESCR(D7H_00H, 0xD7, 0x00, IAP_F_FM | IAP_F_CC),
1265 IAPDESCR(D8H_00H, 0xD8, 0x00, IAP_F_FM | IAP_F_CC),
1266 IAPDESCR(D8H_01H, 0xD8, 0x01, IAP_F_FM | IAP_F_CC),
1267 IAPDESCR(D8H_02H, 0xD8, 0x02, IAP_F_FM | IAP_F_CC),
1268 IAPDESCR(D8H_03H, 0xD8, 0x03, IAP_F_FM | IAP_F_CC),
1269 IAPDESCR(D8H_04H, 0xD8, 0x04, IAP_F_FM | IAP_F_CC),
1271 IAPDESCR(D9H_00H, 0xD9, 0x00, IAP_F_FM | IAP_F_CC),
1272 IAPDESCR(D9H_01H, 0xD9, 0x01, IAP_F_FM | IAP_F_CC),
1273 IAPDESCR(D9H_02H, 0xD9, 0x02, IAP_F_FM | IAP_F_CC),
1274 IAPDESCR(D9H_03H, 0xD9, 0x03, IAP_F_FM | IAP_F_CC),
1276 IAPDESCR(DAH_00H, 0xDA, 0x00, IAP_F_FM | IAP_F_CC),
1277 IAPDESCR(DAH_01H, 0xDA, 0x01, IAP_F_FM | IAP_F_CC),
1278 IAPDESCR(DAH_02H, 0xDA, 0x02, IAP_F_FM | IAP_F_CC),
1280 IAPDESCR(DBH_00H, 0xDB, 0x00, IAP_F_FM | IAP_F_CC),
1281 IAPDESCR(DBH_01H, 0xDB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1283 IAPDESCR(DCH_01H, 0xDC, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1284 IAPDESCR(DCH_02H, 0xDC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1285 IAPDESCR(DCH_04H, 0xDC, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1286 IAPDESCR(DCH_08H, 0xDC, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1287 IAPDESCR(DCH_10H, 0xDC, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1288 IAPDESCR(DCH_1FH, 0xDC, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2),
1290 IAPDESCR(E0H_00H, 0xE0, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2),
1291 IAPDESCR(E0H_01H, 0xE0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
1294 IAPDESCR(E2H_00H, 0xE2, 0x00, IAP_F_FM | IAP_F_CC),
1296 IAPDESCR(E4H_00H, 0xE4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1297 IAPDESCR(E4H_01H, 0xE4, 0x01, IAP_F_FM | IAP_F_I7O),
1299 IAPDESCR(E5H_01H, 0xE5, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1301 IAPDESCR(E6H_00H, 0xE6, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2),
1302 IAPDESCR(E6H_01H, 0xE6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 |
1304 IAPDESCR(E6H_02H, 0xE6, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1306 IAPDESCR(E8H_01H, 0xE8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1307 IAPDESCR(E8H_02H, 0xE8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1308 IAPDESCR(E8H_03H, 0xE8, 0x03, IAP_F_FM | IAP_F_I7),
1310 IAPDESCR(ECH_01H, 0xEC, 0x01, IAP_F_FM | IAP_F_WM),
1312 IAPDESCR(F0H_00H, 0xF0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1313 IAPDESCR(F0H_01H, 0xF0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1314 IAPDESCR(F0H_02H, 0xF0, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1315 IAPDESCR(F0H_04H, 0xF0, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1316 IAPDESCR(F0H_08H, 0xF0, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1317 IAPDESCR(F0H_10H, 0xF0, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1318 IAPDESCR(F0H_20H, 0xF0, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1319 IAPDESCR(F0H_40H, 0xF0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1320 IAPDESCR(F0H_80H, 0xF0, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1322 IAPDESCR(F1H_02H, 0xF1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1323 IAPDESCR(F1H_04H, 0xF1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1324 IAPDESCR(F1H_07H, 0xF1, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1326 IAPDESCR(F2H_01H, 0xF2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1327 IAPDESCR(F2H_02H, 0xF2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1328 IAPDESCR(F2H_04H, 0xF2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1329 IAPDESCR(F2H_08H, 0xF2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1330 IAPDESCR(F2H_0FH, 0xF2, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1332 IAPDESCR(F3H_01H, 0xF3, 0x01, IAP_F_FM | IAP_F_I7O),
1333 IAPDESCR(F3H_02H, 0xF3, 0x02, IAP_F_FM | IAP_F_I7O),
1334 IAPDESCR(F3H_04H, 0xF3, 0x04, IAP_F_FM | IAP_F_I7O),
1335 IAPDESCR(F3H_08H, 0xF3, 0x08, IAP_F_FM | IAP_F_I7O),
1336 IAPDESCR(F3H_10H, 0xF3, 0x10, IAP_F_FM | IAP_F_I7O),
1337 IAPDESCR(F3H_20H, 0xF3, 0x20, IAP_F_FM | IAP_F_I7O),
1339 IAPDESCR(F4H_01H, 0xF4, 0x01, IAP_F_FM | IAP_F_I7O),
1340 IAPDESCR(F4H_02H, 0xF4, 0x02, IAP_F_FM | IAP_F_I7O),
1341 IAPDESCR(F4H_04H, 0xF4, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O),
1342 IAPDESCR(F4H_08H, 0xF4, 0x08, IAP_F_FM | IAP_F_I7O),
1343 IAPDESCR(F4H_10H, 0xF4, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1345 IAPDESCR(F6H_01H, 0xF6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
1347 IAPDESCR(F7H_01H, 0xF7, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1348 IAPDESCR(F7H_02H, 0xF7, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1349 IAPDESCR(F7H_04H, 0xF7, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1351 IAPDESCR(F8H_00H, 0xF8, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
1352 IAPDESCR(F8H_01H, 0xF8, 0x01, IAP_F_FM | IAP_F_I7O),
1354 IAPDESCR(FDH_01H, 0xFD, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1355 IAPDESCR(FDH_02H, 0xFD, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1356 IAPDESCR(FDH_04H, 0xFD, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1357 IAPDESCR(FDH_08H, 0xFD, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1358 IAPDESCR(FDH_10H, 0xFD, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1359 IAPDESCR(FDH_20H, 0xFD, 0x20, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1360 IAPDESCR(FDH_40H, 0xFD, 0x40, IAP_F_FM | IAP_F_WM | IAP_F_I7),
1363 static const int niap_events = sizeof(iap_events) / sizeof(iap_events[0]);
1366 iap_perfctr_value_to_reload_count(pmc_value_t v)
1368 v &= (1ULL << core_iap_width) - 1;
1369 return (1ULL << core_iap_width) - v;
1373 iap_reload_count_to_perfctr_value(pmc_value_t rlc)
1375 return (1ULL << core_iap_width) - rlc;
1379 iap_pmc_has_overflowed(int ri)
1384 * We treat a Core (i.e., Intel architecture v1) PMC as has
1385 * having overflowed if its MSB is zero.
1388 return ((v & (1ULL << (core_iap_width - 1))) == 0);
1392 * Check an event against the set of supported architectural events.
1394 * Returns 1 if the event is architectural and unsupported on this
1395 * CPU. Returns 0 otherwise.
1399 iap_architectural_event_is_unsupported(enum pmc_event pe)
1401 enum core_arch_events ae;
1404 case PMC_EV_IAP_EVENT_3CH_00H:
1405 ae = CORE_AE_UNHALTED_CORE_CYCLES;
1407 case PMC_EV_IAP_EVENT_C0H_00H:
1408 ae = CORE_AE_INSTRUCTION_RETIRED;
1410 case PMC_EV_IAP_EVENT_3CH_01H:
1411 ae = CORE_AE_UNHALTED_REFERENCE_CYCLES;
1413 case PMC_EV_IAP_EVENT_2EH_4FH:
1414 ae = CORE_AE_LLC_REFERENCE;
1416 case PMC_EV_IAP_EVENT_2EH_41H:
1417 ae = CORE_AE_LLC_MISSES;
1419 case PMC_EV_IAP_EVENT_C4H_00H:
1420 ae = CORE_AE_BRANCH_INSTRUCTION_RETIRED;
1422 case PMC_EV_IAP_EVENT_C5H_00H:
1423 ae = CORE_AE_BRANCH_MISSES_RETIRED;
1426 default: /* Non architectural event. */
1430 return ((core_architectural_events & (1 << ae)) == 0);
1434 iap_event_corei7_ok_on_counter(enum pmc_event pe, int ri)
1440 * Events valid only on counter 0, 1.
1442 case PMC_EV_IAP_EVENT_40H_01H:
1443 case PMC_EV_IAP_EVENT_40H_02H:
1444 case PMC_EV_IAP_EVENT_40H_04H:
1445 case PMC_EV_IAP_EVENT_40H_08H:
1446 case PMC_EV_IAP_EVENT_40H_0FH:
1447 case PMC_EV_IAP_EVENT_41H_02H:
1448 case PMC_EV_IAP_EVENT_41H_04H:
1449 case PMC_EV_IAP_EVENT_41H_08H:
1450 case PMC_EV_IAP_EVENT_42H_01H:
1451 case PMC_EV_IAP_EVENT_42H_02H:
1452 case PMC_EV_IAP_EVENT_42H_04H:
1453 case PMC_EV_IAP_EVENT_42H_08H:
1454 case PMC_EV_IAP_EVENT_43H_01H:
1455 case PMC_EV_IAP_EVENT_43H_02H:
1456 case PMC_EV_IAP_EVENT_48H_02H:
1457 case PMC_EV_IAP_EVENT_51H_01H:
1458 case PMC_EV_IAP_EVENT_51H_02H:
1459 case PMC_EV_IAP_EVENT_51H_04H:
1460 case PMC_EV_IAP_EVENT_51H_08H:
1461 case PMC_EV_IAP_EVENT_63H_01H:
1462 case PMC_EV_IAP_EVENT_63H_02H:
1467 mask = ~0; /* Any row index is ok. */
1470 return (mask & (1 << ri));
1474 iap_event_westmere_ok_on_counter(enum pmc_event pe, int ri)
1480 * Events valid only on counter 0.
1482 case PMC_EV_IAP_EVENT_B3H_01H:
1483 case PMC_EV_IAP_EVENT_B3H_02H:
1484 case PMC_EV_IAP_EVENT_B3H_04H:
1489 * Events valid only on counter 0, 1.
1491 case PMC_EV_IAP_EVENT_51H_01H:
1492 case PMC_EV_IAP_EVENT_51H_02H:
1493 case PMC_EV_IAP_EVENT_51H_04H:
1494 case PMC_EV_IAP_EVENT_51H_08H:
1495 case PMC_EV_IAP_EVENT_63H_01H:
1496 case PMC_EV_IAP_EVENT_63H_02H:
1501 mask = ~0; /* Any row index is ok. */
1504 return (mask & (1 << ri));
1508 iap_event_ok_on_counter(enum pmc_event pe, int ri)
1514 * Events valid only on counter 0.
1516 case PMC_EV_IAP_EVENT_10H_00H:
1517 case PMC_EV_IAP_EVENT_14H_00H:
1518 case PMC_EV_IAP_EVENT_18H_00H:
1519 case PMC_EV_IAP_EVENT_B3H_01H:
1520 case PMC_EV_IAP_EVENT_B3H_02H:
1521 case PMC_EV_IAP_EVENT_B3H_04H:
1522 case PMC_EV_IAP_EVENT_C1H_00H:
1523 case PMC_EV_IAP_EVENT_CBH_01H:
1524 case PMC_EV_IAP_EVENT_CBH_02H:
1529 * Events valid only on counter 1.
1531 case PMC_EV_IAP_EVENT_11H_00H:
1532 case PMC_EV_IAP_EVENT_12H_00H:
1533 case PMC_EV_IAP_EVENT_13H_00H:
1538 mask = ~0; /* Any row index is ok. */
1541 return (mask & (1 << ri));
1545 iap_allocate_pmc(int cpu, int ri, struct pmc *pm,
1546 const struct pmc_op_pmcallocate *a)
1550 struct iap_event_descr *ie;
1551 uint32_t c, caps, config, cpuflag, evsel, mask;
1553 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
1554 ("[core,%d] illegal CPU %d", __LINE__, cpu));
1555 KASSERT(ri >= 0 && ri < core_iap_npmc,
1556 ("[core,%d] illegal row-index value %d", __LINE__, ri));
1558 /* check requested capabilities */
1560 if ((IAP_PMC_CAPS & caps) != caps)
1565 if (iap_architectural_event_is_unsupported(ev))
1566 return (EOPNOTSUPP);
1568 switch (core_cputype) {
1569 case PMC_CPU_INTEL_COREI7:
1570 if (iap_event_corei7_ok_on_counter(ev, ri) == 0)
1573 case PMC_CPU_INTEL_WESTMERE:
1574 if (iap_event_westmere_ok_on_counter(ev, ri) == 0)
1578 if (iap_event_ok_on_counter(ev, ri) == 0)
1583 * Look for an event descriptor with matching CPU and event id
1587 switch (core_cputype) {
1589 case PMC_CPU_INTEL_ATOM:
1592 case PMC_CPU_INTEL_CORE:
1595 case PMC_CPU_INTEL_CORE2:
1596 cpuflag = IAP_F_CC2;
1598 case PMC_CPU_INTEL_CORE2EXTREME:
1599 cpuflag = IAP_F_CC2 | IAP_F_CC2E;
1601 case PMC_CPU_INTEL_COREI7:
1604 case PMC_CPU_INTEL_WESTMERE:
1609 for (n = 0, ie = iap_events; n < niap_events; n++, ie++)
1610 if (ie->iap_ev == ev && ie->iap_flags & cpuflag)
1613 if (n == niap_events)
1617 * A matching event descriptor has been found, so start
1618 * assembling the contents of the event select register.
1620 evsel = ie->iap_evcode;
1622 config = a->pm_md.pm_iap.pm_iap_config & ~IAP_F_CMASK;
1625 * If the event uses a fixed umask value, reject any umask
1626 * bits set by the user.
1628 if (ie->iap_flags & IAP_F_FM) {
1630 if (IAP_UMASK(config) != 0)
1633 evsel |= (ie->iap_umask << 8);
1638 * Otherwise, the UMASK value needs to be taken from
1639 * the MD fields of the allocation request. Reject
1640 * requests that specify reserved bits.
1645 if (ie->iap_umask & IAP_M_CORE) {
1646 if ((c = (config & IAP_F_CORE)) != IAP_CORE_ALL &&
1652 if (ie->iap_umask & IAP_M_AGENT)
1653 mask |= IAP_F_AGENT;
1655 if (ie->iap_umask & IAP_M_PREFETCH) {
1657 if ((c = (config & IAP_F_PREFETCH)) ==
1658 IAP_PREFETCH_RESERVED)
1661 mask |= IAP_F_PREFETCH;
1664 if (ie->iap_umask & IAP_M_MESI)
1667 if (ie->iap_umask & IAP_M_SNOOPRESPONSE)
1668 mask |= IAP_F_SNOOPRESPONSE;
1670 if (ie->iap_umask & IAP_M_SNOOPTYPE)
1671 mask |= IAP_F_SNOOPTYPE;
1673 if (ie->iap_umask & IAP_M_TRANSITION)
1674 mask |= IAP_F_TRANSITION;
1677 * If bits outside of the allowed set of umask bits
1678 * are set, reject the request.
1683 evsel |= (config & mask);
1688 * Only Atom CPUs support the 'ANY' qualifier.
1690 if (core_cputype == PMC_CPU_INTEL_ATOM)
1691 evsel |= (config & IAP_ANY);
1692 else if (config & IAP_ANY)
1696 * Check offcore response configuration.
1698 if (a->pm_md.pm_iap.pm_iap_rsp != 0) {
1699 if (ev != PMC_EV_IAP_EVENT_B7H_01H &&
1700 ev != PMC_EV_IAP_EVENT_BBH_01H)
1702 if (core_cputype == PMC_CPU_INTEL_COREI7 &&
1703 ev == PMC_EV_IAP_EVENT_BBH_01H)
1705 if ( a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK)
1707 pm->pm_md.pm_iap.pm_iap_rsp =
1708 a->pm_md.pm_iap.pm_iap_rsp & IA_OFFCORE_RSP_MASK;
1711 if (caps & PMC_CAP_THRESHOLD)
1712 evsel |= (a->pm_md.pm_iap.pm_iap_config & IAP_F_CMASK);
1713 if (caps & PMC_CAP_USER)
1715 if (caps & PMC_CAP_SYSTEM)
1717 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0)
1718 evsel |= (IAP_OS | IAP_USR);
1719 if (caps & PMC_CAP_EDGE)
1721 if (caps & PMC_CAP_INVERT)
1723 if (caps & PMC_CAP_INTERRUPT)
1726 pm->pm_md.pm_iap.pm_iap_evsel = evsel;
1732 iap_config_pmc(int cpu, int ri, struct pmc *pm)
1734 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
1735 ("[core,%d] illegal CPU %d", __LINE__, cpu));
1737 KASSERT(ri >= 0 && ri < core_iap_npmc,
1738 ("[core,%d] illegal row-index %d", __LINE__, ri));
1740 PMCDBG(MDP,CFG,1, "iap-config cpu=%d ri=%d pm=%p", cpu, ri, pm);
1742 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__,
1745 core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc = pm;
1751 iap_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
1755 char iap_name[PMC_NAME_MAX];
1757 phw = &core_pcpu[cpu]->pc_corepmcs[ri];
1759 (void) snprintf(iap_name, sizeof(iap_name), "IAP-%d", ri);
1760 if ((error = copystr(iap_name, pi->pm_name, PMC_NAME_MAX,
1764 pi->pm_class = PMC_CLASS_IAP;
1766 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
1767 pi->pm_enabled = TRUE;
1768 *ppmc = phw->phw_pmc;
1770 pi->pm_enabled = FALSE;
1778 iap_get_config(int cpu, int ri, struct pmc **ppm)
1780 *ppm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc;
1786 iap_get_msr(int ri, uint32_t *msr)
1788 KASSERT(ri >= 0 && ri < core_iap_npmc,
1789 ("[iap,%d] ri %d out of range", __LINE__, ri));
1797 iap_read_pmc(int cpu, int ri, pmc_value_t *v)
1802 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
1803 ("[core,%d] illegal cpu value %d", __LINE__, cpu));
1804 KASSERT(ri >= 0 && ri < core_iap_npmc,
1805 ("[core,%d] illegal row-index %d", __LINE__, ri));
1807 pm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc;
1810 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu,
1814 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
1815 *v = iap_perfctr_value_to_reload_count(tmp);
1819 PMCDBG(MDP,REA,1, "iap-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri,
1826 iap_release_pmc(int cpu, int ri, struct pmc *pm)
1830 PMCDBG(MDP,REL,1, "iap-release cpu=%d ri=%d pm=%p", cpu, ri,
1833 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
1834 ("[core,%d] illegal CPU value %d", __LINE__, cpu));
1835 KASSERT(ri >= 0 && ri < core_iap_npmc,
1836 ("[core,%d] illegal row-index %d", __LINE__, ri));
1838 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc
1839 == NULL, ("[core,%d] PHW pmc non-NULL", __LINE__));
1845 iap_start_pmc(int cpu, int ri)
1849 struct core_cpu *cc;
1851 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
1852 ("[core,%d] illegal CPU value %d", __LINE__, cpu));
1853 KASSERT(ri >= 0 && ri < core_iap_npmc,
1854 ("[core,%d] illegal row-index %d", __LINE__, ri));
1856 cc = core_pcpu[cpu];
1857 pm = cc->pc_corepmcs[ri].phw_pmc;
1860 ("[core,%d] starting cpu%d,ri%d with no pmc configured",
1861 __LINE__, cpu, ri));
1863 PMCDBG(MDP,STA,1, "iap-start cpu=%d ri=%d", cpu, ri);
1865 evsel = pm->pm_md.pm_iap.pm_iap_evsel;
1867 PMCDBG(MDP,STA,2, "iap-start/2 cpu=%d ri=%d evselmsr=0x%x evsel=0x%x",
1868 cpu, ri, IAP_EVSEL0 + ri, evsel);
1870 /* Event specific configuration. */
1871 switch (pm->pm_event) {
1872 case PMC_EV_IAP_EVENT_B7H_01H:
1873 wrmsr(IA_OFFCORE_RSP0, pm->pm_md.pm_iap.pm_iap_rsp);
1875 case PMC_EV_IAP_EVENT_BBH_01H:
1876 wrmsr(IA_OFFCORE_RSP1, pm->pm_md.pm_iap.pm_iap_rsp);
1882 wrmsr(IAP_EVSEL0 + ri, evsel | IAP_EN);
1884 if (core_cputype == PMC_CPU_INTEL_CORE)
1889 cc->pc_globalctrl |= (1ULL << ri);
1890 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl);
1891 } while (cc->pc_resync != 0);
1897 iap_stop_pmc(int cpu, int ri)
1900 struct core_cpu *cc;
1903 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
1904 ("[core,%d] illegal cpu value %d", __LINE__, cpu));
1905 KASSERT(ri >= 0 && ri < core_iap_npmc,
1906 ("[core,%d] illegal row index %d", __LINE__, ri));
1908 cc = core_pcpu[cpu];
1909 pm = cc->pc_corepmcs[ri].phw_pmc;
1912 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__,
1915 PMCDBG(MDP,STO,1, "iap-stop cpu=%d ri=%d", cpu, ri);
1917 msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK;
1918 wrmsr(IAP_EVSEL0 + ri, msr); /* stop hw */
1920 if (core_cputype == PMC_CPU_INTEL_CORE)
1926 cc->pc_globalctrl &= ~(1ULL << ri);
1927 msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK;
1928 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl);
1929 } while (cc->pc_resync != 0);
1935 iap_write_pmc(int cpu, int ri, pmc_value_t v)
1938 struct core_cpu *cc;
1940 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
1941 ("[core,%d] illegal cpu value %d", __LINE__, cpu));
1942 KASSERT(ri >= 0 && ri < core_iap_npmc,
1943 ("[core,%d] illegal row index %d", __LINE__, ri));
1945 cc = core_pcpu[cpu];
1946 pm = cc->pc_corepmcs[ri].phw_pmc;
1949 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__,
1952 PMCDBG(MDP,WRI,1, "iap-write cpu=%d ri=%d msr=0x%x v=%jx", cpu, ri,
1955 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
1956 v = iap_reload_count_to_perfctr_value(v);
1959 * Write the new value to the counter. The counter will be in
1960 * a stopped state when the pcd_write() entry point is called.
1963 wrmsr(IAP_PMC0 + ri, v & ((1ULL << core_iap_width) - 1));
1970 iap_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth,
1973 struct pmc_classdep *pcd;
1975 KASSERT(md != NULL, ("[iap,%d] md is NULL", __LINE__));
1977 PMCDBG(MDP,INI,1, "%s", "iap-initialize");
1979 /* Remember the set of architectural events supported. */
1980 core_architectural_events = ~flags;
1982 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP];
1984 pcd->pcd_caps = IAP_PMC_CAPS;
1985 pcd->pcd_class = PMC_CLASS_IAP;
1986 pcd->pcd_num = npmc;
1987 pcd->pcd_ri = md->pmd_npmc;
1988 pcd->pcd_width = pmcwidth;
1990 pcd->pcd_allocate_pmc = iap_allocate_pmc;
1991 pcd->pcd_config_pmc = iap_config_pmc;
1992 pcd->pcd_describe = iap_describe;
1993 pcd->pcd_get_config = iap_get_config;
1994 pcd->pcd_get_msr = iap_get_msr;
1995 pcd->pcd_pcpu_fini = core_pcpu_fini;
1996 pcd->pcd_pcpu_init = core_pcpu_init;
1997 pcd->pcd_read_pmc = iap_read_pmc;
1998 pcd->pcd_release_pmc = iap_release_pmc;
1999 pcd->pcd_start_pmc = iap_start_pmc;
2000 pcd->pcd_stop_pmc = iap_stop_pmc;
2001 pcd->pcd_write_pmc = iap_write_pmc;
2003 md->pmd_npmc += npmc;
2007 core_intr(int cpu, struct trapframe *tf)
2011 struct core_cpu *cc;
2012 int error, found_interrupt, ri;
2015 PMCDBG(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf,
2016 TRAPF_USERMODE(tf));
2018 found_interrupt = 0;
2019 cc = core_pcpu[cpu];
2021 for (ri = 0; ri < core_iap_npmc; ri++) {
2023 if ((pm = cc->pc_corepmcs[ri].phw_pmc) == NULL ||
2024 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
2027 if (!iap_pmc_has_overflowed(ri))
2030 found_interrupt = 1;
2032 if (pm->pm_state != PMC_STATE_RUNNING)
2035 error = pmc_process_interrupt(cpu, pm, tf,
2036 TRAPF_USERMODE(tf));
2038 v = pm->pm_sc.pm_reloadcount;
2039 v = iaf_reload_count_to_perfctr_value(v);
2042 * Stop the counter, reload it but only restart it if
2043 * the PMC is not stalled.
2045 msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK;
2046 wrmsr(IAP_EVSEL0 + ri, msr);
2047 wrmsr(IAP_PMC0 + ri, v);
2052 wrmsr(IAP_EVSEL0 + ri, msr | (pm->pm_md.pm_iap.pm_iap_evsel |
2056 if (found_interrupt)
2057 lapic_reenable_pmc();
2059 atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed :
2060 &pmc_stats.pm_intr_ignored, 1);
2062 return (found_interrupt);
2066 core2_intr(int cpu, struct trapframe *tf)
2068 int error, found_interrupt, n;
2069 uint64_t flag, intrstatus, intrenable, msr;
2071 struct core_cpu *cc;
2074 PMCDBG(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf,
2075 TRAPF_USERMODE(tf));
2078 * The IA_GLOBAL_STATUS (MSR 0x38E) register indicates which
2079 * PMCs have a pending PMI interrupt. We take a 'snapshot' of
2080 * the current set of interrupting PMCs and process these
2081 * after stopping them.
2083 intrstatus = rdmsr(IA_GLOBAL_STATUS);
2084 intrenable = intrstatus & core_pmcmask;
2086 PMCDBG(MDP,INT, 1, "cpu=%d intrstatus=%jx", cpu,
2087 (uintmax_t) intrstatus);
2089 found_interrupt = 0;
2090 cc = core_pcpu[cpu];
2092 KASSERT(cc != NULL, ("[core,%d] null pcpu", __LINE__));
2094 cc->pc_globalctrl &= ~intrenable;
2095 cc->pc_resync = 1; /* MSRs now potentially out of sync. */
2098 * Stop PMCs and clear overflow status bits.
2100 msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK;
2101 wrmsr(IA_GLOBAL_CTRL, msr);
2102 wrmsr(IA_GLOBAL_OVF_CTRL, intrenable |
2103 IA_GLOBAL_STATUS_FLAG_OVFBUF |
2104 IA_GLOBAL_STATUS_FLAG_CONDCHG);
2107 * Look for interrupts from fixed function PMCs.
2109 for (n = 0, flag = (1ULL << IAF_OFFSET); n < core_iaf_npmc;
2112 if ((intrstatus & flag) == 0)
2115 found_interrupt = 1;
2117 pm = cc->pc_corepmcs[n + core_iaf_ri].phw_pmc;
2118 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING ||
2119 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
2122 error = pmc_process_interrupt(cpu, pm, tf,
2123 TRAPF_USERMODE(tf));
2125 intrenable &= ~flag;
2127 v = iaf_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount);
2129 /* Reload sampling count. */
2130 wrmsr(IAF_CTR0 + n, v);
2132 PMCDBG(MDP,INT, 1, "iaf-intr cpu=%d error=%d v=%jx(%jx)", cpu, error,
2133 (uintmax_t) v, (uintmax_t) rdpmc(IAF_RI_TO_MSR(n)));
2137 * Process interrupts from the programmable counters.
2139 for (n = 0, flag = 1; n < core_iap_npmc; n++, flag <<= 1) {
2140 if ((intrstatus & flag) == 0)
2143 found_interrupt = 1;
2145 pm = cc->pc_corepmcs[n].phw_pmc;
2146 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING ||
2147 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
2150 error = pmc_process_interrupt(cpu, pm, tf,
2151 TRAPF_USERMODE(tf));
2153 intrenable &= ~flag;
2155 v = iap_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount);
2157 PMCDBG(MDP,INT, 1, "iap-intr cpu=%d error=%d v=%jx", cpu, error,
2160 /* Reload sampling count. */
2161 wrmsr(IAP_PMC0 + n, v);
2165 * Reenable all non-stalled PMCs.
2167 PMCDBG(MDP,INT, 1, "cpu=%d intrenable=%jx", cpu,
2168 (uintmax_t) intrenable);
2170 cc->pc_globalctrl |= intrenable;
2172 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl & IA_GLOBAL_CTRL_MASK);
2174 PMCDBG(MDP,INT, 1, "cpu=%d fixedctrl=%jx globalctrl=%jx status=%jx "
2175 "ovf=%jx", cpu, (uintmax_t) rdmsr(IAF_CTRL),
2176 (uintmax_t) rdmsr(IA_GLOBAL_CTRL),
2177 (uintmax_t) rdmsr(IA_GLOBAL_STATUS),
2178 (uintmax_t) rdmsr(IA_GLOBAL_OVF_CTRL));
2180 if (found_interrupt)
2181 lapic_reenable_pmc();
2183 atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed :
2184 &pmc_stats.pm_intr_ignored, 1);
2186 return (found_interrupt);
2190 pmc_core_initialize(struct pmc_mdep *md, int maxcpu)
2192 int cpuid[CORE_CPUID_REQUEST_SIZE];
2193 int ipa_version, flags, nflags;
2195 do_cpuid(CORE_CPUID_REQUEST, cpuid);
2197 ipa_version = cpuid[CORE_CPUID_EAX] & 0xFF;
2199 PMCDBG(MDP,INI,1,"core-init cputype=%d ncpu=%d ipa-version=%d",
2200 md->pmd_cputype, maxcpu, ipa_version);
2202 if (ipa_version < 1 || ipa_version > 3) /* Unknown PMC architecture. */
2203 return (EPROGMISMATCH);
2205 core_cputype = md->pmd_cputype;
2210 * Initialize programmable counters.
2212 KASSERT(ipa_version >= 1,
2213 ("[core,%d] ipa_version %d too small", __LINE__, ipa_version));
2215 core_iap_npmc = (cpuid[CORE_CPUID_EAX] >> 8) & 0xFF;
2216 core_iap_width = (cpuid[CORE_CPUID_EAX] >> 16) & 0xFF;
2218 core_pmcmask |= ((1ULL << core_iap_npmc) - 1);
2220 nflags = (cpuid[CORE_CPUID_EAX] >> 24) & 0xFF;
2221 flags = cpuid[CORE_CPUID_EBX] & ((1 << nflags) - 1);
2223 iap_initialize(md, maxcpu, core_iap_npmc, core_iap_width, flags);
2226 * Initialize fixed function counters, if present.
2228 if (core_cputype != PMC_CPU_INTEL_CORE) {
2229 KASSERT(ipa_version >= 2,
2230 ("[core,%d] ipa_version %d too small", __LINE__,
2233 core_iaf_ri = core_iap_npmc;
2234 core_iaf_npmc = cpuid[CORE_CPUID_EDX] & 0x1F;
2235 core_iaf_width = (cpuid[CORE_CPUID_EDX] >> 5) & 0xFF;
2237 iaf_initialize(md, maxcpu, core_iaf_npmc, core_iaf_width);
2238 core_pmcmask |= ((1ULL << core_iaf_npmc) - 1) << IAF_OFFSET;
2241 PMCDBG(MDP,INI,1,"core-init pmcmask=0x%jx iafri=%d", core_pmcmask,
2244 core_pcpu = malloc(sizeof(struct core_cpu **) * maxcpu, M_PMC,
2248 * Choose the appropriate interrupt handler.
2250 if (ipa_version == 1)
2251 md->pmd_intr = core_intr;
2253 md->pmd_intr = core2_intr;
2255 md->pmd_pcpu_fini = NULL;
2256 md->pmd_pcpu_init = NULL;
2262 pmc_core_finalize(struct pmc_mdep *md)
2264 PMCDBG(MDP,INI,1, "%s", "core-finalize");
2266 free(core_pcpu, M_PMC);