sys/dev/hwpmc/hwpmc_core.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 2008 Joseph Koshy
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  */
  28
  29 /*
  30  * Intel Core PMCs.
  31  */
  32
  33 #include <sys/cdefs.h>
  34 __FBSDID("$FreeBSD$");
  35
  36 #include <sys/param.h>
  37 #include <sys/bus.h>
  38 #include <sys/pmc.h>
  39 #include <sys/pmckern.h>
  40 #include <sys/systm.h>
  41
  42 #include <machine/intr_machdep.h>
  43 #if (__FreeBSD_version >= 1100000)
  44 #include <x86/apicvar.h>
  45 #else
  46 #include <machine/apicvar.h>
  47 #endif
  48 #include <machine/cpu.h>
  49 #include <machine/cpufunc.h>
  50 #include <machine/md_var.h>
  51 #include <machine/specialreg.h>
  52
  53 #define CORE_CPUID_REQUEST              0xA
  54 #define CORE_CPUID_REQUEST_SIZE         0x4
  55 #define CORE_CPUID_EAX                  0x0
  56 #define CORE_CPUID_EBX                  0x1
  57 #define CORE_CPUID_ECX                  0x2
  58 #define CORE_CPUID_EDX                  0x3
  59
  60 #define IAF_PMC_CAPS                    \
  61         (PMC_CAP_READ | PMC_CAP_WRITE | PMC_CAP_INTERRUPT | \
  62          PMC_CAP_USER | PMC_CAP_SYSTEM)
  63 #define IAF_RI_TO_MSR(RI)               ((RI) + (1 << 30))
  64
  65 #define IAP_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | PMC_CAP_SYSTEM | \
  66     PMC_CAP_EDGE | PMC_CAP_THRESHOLD | PMC_CAP_READ | PMC_CAP_WRITE |    \
  67     PMC_CAP_INVERT | PMC_CAP_QUALIFIER | PMC_CAP_PRECISE)
  68
  69 #define EV_IS_NOTARCH           0
  70 #define EV_IS_ARCH_SUPP         1
  71 #define EV_IS_ARCH_NOTSUPP      -1
  72
  73 /*
  74  * "Architectural" events defined by Intel.  The values of these
  75  * symbols correspond to positions in the bitmask returned by
  76  * the CPUID.0AH instruction.
  77  */
  78 enum core_arch_events {
  79         CORE_AE_BRANCH_INSTRUCTION_RETIRED      = 5,
  80         CORE_AE_BRANCH_MISSES_RETIRED           = 6,
  81         CORE_AE_INSTRUCTION_RETIRED             = 1,
  82         CORE_AE_LLC_MISSES                      = 4,
  83         CORE_AE_LLC_REFERENCE                   = 3,
  84         CORE_AE_UNHALTED_REFERENCE_CYCLES       = 2,
  85         CORE_AE_UNHALTED_CORE_CYCLES            = 0
  86 };
  87
  88 static enum pmc_cputype core_cputype;
  89
  90 struct core_cpu {
  91         volatile uint32_t       pc_resync;
  92         volatile uint32_t       pc_iafctrl;     /* Fixed function control. */
  93         volatile uint64_t       pc_globalctrl;  /* Global control register. */
  94         struct pmc_hw           pc_corepmcs[];
  95 };
  96
  97 static struct core_cpu **core_pcpu;
  98
  99 static uint32_t core_architectural_events;
 100 static uint64_t core_pmcmask;
 101
 102 static int core_iaf_ri;         /* relative index of fixed counters */
 103 static int core_iaf_width;
 104 static int core_iaf_npmc;
 105
 106 static int core_iap_width;
 107 static int core_iap_npmc;
 108 static int core_iap_wroffset;
 109
 110 static int
 111 core_pcpu_noop(struct pmc_mdep *md, int cpu)
 112 {
 113         (void) md;
 114         (void) cpu;
 115         return (0);
 116 }
 117
 118 static int
 119 core_pcpu_init(struct pmc_mdep *md, int cpu)
 120 {
 121         struct pmc_cpu *pc;
 122         struct core_cpu *cc;
 123         struct pmc_hw *phw;
 124         int core_ri, n, npmc;
 125
 126         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 127             ("[iaf,%d] insane cpu number %d", __LINE__, cpu));
 128
 129         PMCDBG1(MDP,INI,1,"core-init cpu=%d", cpu);
 130
 131         core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri;
 132         npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num;
 133
 134         if (core_cputype != PMC_CPU_INTEL_CORE)
 135                 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num;
 136
 137         cc = malloc(sizeof(struct core_cpu) + npmc * sizeof(struct pmc_hw),
 138             M_PMC, M_WAITOK | M_ZERO);
 139
 140         core_pcpu[cpu] = cc;
 141         pc = pmc_pcpu[cpu];
 142
 143         KASSERT(pc != NULL && cc != NULL,
 144             ("[core,%d] NULL per-cpu structures cpu=%d", __LINE__, cpu));
 145
 146         for (n = 0, phw = cc->pc_corepmcs; n < npmc; n++, phw++) {
 147                 phw->phw_state    = PMC_PHW_FLAG_IS_ENABLED |
 148                     PMC_PHW_CPU_TO_STATE(cpu) |
 149                     PMC_PHW_INDEX_TO_STATE(n + core_ri);
 150                 phw->phw_pmc      = NULL;
 151                 pc->pc_hwpmcs[n + core_ri]  = phw;
 152         }
 153
 154         return (0);
 155 }
 156
 157 static int
 158 core_pcpu_fini(struct pmc_mdep *md, int cpu)
 159 {
 160         int core_ri, n, npmc;
 161         struct pmc_cpu *pc;
 162         struct core_cpu *cc;
 163         uint64_t msr = 0;
 164
 165         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 166             ("[core,%d] insane cpu number (%d)", __LINE__, cpu));
 167
 168         PMCDBG1(MDP,INI,1,"core-pcpu-fini cpu=%d", cpu);
 169
 170         if ((cc = core_pcpu[cpu]) == NULL)
 171                 return (0);
 172
 173         core_pcpu[cpu] = NULL;
 174
 175         pc = pmc_pcpu[cpu];
 176
 177         KASSERT(pc != NULL, ("[core,%d] NULL per-cpu %d state", __LINE__,
 178                 cpu));
 179
 180         npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num;
 181         core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri;
 182
 183         for (n = 0; n < npmc; n++) {
 184                 msr = rdmsr(IAP_EVSEL0 + n) & ~IAP_EVSEL_MASK;
 185                 wrmsr(IAP_EVSEL0 + n, msr);
 186         }
 187
 188         if (core_cputype != PMC_CPU_INTEL_CORE) {
 189                 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK;
 190                 wrmsr(IAF_CTRL, msr);
 191                 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num;
 192         }
 193
 194         for (n = 0; n < npmc; n++)
 195                 pc->pc_hwpmcs[n + core_ri] = NULL;
 196
 197         free(cc, M_PMC);
 198
 199         return (0);
 200 }
 201
 202 /*
 203  * Fixed function counters.
 204  */
 205
 206 static pmc_value_t
 207 iaf_perfctr_value_to_reload_count(pmc_value_t v)
 208 {
 209
 210         /* If the PMC has overflowed, return a reload count of zero. */
 211         if ((v & (1ULL << (core_iaf_width - 1))) == 0)
 212                 return (0);
 213         v &= (1ULL << core_iaf_width) - 1;
 214         return (1ULL << core_iaf_width) - v;
 215 }
 216
 217 static pmc_value_t
 218 iaf_reload_count_to_perfctr_value(pmc_value_t rlc)
 219 {
 220         return (1ULL << core_iaf_width) - rlc;
 221 }
 222
 223 static int
 224 iaf_allocate_pmc(int cpu, int ri, struct pmc *pm,
 225     const struct pmc_op_pmcallocate *a)
 226 {
 227         enum pmc_event ev;
 228         uint32_t caps, flags, validflags;
 229
 230         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 231             ("[core,%d] illegal CPU %d", __LINE__, cpu));
 232
 233         PMCDBG2(MDP,ALL,1, "iaf-allocate ri=%d reqcaps=0x%x", ri, pm->pm_caps);
 234
 235         if (ri < 0 || ri > core_iaf_npmc)
 236                 return (EINVAL);
 237
 238         caps = a->pm_caps;
 239
 240         if (a->pm_class != PMC_CLASS_IAF ||
 241             (caps & IAF_PMC_CAPS) != caps)
 242                 return (EINVAL);
 243
 244         ev = pm->pm_event;
 245
 246
 247         if (ev == PMC_EV_IAF_INSTR_RETIRED_ANY && ri != 0)
 248                 return (EINVAL);
 249         if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_CORE && ri != 1)
 250                 return (EINVAL);
 251         if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_REF && ri != 2)
 252                 return (EINVAL);
 253
 254         flags = a->pm_md.pm_iaf.pm_iaf_flags;
 255
 256         validflags = IAF_MASK;
 257
 258         if (caps & PMC_CAP_INTERRUPT)
 259                 flags |= IAF_PMI;
 260         if (caps & PMC_CAP_SYSTEM)
 261                 flags |= IAF_OS;
 262         if (caps & PMC_CAP_USER)
 263                 flags |= IAF_USR;
 264         if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0)
 265                 flags |= (IAF_OS | IAF_USR);
 266
 267         pm->pm_md.pm_iaf.pm_iaf_ctrl = (flags << (ri * 4));
 268
 269         PMCDBG1(MDP,ALL,2, "iaf-allocate config=0x%jx",
 270             (uintmax_t) pm->pm_md.pm_iaf.pm_iaf_ctrl);
 271
 272         return (0);
 273 }
 274
 275 static int
 276 iaf_config_pmc(int cpu, int ri, struct pmc *pm)
 277 {
 278         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 279             ("[core,%d] illegal CPU %d", __LINE__, cpu));
 280
 281         KASSERT(ri >= 0 && ri < core_iaf_npmc,
 282             ("[core,%d] illegal row-index %d", __LINE__, ri));
 283
 284         PMCDBG3(MDP,CFG,1, "iaf-config cpu=%d ri=%d pm=%p", cpu, ri, pm);
 285
 286         KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__,
 287             cpu));
 288
 289         core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc = pm;
 290
 291         return (0);
 292 }
 293
 294 static int
 295 iaf_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
 296 {
 297         int error;
 298         struct pmc_hw *phw;
 299         char iaf_name[PMC_NAME_MAX];
 300
 301         phw = &core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri];
 302
 303         (void) snprintf(iaf_name, sizeof(iaf_name), "IAF-%d", ri);
 304         if ((error = copystr(iaf_name, pi->pm_name, PMC_NAME_MAX,
 305             NULL)) != 0)
 306                 return (error);
 307
 308         pi->pm_class = PMC_CLASS_IAF;
 309
 310         if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
 311                 pi->pm_enabled = TRUE;
 312                 *ppmc          = phw->phw_pmc;
 313         } else {
 314                 pi->pm_enabled = FALSE;
 315                 *ppmc          = NULL;
 316         }
 317
 318         return (0);
 319 }
 320
 321 static int
 322 iaf_get_config(int cpu, int ri, struct pmc **ppm)
 323 {
 324         *ppm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc;
 325
 326         return (0);
 327 }
 328
 329 static int
 330 iaf_get_msr(int ri, uint32_t *msr)
 331 {
 332         KASSERT(ri >= 0 && ri < core_iaf_npmc,
 333             ("[iaf,%d] ri %d out of range", __LINE__, ri));
 334
 335         *msr = IAF_RI_TO_MSR(ri);
 336
 337         return (0);
 338 }
 339
 340 static int
 341 iaf_read_pmc(int cpu, int ri, pmc_value_t *v)
 342 {
 343         struct pmc *pm;
 344         pmc_value_t tmp;
 345
 346         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 347             ("[core,%d] illegal cpu value %d", __LINE__, cpu));
 348         KASSERT(ri >= 0 && ri < core_iaf_npmc,
 349             ("[core,%d] illegal row-index %d", __LINE__, ri));
 350
 351         pm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc;
 352
 353         KASSERT(pm,
 354             ("[core,%d] cpu %d ri %d(%d) pmc not configured", __LINE__, cpu,
 355                 ri, ri + core_iaf_ri));
 356
 357         tmp = rdpmc(IAF_RI_TO_MSR(ri));
 358
 359         if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
 360                 *v = iaf_perfctr_value_to_reload_count(tmp);
 361         else
 362                 *v = tmp & ((1ULL << core_iaf_width) - 1);
 363
 364         PMCDBG4(MDP,REA,1, "iaf-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri,
 365             IAF_RI_TO_MSR(ri), *v);
 366
 367         return (0);
 368 }
 369
 370 static int
 371 iaf_release_pmc(int cpu, int ri, struct pmc *pmc)
 372 {
 373         PMCDBG3(MDP,REL,1, "iaf-release cpu=%d ri=%d pm=%p", cpu, ri, pmc);
 374
 375         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 376             ("[core,%d] illegal CPU value %d", __LINE__, cpu));
 377         KASSERT(ri >= 0 && ri < core_iaf_npmc,
 378             ("[core,%d] illegal row-index %d", __LINE__, ri));
 379
 380         KASSERT(core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc == NULL,
 381             ("[core,%d] PHW pmc non-NULL", __LINE__));
 382
 383         return (0);
 384 }
 385
 386 static int
 387 iaf_start_pmc(int cpu, int ri)
 388 {
 389         struct pmc *pm;
 390         struct core_cpu *iafc;
 391         uint64_t msr = 0;
 392
 393         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 394             ("[core,%d] illegal CPU value %d", __LINE__, cpu));
 395         KASSERT(ri >= 0 && ri < core_iaf_npmc,
 396             ("[core,%d] illegal row-index %d", __LINE__, ri));
 397
 398         PMCDBG2(MDP,STA,1,"iaf-start cpu=%d ri=%d", cpu, ri);
 399
 400         iafc = core_pcpu[cpu];
 401         pm = iafc->pc_corepmcs[ri + core_iaf_ri].phw_pmc;
 402
 403         iafc->pc_iafctrl |= pm->pm_md.pm_iaf.pm_iaf_ctrl;
 404
 405         msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK;
 406         wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK));
 407
 408         do {
 409                 iafc->pc_resync = 0;
 410                 iafc->pc_globalctrl |= (1ULL << (ri + IAF_OFFSET));
 411                 msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK;
 412                 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl &
 413                                              IAF_GLOBAL_CTRL_MASK));
 414         } while (iafc->pc_resync != 0);
 415
 416         PMCDBG4(MDP,STA,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)",
 417             iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL),
 418             iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL));
 419
 420         return (0);
 421 }
 422
 423 static int
 424 iaf_stop_pmc(int cpu, int ri)
 425 {
 426         uint32_t fc;
 427         struct core_cpu *iafc;
 428         uint64_t msr = 0;
 429
 430         PMCDBG2(MDP,STO,1,"iaf-stop cpu=%d ri=%d", cpu, ri);
 431
 432         iafc = core_pcpu[cpu];
 433
 434         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 435             ("[core,%d] illegal CPU value %d", __LINE__, cpu));
 436         KASSERT(ri >= 0 && ri < core_iaf_npmc,
 437             ("[core,%d] illegal row-index %d", __LINE__, ri));
 438
 439         fc = (IAF_MASK << (ri * 4));
 440
 441         iafc->pc_iafctrl &= ~fc;
 442
 443         PMCDBG1(MDP,STO,1,"iaf-stop iafctrl=%x", iafc->pc_iafctrl);
 444         msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK;
 445         wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK));
 446
 447         do {
 448                 iafc->pc_resync = 0;
 449                 iafc->pc_globalctrl &= ~(1ULL << (ri + IAF_OFFSET));
 450                 msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK;
 451                 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl &
 452                                              IAF_GLOBAL_CTRL_MASK));
 453         } while (iafc->pc_resync != 0);
 454
 455         PMCDBG4(MDP,STO,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)",
 456             iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL),
 457             iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL));
 458
 459         return (0);
 460 }
 461
 462 static int
 463 iaf_write_pmc(int cpu, int ri, pmc_value_t v)
 464 {
 465         struct core_cpu *cc;
 466         struct pmc *pm;
 467         uint64_t msr;
 468
 469         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 470             ("[core,%d] illegal cpu value %d", __LINE__, cpu));
 471         KASSERT(ri >= 0 && ri < core_iaf_npmc,
 472             ("[core,%d] illegal row-index %d", __LINE__, ri));
 473
 474         cc = core_pcpu[cpu];
 475         pm = cc->pc_corepmcs[ri + core_iaf_ri].phw_pmc;
 476
 477         KASSERT(pm,
 478             ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, ri));
 479
 480         if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
 481                 v = iaf_reload_count_to_perfctr_value(v);
 482
 483         /* Turn off fixed counters */
 484         msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK;
 485         wrmsr(IAF_CTRL, msr);
 486
 487         wrmsr(IAF_CTR0 + ri, v & ((1ULL << core_iaf_width) - 1));
 488
 489         /* Turn on fixed counters */
 490         msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK;
 491         wrmsr(IAF_CTRL, msr | (cc->pc_iafctrl & IAF_CTRL_MASK));
 492
 493         PMCDBG6(MDP,WRI,1, "iaf-write cpu=%d ri=%d msr=0x%x v=%jx iafctrl=%jx "
 494             "pmc=%jx", cpu, ri, IAF_RI_TO_MSR(ri), v,
 495             (uintmax_t) rdmsr(IAF_CTRL),
 496             (uintmax_t) rdpmc(IAF_RI_TO_MSR(ri)));
 497
 498         return (0);
 499 }
 500
 501
 502 static void
 503 iaf_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth)
 504 {
 505         struct pmc_classdep *pcd;
 506
 507         KASSERT(md != NULL, ("[iaf,%d] md is NULL", __LINE__));
 508
 509         PMCDBG0(MDP,INI,1, "iaf-initialize");
 510
 511         pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF];
 512
 513         pcd->pcd_caps   = IAF_PMC_CAPS;
 514         pcd->pcd_class  = PMC_CLASS_IAF;
 515         pcd->pcd_num    = npmc;
 516         pcd->pcd_ri     = md->pmd_npmc;
 517         pcd->pcd_width  = pmcwidth;
 518
 519         pcd->pcd_allocate_pmc   = iaf_allocate_pmc;
 520         pcd->pcd_config_pmc     = iaf_config_pmc;
 521         pcd->pcd_describe       = iaf_describe;
 522         pcd->pcd_get_config     = iaf_get_config;
 523         pcd->pcd_get_msr        = iaf_get_msr;
 524         pcd->pcd_pcpu_fini      = core_pcpu_noop;
 525         pcd->pcd_pcpu_init      = core_pcpu_noop;
 526         pcd->pcd_read_pmc       = iaf_read_pmc;
 527         pcd->pcd_release_pmc    = iaf_release_pmc;
 528         pcd->pcd_start_pmc      = iaf_start_pmc;
 529         pcd->pcd_stop_pmc       = iaf_stop_pmc;
 530         pcd->pcd_write_pmc      = iaf_write_pmc;
 531
 532         md->pmd_npmc           += npmc;
 533 }
 534
 535 /*
 536  * Intel programmable PMCs.
 537  */
 538
 539 /* Sub fields of UMASK that this event supports. */
 540 #define IAP_M_CORE              (1 << 0) /* Core specificity */
 541 #define IAP_M_AGENT             (1 << 1) /* Agent specificity */
 542 #define IAP_M_PREFETCH          (1 << 2) /* Prefetch */
 543 #define IAP_M_MESI              (1 << 3) /* MESI */
 544 #define IAP_M_SNOOPRESPONSE     (1 << 4) /* Snoop response */
 545 #define IAP_M_SNOOPTYPE         (1 << 5) /* Snoop type */
 546 #define IAP_M_TRANSITION        (1 << 6) /* Transition */
 547
 548 #define IAP_F_CORE              (0x3 << 14) /* Core specificity */
 549 #define IAP_F_AGENT             (0x1 << 13) /* Agent specificity */
 550 #define IAP_F_PREFETCH          (0x3 << 12) /* Prefetch */
 551 #define IAP_F_MESI              (0xF <<  8) /* MESI */
 552 #define IAP_F_SNOOPRESPONSE     (0xB <<  8) /* Snoop response */
 553 #define IAP_F_SNOOPTYPE         (0x3 <<  8) /* Snoop type */
 554 #define IAP_F_TRANSITION        (0x1 << 12) /* Transition */
 555
 556 #define IAP_PREFETCH_RESERVED   (0x2 << 12)
 557 #define IAP_CORE_THIS           (0x1 << 14)
 558 #define IAP_CORE_ALL            (0x3 << 14)
 559 #define IAP_F_CMASK             0xFF000000
 560
 561 static pmc_value_t
 562 iap_perfctr_value_to_reload_count(pmc_value_t v)
 563 {
 564
 565         /* If the PMC has overflowed, return a reload count of zero. */
 566         if ((v & (1ULL << (core_iap_width - 1))) == 0)
 567                 return (0);
 568         v &= (1ULL << core_iap_width) - 1;
 569         return (1ULL << core_iap_width) - v;
 570 }
 571
 572 static pmc_value_t
 573 iap_reload_count_to_perfctr_value(pmc_value_t rlc)
 574 {
 575         return (1ULL << core_iap_width) - rlc;
 576 }
 577
 578 static int
 579 iap_pmc_has_overflowed(int ri)
 580 {
 581         uint64_t v;
 582
 583         /*
 584          * We treat a Core (i.e., Intel architecture v1) PMC as has
 585          * having overflowed if its MSB is zero.
 586          */
 587         v = rdpmc(ri);
 588         return ((v & (1ULL << (core_iap_width - 1))) == 0);
 589 }
 590
 591 static int
 592 iap_event_corei7_ok_on_counter(uint8_t evsel, int ri)
 593 {
 594         uint32_t mask;
 595
 596         switch (evsel) {
 597                 /*
 598                  * Events valid only on counter 0, 1.
 599                  */
 600                 case 0x40:
 601                 case 0x41:
 602                 case 0x42:
 603                 case 0x43:
 604                 case 0x51:
 605                 case 0x63:
 606                         mask = 0x3;
 607                 break;
 608
 609                 default:
 610                 mask = ~0;      /* Any row index is ok. */
 611         }
 612
 613         return (mask & (1 << ri));
 614 }
 615
 616 static int
 617 iap_event_westmere_ok_on_counter(uint8_t evsel, int ri)
 618 {
 619         uint32_t mask;
 620
 621         switch (evsel) {
 622                 /*
 623                  * Events valid only on counter 0.
 624                  */
 625                 case 0x60:
 626                 case 0xB3:
 627                 mask = 0x1;
 628                 break;
 629
 630                 /*
 631                  * Events valid only on counter 0, 1.
 632                  */
 633                 case 0x4C:
 634                 case 0x4E:
 635                 case 0x51:
 636                 case 0x63:
 637                 mask = 0x3;
 638                 break;
 639
 640         default:
 641                 mask = ~0;      /* Any row index is ok. */
 642         }
 643
 644         return (mask & (1 << ri));
 645 }
 646
 647 static int
 648 iap_event_sb_sbx_ib_ibx_ok_on_counter(uint8_t evsel, int ri)
 649 {
 650         uint32_t mask;
 651
 652         switch (evsel) {
 653                 /* Events valid only on counter 0. */
 654     case 0xB7:
 655                 mask = 0x1;
 656                 break;
 657                 /* Events valid only on counter 1. */
 658         case 0xC0:
 659                 mask = 0x2;
 660                 break;
 661                 /* Events valid only on counter 2. */
 662         case 0x48:
 663         case 0xA2:
 664         case 0xA3:
 665                 mask = 0x4;
 666                 break;
 667                 /* Events valid only on counter 3. */
 668         case 0xBB:
 669         case 0xCD:
 670                 mask = 0x8;
 671                 break;
 672         default:
 673                 mask = ~0;      /* Any row index is ok. */
 674         }
 675
 676         return (mask & (1 << ri));
 677 }
 678
 679 static int
 680 iap_event_ok_on_counter(uint8_t evsel, int ri)
 681 {
 682         uint32_t mask;
 683
 684         switch (evsel) {
 685                 /*
 686                  * Events valid only on counter 0.
 687                  */
 688         case 0x10:
 689         case 0x14:
 690         case 0x18:
 691         case 0xB3:
 692         case 0xC1:
 693         case 0xCB:
 694                 mask = (1 << 0);
 695                 break;
 696
 697                 /*
 698                  * Events valid only on counter 1.
 699                  */
 700         case 0x11:
 701         case 0x12:
 702         case 0x13:
 703                 mask = (1 << 1);
 704                 break;
 705
 706         default:
 707                 mask = ~0;      /* Any row index is ok. */
 708         }
 709
 710         return (mask & (1 << ri));
 711 }
 712
 713 static int
 714 iap_allocate_pmc(int cpu, int ri, struct pmc *pm,
 715     const struct pmc_op_pmcallocate *a)
 716 {
 717         enum pmc_event map;
 718         uint8_t ev;
 719         uint32_t caps;
 720         const struct pmc_md_iap_op_pmcallocate *iap;
 721
 722         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 723             ("[core,%d] illegal CPU %d", __LINE__, cpu));
 724         KASSERT(ri >= 0 && ri < core_iap_npmc,
 725             ("[core,%d] illegal row-index value %d", __LINE__, ri));
 726
 727         /* check requested capabilities */
 728         caps = a->pm_caps;
 729         if ((IAP_PMC_CAPS & caps) != caps)
 730                 return (EPERM);
 731         map = 0;        /* XXX: silent GCC warning */
 732         iap = &a->pm_md.pm_iap;
 733         ev = IAP_EVSEL_GET(iap->pm_iap_config);
 734
 735         switch (core_cputype) {
 736         case PMC_CPU_INTEL_COREI7:
 737         case PMC_CPU_INTEL_NEHALEM_EX:
 738                 if (iap_event_corei7_ok_on_counter(ev, ri) == 0)
 739                         return (EINVAL);
 740                 break;
 741         case PMC_CPU_INTEL_SKYLAKE:
 742         case PMC_CPU_INTEL_SKYLAKE_XEON:
 743         case PMC_CPU_INTEL_BROADWELL:
 744         case PMC_CPU_INTEL_BROADWELL_XEON:
 745         case PMC_CPU_INTEL_SANDYBRIDGE:
 746         case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
 747         case PMC_CPU_INTEL_IVYBRIDGE:
 748         case PMC_CPU_INTEL_IVYBRIDGE_XEON:
 749         case PMC_CPU_INTEL_HASWELL:
 750         case PMC_CPU_INTEL_HASWELL_XEON:
 751                 if (iap_event_sb_sbx_ib_ibx_ok_on_counter(ev, ri) == 0)
 752                         return (EINVAL);
 753                 break;
 754         case PMC_CPU_INTEL_WESTMERE:
 755         case PMC_CPU_INTEL_WESTMERE_EX:
 756                 if (iap_event_westmere_ok_on_counter(ev, ri) == 0)
 757                         return (EINVAL);
 758                 break;
 759         default:
 760                 if (iap_event_ok_on_counter(ev, ri) == 0)
 761                         return (EINVAL);
 762         }
 763
 764         pm->pm_md.pm_iap.pm_iap_evsel = iap->pm_iap_config;
 765         return (0);
 766 }
 767
 768 static int
 769 iap_config_pmc(int cpu, int ri, struct pmc *pm)
 770 {
 771         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 772             ("[core,%d] illegal CPU %d", __LINE__, cpu));
 773
 774         KASSERT(ri >= 0 && ri < core_iap_npmc,
 775             ("[core,%d] illegal row-index %d", __LINE__, ri));
 776
 777         PMCDBG3(MDP,CFG,1, "iap-config cpu=%d ri=%d pm=%p", cpu, ri, pm);
 778
 779         KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__,
 780             cpu));
 781
 782         core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc = pm;
 783
 784         return (0);
 785 }
 786
 787 static int
 788 iap_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
 789 {
 790         int error;
 791         struct pmc_hw *phw;
 792         char iap_name[PMC_NAME_MAX];
 793
 794         phw = &core_pcpu[cpu]->pc_corepmcs[ri];
 795
 796         (void) snprintf(iap_name, sizeof(iap_name), "IAP-%d", ri);
 797         if ((error = copystr(iap_name, pi->pm_name, PMC_NAME_MAX,
 798             NULL)) != 0)
 799                 return (error);
 800
 801         pi->pm_class = PMC_CLASS_IAP;
 802
 803         if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
 804                 pi->pm_enabled = TRUE;
 805                 *ppmc          = phw->phw_pmc;
 806         } else {
 807                 pi->pm_enabled = FALSE;
 808                 *ppmc          = NULL;
 809         }
 810
 811         return (0);
 812 }
 813
 814 static int
 815 iap_get_config(int cpu, int ri, struct pmc **ppm)
 816 {
 817         *ppm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc;
 818
 819         return (0);
 820 }
 821
 822 static int
 823 iap_get_msr(int ri, uint32_t *msr)
 824 {
 825         KASSERT(ri >= 0 && ri < core_iap_npmc,
 826             ("[iap,%d] ri %d out of range", __LINE__, ri));
 827
 828         *msr = ri;
 829
 830         return (0);
 831 }
 832
 833 static int
 834 iap_read_pmc(int cpu, int ri, pmc_value_t *v)
 835 {
 836         struct pmc *pm;
 837         pmc_value_t tmp;
 838
 839         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 840             ("[core,%d] illegal cpu value %d", __LINE__, cpu));
 841         KASSERT(ri >= 0 && ri < core_iap_npmc,
 842             ("[core,%d] illegal row-index %d", __LINE__, ri));
 843
 844         pm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc;
 845
 846         KASSERT(pm,
 847             ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu,
 848                 ri));
 849
 850         tmp = rdpmc(ri);
 851         if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
 852                 *v = iap_perfctr_value_to_reload_count(tmp);
 853         else
 854                 *v = tmp & ((1ULL << core_iap_width) - 1);
 855
 856         PMCDBG4(MDP,REA,1, "iap-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri,
 857             IAP_PMC0 + ri, *v);
 858
 859         return (0);
 860 }
 861
 862 static int
 863 iap_release_pmc(int cpu, int ri, struct pmc *pm)
 864 {
 865         (void) pm;
 866
 867         PMCDBG3(MDP,REL,1, "iap-release cpu=%d ri=%d pm=%p", cpu, ri,
 868             pm);
 869
 870         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 871             ("[core,%d] illegal CPU value %d", __LINE__, cpu));
 872         KASSERT(ri >= 0 && ri < core_iap_npmc,
 873             ("[core,%d] illegal row-index %d", __LINE__, ri));
 874
 875         KASSERT(core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc
 876             == NULL, ("[core,%d] PHW pmc non-NULL", __LINE__));
 877
 878         return (0);
 879 }
 880
 881 static int
 882 iap_start_pmc(int cpu, int ri)
 883 {
 884         struct pmc *pm;
 885         uint32_t evsel;
 886         struct core_cpu *cc;
 887
 888         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 889             ("[core,%d] illegal CPU value %d", __LINE__, cpu));
 890         KASSERT(ri >= 0 && ri < core_iap_npmc,
 891             ("[core,%d] illegal row-index %d", __LINE__, ri));
 892
 893         cc = core_pcpu[cpu];
 894         pm = cc->pc_corepmcs[ri].phw_pmc;
 895
 896         KASSERT(pm,
 897             ("[core,%d] starting cpu%d,ri%d with no pmc configured",
 898                 __LINE__, cpu, ri));
 899
 900         PMCDBG2(MDP,STA,1, "iap-start cpu=%d ri=%d", cpu, ri);
 901
 902         evsel = pm->pm_md.pm_iap.pm_iap_evsel;
 903
 904         PMCDBG4(MDP,STA,2, "iap-start/2 cpu=%d ri=%d evselmsr=0x%x evsel=0x%x",
 905             cpu, ri, IAP_EVSEL0 + ri, evsel);
 906
 907         /* Event specific configuration. */
 908
 909         switch (IAP_EVSEL_GET(evsel)) {
 910         case 0xB7:
 911                 wrmsr(IA_OFFCORE_RSP0, pm->pm_md.pm_iap.pm_iap_rsp);
 912                 break;
 913         case 0xBB:
 914                 wrmsr(IA_OFFCORE_RSP1, pm->pm_md.pm_iap.pm_iap_rsp);
 915                 break;
 916         default:
 917                 break;
 918         }
 919
 920         wrmsr(IAP_EVSEL0 + ri, evsel | IAP_EN);
 921
 922         if (core_cputype == PMC_CPU_INTEL_CORE)
 923                 return (0);
 924
 925         do {
 926                 cc->pc_resync = 0;
 927                 cc->pc_globalctrl |= (1ULL << ri);
 928                 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl);
 929         } while (cc->pc_resync != 0);
 930
 931         return (0);
 932 }
 933
 934 static int
 935 iap_stop_pmc(int cpu, int ri)
 936 {
 937         struct pmc *pm;
 938         struct core_cpu *cc;
 939         uint64_t msr;
 940
 941         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 942             ("[core,%d] illegal cpu value %d", __LINE__, cpu));
 943         KASSERT(ri >= 0 && ri < core_iap_npmc,
 944             ("[core,%d] illegal row index %d", __LINE__, ri));
 945
 946         cc = core_pcpu[cpu];
 947         pm = cc->pc_corepmcs[ri].phw_pmc;
 948
 949         KASSERT(pm,
 950             ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__,
 951                 cpu, ri));
 952
 953         PMCDBG2(MDP,STO,1, "iap-stop cpu=%d ri=%d", cpu, ri);
 954
 955         msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK;
 956         wrmsr(IAP_EVSEL0 + ri, msr);    /* stop hw */
 957
 958         if (core_cputype == PMC_CPU_INTEL_CORE)
 959                 return (0);
 960
 961         msr = 0;
 962         do {
 963                 cc->pc_resync = 0;
 964                 cc->pc_globalctrl &= ~(1ULL << ri);
 965                 msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK;
 966                 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl);
 967         } while (cc->pc_resync != 0);
 968
 969         return (0);
 970 }
 971
 972 static int
 973 iap_write_pmc(int cpu, int ri, pmc_value_t v)
 974 {
 975         struct pmc *pm;
 976         struct core_cpu *cc;
 977
 978         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 979             ("[core,%d] illegal cpu value %d", __LINE__, cpu));
 980         KASSERT(ri >= 0 && ri < core_iap_npmc,
 981             ("[core,%d] illegal row index %d", __LINE__, ri));
 982
 983         cc = core_pcpu[cpu];
 984         pm = cc->pc_corepmcs[ri].phw_pmc;
 985
 986         KASSERT(pm,
 987             ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__,
 988                 cpu, ri));
 989
 990         if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
 991                 v = iap_reload_count_to_perfctr_value(v);
 992
 993         v &= (1ULL << core_iap_width) - 1;
 994
 995         PMCDBG4(MDP,WRI,1, "iap-write cpu=%d ri=%d msr=0x%x v=%jx", cpu, ri,
 996             IAP_PMC0 + ri, v);
 997
 998         /*
 999          * Write the new value to the counter (or it's alias).  The
1000          * counter will be in a stopped state when the pcd_write()
1001          * entry point is called.
1002          */
1003         wrmsr(core_iap_wroffset + IAP_PMC0 + ri, v);
1004         return (0);
1005 }
1006
1007
1008 static void
1009 iap_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth,
1010     int flags)
1011 {
1012         struct pmc_classdep *pcd;
1013
1014         KASSERT(md != NULL, ("[iap,%d] md is NULL", __LINE__));
1015
1016         PMCDBG0(MDP,INI,1, "iap-initialize");
1017
1018         /* Remember the set of architectural events supported. */
1019         core_architectural_events = ~flags;
1020
1021         pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP];
1022
1023         pcd->pcd_caps   = IAP_PMC_CAPS;
1024         pcd->pcd_class  = PMC_CLASS_IAP;
1025         pcd->pcd_num    = npmc;
1026         pcd->pcd_ri     = md->pmd_npmc;
1027         pcd->pcd_width  = pmcwidth;
1028
1029         pcd->pcd_allocate_pmc   = iap_allocate_pmc;
1030         pcd->pcd_config_pmc     = iap_config_pmc;
1031         pcd->pcd_describe       = iap_describe;
1032         pcd->pcd_get_config     = iap_get_config;
1033         pcd->pcd_get_msr        = iap_get_msr;
1034         pcd->pcd_pcpu_fini      = core_pcpu_fini;
1035         pcd->pcd_pcpu_init      = core_pcpu_init;
1036         pcd->pcd_read_pmc       = iap_read_pmc;
1037         pcd->pcd_release_pmc    = iap_release_pmc;
1038         pcd->pcd_start_pmc      = iap_start_pmc;
1039         pcd->pcd_stop_pmc       = iap_stop_pmc;
1040         pcd->pcd_write_pmc      = iap_write_pmc;
1041
1042         md->pmd_npmc           += npmc;
1043 }
1044
1045 static int
1046 core_intr(int cpu, struct trapframe *tf)
1047 {
1048         pmc_value_t v;
1049         struct pmc *pm;
1050         struct core_cpu *cc;
1051         int error, found_interrupt, ri;
1052         uint64_t msr;
1053
1054         PMCDBG3(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf,
1055             TRAPF_USERMODE(tf));
1056
1057         found_interrupt = 0;
1058         cc = core_pcpu[cpu];
1059
1060         for (ri = 0; ri < core_iap_npmc; ri++) {
1061
1062                 if ((pm = cc->pc_corepmcs[ri].phw_pmc) == NULL ||
1063                     !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
1064                         continue;
1065
1066                 if (!iap_pmc_has_overflowed(ri))
1067                         continue;
1068
1069                 found_interrupt = 1;
1070
1071                 if (pm->pm_state != PMC_STATE_RUNNING)
1072                         continue;
1073
1074                 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf,
1075                     TRAPF_USERMODE(tf));
1076
1077                 v = pm->pm_sc.pm_reloadcount;
1078                 v = iap_reload_count_to_perfctr_value(v);
1079
1080                 /*
1081                  * Stop the counter, reload it but only restart it if
1082                  * the PMC is not stalled.
1083                  */
1084                 msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK;
1085                 wrmsr(IAP_EVSEL0 + ri, msr);
1086                 wrmsr(core_iap_wroffset + IAP_PMC0 + ri, v);
1087
1088                 if (error)
1089                         continue;
1090
1091                 wrmsr(IAP_EVSEL0 + ri, msr | (pm->pm_md.pm_iap.pm_iap_evsel |
1092                                               IAP_EN));
1093         }
1094
1095         if (found_interrupt)
1096                 lapic_reenable_pmc();
1097
1098         if (found_interrupt)
1099                 counter_u64_add(pmc_stats.pm_intr_processed, 1);
1100         else
1101                 counter_u64_add(pmc_stats.pm_intr_ignored, 1);
1102
1103         return (found_interrupt);
1104 }
1105
1106 static int
1107 core2_intr(int cpu, struct trapframe *tf)
1108 {
1109         int error, found_interrupt, n;
1110         uint64_t flag, intrstatus, intrenable, msr;
1111         struct pmc *pm;
1112         struct core_cpu *cc;
1113         pmc_value_t v;
1114
1115         PMCDBG3(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf,
1116             TRAPF_USERMODE(tf));
1117
1118         /*
1119          * The IA_GLOBAL_STATUS (MSR 0x38E) register indicates which
1120          * PMCs have a pending PMI interrupt.  We take a 'snapshot' of
1121          * the current set of interrupting PMCs and process these
1122          * after stopping them.
1123          */
1124         intrstatus = rdmsr(IA_GLOBAL_STATUS);
1125         intrenable = intrstatus & core_pmcmask;
1126
1127         PMCDBG2(MDP,INT, 1, "cpu=%d intrstatus=%jx", cpu,
1128             (uintmax_t) intrstatus);
1129
1130         found_interrupt = 0;
1131         cc = core_pcpu[cpu];
1132
1133         KASSERT(cc != NULL, ("[core,%d] null pcpu", __LINE__));
1134
1135         cc->pc_globalctrl &= ~intrenable;
1136         cc->pc_resync = 1;      /* MSRs now potentially out of sync. */
1137
1138         /*
1139          * Stop PMCs and clear overflow status bits.
1140          */
1141         msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK;
1142         wrmsr(IA_GLOBAL_CTRL, msr);
1143         wrmsr(IA_GLOBAL_OVF_CTRL, intrenable |
1144             IA_GLOBAL_STATUS_FLAG_OVFBUF |
1145             IA_GLOBAL_STATUS_FLAG_CONDCHG);
1146
1147         /*
1148          * Look for interrupts from fixed function PMCs.
1149          */
1150         for (n = 0, flag = (1ULL << IAF_OFFSET); n < core_iaf_npmc;
1151              n++, flag <<= 1) {
1152
1153                 if ((intrstatus & flag) == 0)
1154                         continue;
1155
1156                 found_interrupt = 1;
1157
1158                 pm = cc->pc_corepmcs[n + core_iaf_ri].phw_pmc;
1159                 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING ||
1160                     !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
1161                         continue;
1162
1163                 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf,
1164                     TRAPF_USERMODE(tf));
1165
1166                 if (error)
1167                         intrenable &= ~flag;
1168
1169                 v = iaf_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount);
1170
1171                 /* Reload sampling count. */
1172                 wrmsr(IAF_CTR0 + n, v);
1173
1174                 PMCDBG4(MDP,INT, 1, "iaf-intr cpu=%d error=%d v=%jx(%jx)", cpu,
1175                     error, (uintmax_t) v, (uintmax_t) rdpmc(IAF_RI_TO_MSR(n)));
1176         }
1177
1178         /*
1179          * Process interrupts from the programmable counters.
1180          */
1181         for (n = 0, flag = 1; n < core_iap_npmc; n++, flag <<= 1) {
1182                 if ((intrstatus & flag) == 0)
1183                         continue;
1184
1185                 found_interrupt = 1;
1186
1187                 pm = cc->pc_corepmcs[n].phw_pmc;
1188                 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING ||
1189                     !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
1190                         continue;
1191
1192                 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf,
1193                     TRAPF_USERMODE(tf));
1194                 if (error)
1195                         intrenable &= ~flag;
1196
1197                 v = iap_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount);
1198
1199                 PMCDBG3(MDP,INT, 1, "iap-intr cpu=%d error=%d v=%jx", cpu, error,
1200                     (uintmax_t) v);
1201
1202                 /* Reload sampling count. */
1203                 wrmsr(core_iap_wroffset + IAP_PMC0 + n, v);
1204         }
1205
1206         /*
1207          * Reenable all non-stalled PMCs.
1208          */
1209         PMCDBG2(MDP,INT, 1, "cpu=%d intrenable=%jx", cpu,
1210             (uintmax_t) intrenable);
1211
1212         cc->pc_globalctrl |= intrenable;
1213
1214         wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl & IA_GLOBAL_CTRL_MASK);
1215
1216         PMCDBG5(MDP,INT, 1, "cpu=%d fixedctrl=%jx globalctrl=%jx status=%jx "
1217             "ovf=%jx", cpu, (uintmax_t) rdmsr(IAF_CTRL),
1218             (uintmax_t) rdmsr(IA_GLOBAL_CTRL),
1219             (uintmax_t) rdmsr(IA_GLOBAL_STATUS),
1220             (uintmax_t) rdmsr(IA_GLOBAL_OVF_CTRL));
1221
1222         if (found_interrupt)
1223                 lapic_reenable_pmc();
1224
1225         if (found_interrupt)
1226                 counter_u64_add(pmc_stats.pm_intr_processed, 1);
1227         else
1228                 counter_u64_add(pmc_stats.pm_intr_ignored, 1);
1229
1230         return (found_interrupt);
1231 }
1232
1233 int
1234 pmc_core_initialize(struct pmc_mdep *md, int maxcpu, int version_override)
1235 {
1236         int cpuid[CORE_CPUID_REQUEST_SIZE];
1237         int ipa_version, flags, nflags;
1238
1239         do_cpuid(CORE_CPUID_REQUEST, cpuid);
1240
1241         ipa_version = (version_override > 0) ? version_override :
1242             cpuid[CORE_CPUID_EAX] & 0xFF;
1243         core_cputype = md->pmd_cputype;
1244
1245         PMCDBG3(MDP,INI,1,"core-init cputype=%d ncpu=%d ipa-version=%d",
1246             core_cputype, maxcpu, ipa_version);
1247
1248         if (ipa_version < 1 || ipa_version > 4 ||
1249             (core_cputype != PMC_CPU_INTEL_CORE && ipa_version == 1)) {
1250                 /* Unknown PMC architecture. */
1251                 printf("hwpc_core: unknown PMC architecture: %d\n",
1252                     ipa_version);
1253                 return (EPROGMISMATCH);
1254         }
1255
1256         core_iap_wroffset = 0;
1257         if (cpu_feature2 & CPUID2_PDCM) {
1258                 if (rdmsr(IA32_PERF_CAPABILITIES) & PERFCAP_FW_WRITE) {
1259                         PMCDBG0(MDP, INI, 1,
1260                             "core-init full-width write supported");
1261                         core_iap_wroffset = IAP_A_PMC0 - IAP_PMC0;
1262                 } else
1263                         PMCDBG0(MDP, INI, 1,
1264                             "core-init full-width write NOT supported");
1265         } else
1266                 PMCDBG0(MDP, INI, 1, "core-init pdcm not supported");
1267
1268         core_pmcmask = 0;
1269
1270         /*
1271          * Initialize programmable counters.
1272          */
1273         core_iap_npmc = (cpuid[CORE_CPUID_EAX] >> 8) & 0xFF;
1274         core_iap_width = (cpuid[CORE_CPUID_EAX] >> 16) & 0xFF;
1275
1276         core_pmcmask |= ((1ULL << core_iap_npmc) - 1);
1277
1278         nflags = (cpuid[CORE_CPUID_EAX] >> 24) & 0xFF;
1279         flags = cpuid[CORE_CPUID_EBX] & ((1 << nflags) - 1);
1280
1281         iap_initialize(md, maxcpu, core_iap_npmc, core_iap_width, flags);
1282
1283         /*
1284          * Initialize fixed function counters, if present.
1285          */
1286         if (core_cputype != PMC_CPU_INTEL_CORE) {
1287                 core_iaf_ri = core_iap_npmc;
1288                 core_iaf_npmc = cpuid[CORE_CPUID_EDX] & 0x1F;
1289                 core_iaf_width = (cpuid[CORE_CPUID_EDX] >> 5) & 0xFF;
1290
1291                 iaf_initialize(md, maxcpu, core_iaf_npmc, core_iaf_width);
1292                 core_pmcmask |= ((1ULL << core_iaf_npmc) - 1) << IAF_OFFSET;
1293         }
1294
1295         PMCDBG2(MDP,INI,1,"core-init pmcmask=0x%jx iafri=%d", core_pmcmask,
1296             core_iaf_ri);
1297
1298         core_pcpu = malloc(sizeof(*core_pcpu) * maxcpu, M_PMC,
1299             M_ZERO | M_WAITOK);
1300
1301         /*
1302          * Choose the appropriate interrupt handler.
1303          */
1304         if (ipa_version == 1)
1305                 md->pmd_intr = core_intr;
1306         else
1307                 md->pmd_intr = core2_intr;
1308
1309         md->pmd_pcpu_fini = NULL;
1310         md->pmd_pcpu_init = NULL;
1311
1312         return (0);
1313 }
1314
1315 void
1316 pmc_core_finalize(struct pmc_mdep *md)
1317 {
1318         PMCDBG0(MDP,INI,1, "core-finalize");
1319
1320         free(core_pcpu, M_PMC);
1321         core_pcpu = NULL;
1322 }