2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2008 Joseph Koshy
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #include <sys/param.h>
39 #include <sys/pmckern.h>
41 #include <sys/systm.h>
43 #include <machine/intr_machdep.h>
44 #include <x86/apicvar.h>
45 #include <machine/cpu.h>
46 #include <machine/cpufunc.h>
47 #include <machine/md_var.h>
48 #include <machine/specialreg.h>
50 #define CORE_CPUID_REQUEST 0xA
51 #define CORE_CPUID_REQUEST_SIZE 0x4
52 #define CORE_CPUID_EAX 0x0
53 #define CORE_CPUID_EBX 0x1
54 #define CORE_CPUID_ECX 0x2
55 #define CORE_CPUID_EDX 0x3
57 #define IAF_PMC_CAPS \
58 (PMC_CAP_READ | PMC_CAP_WRITE | PMC_CAP_INTERRUPT | \
59 PMC_CAP_USER | PMC_CAP_SYSTEM)
60 #define IAF_RI_TO_MSR(RI) ((RI) + (1 << 30))
62 #define IAP_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | PMC_CAP_SYSTEM | \
63 PMC_CAP_EDGE | PMC_CAP_THRESHOLD | PMC_CAP_READ | PMC_CAP_WRITE | \
64 PMC_CAP_INVERT | PMC_CAP_QUALIFIER | PMC_CAP_PRECISE)
66 #define EV_IS_NOTARCH 0
67 #define EV_IS_ARCH_SUPP 1
68 #define EV_IS_ARCH_NOTSUPP -1
71 * "Architectural" events defined by Intel. The values of these
72 * symbols correspond to positions in the bitmask returned by
73 * the CPUID.0AH instruction.
75 enum core_arch_events {
76 CORE_AE_BRANCH_INSTRUCTION_RETIRED = 5,
77 CORE_AE_BRANCH_MISSES_RETIRED = 6,
78 CORE_AE_INSTRUCTION_RETIRED = 1,
79 CORE_AE_LLC_MISSES = 4,
80 CORE_AE_LLC_REFERENCE = 3,
81 CORE_AE_UNHALTED_REFERENCE_CYCLES = 2,
82 CORE_AE_UNHALTED_CORE_CYCLES = 0
85 static enum pmc_cputype core_cputype;
88 volatile uint32_t pc_resync;
89 volatile uint32_t pc_iafctrl; /* Fixed function control. */
90 volatile uint64_t pc_globalctrl; /* Global control register. */
91 struct pmc_hw pc_corepmcs[];
94 static struct core_cpu **core_pcpu;
96 static uint32_t core_architectural_events;
97 static uint64_t core_pmcmask;
99 static int core_iaf_ri; /* relative index of fixed counters */
100 static int core_iaf_width;
101 static int core_iaf_npmc;
103 static int core_iap_width;
104 static int core_iap_npmc;
105 static int core_iap_wroffset;
107 static u_int pmc_alloc_refs;
108 static bool pmc_tsx_force_abort_set;
111 core_pcpu_noop(struct pmc_mdep *md, int cpu)
119 core_pcpu_init(struct pmc_mdep *md, int cpu)
124 int core_ri, n, npmc;
126 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
127 ("[iaf,%d] insane cpu number %d", __LINE__, cpu));
129 PMCDBG1(MDP,INI,1,"core-init cpu=%d", cpu);
131 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri;
132 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num;
134 if (core_cputype != PMC_CPU_INTEL_CORE)
135 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num;
137 cc = malloc(sizeof(struct core_cpu) + npmc * sizeof(struct pmc_hw),
138 M_PMC, M_WAITOK | M_ZERO);
143 KASSERT(pc != NULL && cc != NULL,
144 ("[core,%d] NULL per-cpu structures cpu=%d", __LINE__, cpu));
146 for (n = 0, phw = cc->pc_corepmcs; n < npmc; n++, phw++) {
147 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED |
148 PMC_PHW_CPU_TO_STATE(cpu) |
149 PMC_PHW_INDEX_TO_STATE(n + core_ri);
151 pc->pc_hwpmcs[n + core_ri] = phw;
158 core_pcpu_fini(struct pmc_mdep *md, int cpu)
160 int core_ri, n, npmc;
165 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
166 ("[core,%d] insane cpu number (%d)", __LINE__, cpu));
168 PMCDBG1(MDP,INI,1,"core-pcpu-fini cpu=%d", cpu);
170 if ((cc = core_pcpu[cpu]) == NULL)
173 core_pcpu[cpu] = NULL;
177 KASSERT(pc != NULL, ("[core,%d] NULL per-cpu %d state", __LINE__,
180 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num;
181 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri;
183 for (n = 0; n < npmc; n++) {
184 msr = rdmsr(IAP_EVSEL0 + n) & ~IAP_EVSEL_MASK;
185 wrmsr(IAP_EVSEL0 + n, msr);
188 if (core_cputype != PMC_CPU_INTEL_CORE) {
189 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK;
190 wrmsr(IAF_CTRL, msr);
191 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num;
194 for (n = 0; n < npmc; n++)
195 pc->pc_hwpmcs[n + core_ri] = NULL;
203 * Fixed function counters.
207 iaf_perfctr_value_to_reload_count(pmc_value_t v)
210 /* If the PMC has overflowed, return a reload count of zero. */
211 if ((v & (1ULL << (core_iaf_width - 1))) == 0)
213 v &= (1ULL << core_iaf_width) - 1;
214 return (1ULL << core_iaf_width) - v;
218 iaf_reload_count_to_perfctr_value(pmc_value_t rlc)
220 return (1ULL << core_iaf_width) - rlc;
224 iaf_allocate_pmc(int cpu, int ri, struct pmc *pm,
225 const struct pmc_op_pmcallocate *a)
228 uint32_t caps, flags, config;
229 const struct pmc_md_iap_op_pmcallocate *iap;
231 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
232 ("[core,%d] illegal CPU %d", __LINE__, cpu));
234 PMCDBG2(MDP,ALL,1, "iaf-allocate ri=%d reqcaps=0x%x", ri, pm->pm_caps);
236 if (ri < 0 || ri > core_iaf_npmc)
241 if (a->pm_class != PMC_CLASS_IAF ||
242 (caps & IAF_PMC_CAPS) != caps)
245 iap = &a->pm_md.pm_iap;
246 config = iap->pm_iap_config;
247 ev = IAP_EVSEL_GET(config);
248 umask = IAP_UMASK_GET(config);
250 /* INST_RETIRED.ANY */
251 if (ev == 0xC0 && ri != 0)
253 /* CPU_CLK_UNHALTED.THREAD */
254 if (ev == 0x3C && ri != 1)
256 /* CPU_CLK_UNHALTED.REF */
257 if (ev == 0x0 && umask == 0x3 && ri != 2)
261 if ((cpu_stdext_feature3 & CPUID_STDEXT3_TSXFA) != 0 &&
262 !pmc_tsx_force_abort_set) {
263 pmc_tsx_force_abort_set = true;
264 x86_msr_op(MSR_TSX_FORCE_ABORT, MSR_OP_RENDEZVOUS |
271 if (config & IAP_USR)
273 if (config & IAP_ANY)
275 if (config & IAP_INT)
278 if (caps & PMC_CAP_INTERRUPT)
280 if (caps & PMC_CAP_SYSTEM)
282 if (caps & PMC_CAP_USER)
284 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0)
285 flags |= (IAF_OS | IAF_USR);
287 pm->pm_md.pm_iaf.pm_iaf_ctrl = (flags << (ri * 4));
289 PMCDBG1(MDP,ALL,2, "iaf-allocate config=0x%jx",
290 (uintmax_t) pm->pm_md.pm_iaf.pm_iaf_ctrl);
296 iaf_config_pmc(int cpu, int ri, struct pmc *pm)
298 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
299 ("[core,%d] illegal CPU %d", __LINE__, cpu));
301 KASSERT(ri >= 0 && ri < core_iaf_npmc,
302 ("[core,%d] illegal row-index %d", __LINE__, ri));
304 PMCDBG3(MDP,CFG,1, "iaf-config cpu=%d ri=%d pm=%p", cpu, ri, pm);
306 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__,
309 core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc = pm;
315 iaf_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
319 char iaf_name[PMC_NAME_MAX];
321 phw = &core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri];
323 (void) snprintf(iaf_name, sizeof(iaf_name), "IAF-%d", ri);
324 if ((error = copystr(iaf_name, pi->pm_name, PMC_NAME_MAX,
328 pi->pm_class = PMC_CLASS_IAF;
330 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
331 pi->pm_enabled = TRUE;
332 *ppmc = phw->phw_pmc;
334 pi->pm_enabled = FALSE;
342 iaf_get_config(int cpu, int ri, struct pmc **ppm)
344 *ppm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc;
350 iaf_get_msr(int ri, uint32_t *msr)
352 KASSERT(ri >= 0 && ri < core_iaf_npmc,
353 ("[iaf,%d] ri %d out of range", __LINE__, ri));
355 *msr = IAF_RI_TO_MSR(ri);
361 iaf_read_pmc(int cpu, int ri, pmc_value_t *v)
366 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
367 ("[core,%d] illegal cpu value %d", __LINE__, cpu));
368 KASSERT(ri >= 0 && ri < core_iaf_npmc,
369 ("[core,%d] illegal row-index %d", __LINE__, ri));
371 pm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc;
374 ("[core,%d] cpu %d ri %d(%d) pmc not configured", __LINE__, cpu,
375 ri, ri + core_iaf_ri));
377 tmp = rdpmc(IAF_RI_TO_MSR(ri));
379 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
380 *v = iaf_perfctr_value_to_reload_count(tmp);
382 *v = tmp & ((1ULL << core_iaf_width) - 1);
384 PMCDBG4(MDP,REA,1, "iaf-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri,
385 IAF_RI_TO_MSR(ri), *v);
391 iaf_release_pmc(int cpu, int ri, struct pmc *pmc)
393 PMCDBG3(MDP,REL,1, "iaf-release cpu=%d ri=%d pm=%p", cpu, ri, pmc);
395 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
396 ("[core,%d] illegal CPU value %d", __LINE__, cpu));
397 KASSERT(ri >= 0 && ri < core_iaf_npmc,
398 ("[core,%d] illegal row-index %d", __LINE__, ri));
400 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc == NULL,
401 ("[core,%d] PHW pmc non-NULL", __LINE__));
403 MPASS(pmc_alloc_refs > 0);
404 if (pmc_alloc_refs-- == 1 && pmc_tsx_force_abort_set) {
405 pmc_tsx_force_abort_set = false;
406 x86_msr_op(MSR_TSX_FORCE_ABORT, MSR_OP_RENDEZVOUS |
414 iaf_start_pmc(int cpu, int ri)
417 struct core_cpu *iafc;
420 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
421 ("[core,%d] illegal CPU value %d", __LINE__, cpu));
422 KASSERT(ri >= 0 && ri < core_iaf_npmc,
423 ("[core,%d] illegal row-index %d", __LINE__, ri));
425 PMCDBG2(MDP,STA,1,"iaf-start cpu=%d ri=%d", cpu, ri);
427 iafc = core_pcpu[cpu];
428 pm = iafc->pc_corepmcs[ri + core_iaf_ri].phw_pmc;
430 iafc->pc_iafctrl |= pm->pm_md.pm_iaf.pm_iaf_ctrl;
432 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK;
433 wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK));
437 iafc->pc_globalctrl |= (1ULL << (ri + IAF_OFFSET));
438 msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK;
439 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl &
440 IAF_GLOBAL_CTRL_MASK));
441 } while (iafc->pc_resync != 0);
443 PMCDBG4(MDP,STA,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)",
444 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL),
445 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL));
451 iaf_stop_pmc(int cpu, int ri)
454 struct core_cpu *iafc;
457 PMCDBG2(MDP,STO,1,"iaf-stop cpu=%d ri=%d", cpu, ri);
459 iafc = core_pcpu[cpu];
461 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
462 ("[core,%d] illegal CPU value %d", __LINE__, cpu));
463 KASSERT(ri >= 0 && ri < core_iaf_npmc,
464 ("[core,%d] illegal row-index %d", __LINE__, ri));
466 fc = (IAF_MASK << (ri * 4));
468 iafc->pc_iafctrl &= ~fc;
470 PMCDBG1(MDP,STO,1,"iaf-stop iafctrl=%x", iafc->pc_iafctrl);
471 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK;
472 wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK));
476 iafc->pc_globalctrl &= ~(1ULL << (ri + IAF_OFFSET));
477 msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK;
478 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl &
479 IAF_GLOBAL_CTRL_MASK));
480 } while (iafc->pc_resync != 0);
482 PMCDBG4(MDP,STO,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)",
483 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL),
484 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL));
490 iaf_write_pmc(int cpu, int ri, pmc_value_t v)
496 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
497 ("[core,%d] illegal cpu value %d", __LINE__, cpu));
498 KASSERT(ri >= 0 && ri < core_iaf_npmc,
499 ("[core,%d] illegal row-index %d", __LINE__, ri));
502 pm = cc->pc_corepmcs[ri + core_iaf_ri].phw_pmc;
505 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, ri));
507 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
508 v = iaf_reload_count_to_perfctr_value(v);
510 /* Turn off fixed counters */
511 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK;
512 wrmsr(IAF_CTRL, msr);
514 wrmsr(IAF_CTR0 + ri, v & ((1ULL << core_iaf_width) - 1));
516 /* Turn on fixed counters */
517 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK;
518 wrmsr(IAF_CTRL, msr | (cc->pc_iafctrl & IAF_CTRL_MASK));
520 PMCDBG6(MDP,WRI,1, "iaf-write cpu=%d ri=%d msr=0x%x v=%jx iafctrl=%jx "
521 "pmc=%jx", cpu, ri, IAF_RI_TO_MSR(ri), v,
522 (uintmax_t) rdmsr(IAF_CTRL),
523 (uintmax_t) rdpmc(IAF_RI_TO_MSR(ri)));
530 iaf_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth)
532 struct pmc_classdep *pcd;
534 KASSERT(md != NULL, ("[iaf,%d] md is NULL", __LINE__));
536 PMCDBG0(MDP,INI,1, "iaf-initialize");
538 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF];
540 pcd->pcd_caps = IAF_PMC_CAPS;
541 pcd->pcd_class = PMC_CLASS_IAF;
543 pcd->pcd_ri = md->pmd_npmc;
544 pcd->pcd_width = pmcwidth;
546 pcd->pcd_allocate_pmc = iaf_allocate_pmc;
547 pcd->pcd_config_pmc = iaf_config_pmc;
548 pcd->pcd_describe = iaf_describe;
549 pcd->pcd_get_config = iaf_get_config;
550 pcd->pcd_get_msr = iaf_get_msr;
551 pcd->pcd_pcpu_fini = core_pcpu_noop;
552 pcd->pcd_pcpu_init = core_pcpu_noop;
553 pcd->pcd_read_pmc = iaf_read_pmc;
554 pcd->pcd_release_pmc = iaf_release_pmc;
555 pcd->pcd_start_pmc = iaf_start_pmc;
556 pcd->pcd_stop_pmc = iaf_stop_pmc;
557 pcd->pcd_write_pmc = iaf_write_pmc;
559 md->pmd_npmc += npmc;
563 * Intel programmable PMCs.
566 /* Sub fields of UMASK that this event supports. */
567 #define IAP_M_CORE (1 << 0) /* Core specificity */
568 #define IAP_M_AGENT (1 << 1) /* Agent specificity */
569 #define IAP_M_PREFETCH (1 << 2) /* Prefetch */
570 #define IAP_M_MESI (1 << 3) /* MESI */
571 #define IAP_M_SNOOPRESPONSE (1 << 4) /* Snoop response */
572 #define IAP_M_SNOOPTYPE (1 << 5) /* Snoop type */
573 #define IAP_M_TRANSITION (1 << 6) /* Transition */
575 #define IAP_F_CORE (0x3 << 14) /* Core specificity */
576 #define IAP_F_AGENT (0x1 << 13) /* Agent specificity */
577 #define IAP_F_PREFETCH (0x3 << 12) /* Prefetch */
578 #define IAP_F_MESI (0xF << 8) /* MESI */
579 #define IAP_F_SNOOPRESPONSE (0xB << 8) /* Snoop response */
580 #define IAP_F_SNOOPTYPE (0x3 << 8) /* Snoop type */
581 #define IAP_F_TRANSITION (0x1 << 12) /* Transition */
583 #define IAP_PREFETCH_RESERVED (0x2 << 12)
584 #define IAP_CORE_THIS (0x1 << 14)
585 #define IAP_CORE_ALL (0x3 << 14)
586 #define IAP_F_CMASK 0xFF000000
589 iap_perfctr_value_to_reload_count(pmc_value_t v)
592 /* If the PMC has overflowed, return a reload count of zero. */
593 if ((v & (1ULL << (core_iap_width - 1))) == 0)
595 v &= (1ULL << core_iap_width) - 1;
596 return (1ULL << core_iap_width) - v;
600 iap_reload_count_to_perfctr_value(pmc_value_t rlc)
602 return (1ULL << core_iap_width) - rlc;
606 iap_pmc_has_overflowed(int ri)
611 * We treat a Core (i.e., Intel architecture v1) PMC as has
612 * having overflowed if its MSB is zero.
615 return ((v & (1ULL << (core_iap_width - 1))) == 0);
619 iap_event_corei7_ok_on_counter(uint8_t evsel, int ri)
625 * Events valid only on counter 0, 1.
637 mask = ~0; /* Any row index is ok. */
640 return (mask & (1 << ri));
644 iap_event_westmere_ok_on_counter(uint8_t evsel, int ri)
650 * Events valid only on counter 0.
658 * Events valid only on counter 0, 1.
668 mask = ~0; /* Any row index is ok. */
671 return (mask & (1 << ri));
675 iap_event_sb_sbx_ib_ibx_ok_on_counter(uint8_t evsel, int ri)
680 /* Events valid only on counter 0. */
684 /* Events valid only on counter 1. */
688 /* Events valid only on counter 2. */
694 /* Events valid only on counter 3. */
700 mask = ~0; /* Any row index is ok. */
703 return (mask & (1 << ri));
707 iap_event_ok_on_counter(uint8_t evsel, int ri)
713 * Events valid only on counter 0.
725 * Events valid only on counter 1.
734 mask = ~0; /* Any row index is ok. */
737 return (mask & (1 << ri));
741 iap_allocate_pmc(int cpu, int ri, struct pmc *pm,
742 const struct pmc_op_pmcallocate *a)
747 const struct pmc_md_iap_op_pmcallocate *iap;
749 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
750 ("[core,%d] illegal CPU %d", __LINE__, cpu));
751 KASSERT(ri >= 0 && ri < core_iap_npmc,
752 ("[core,%d] illegal row-index value %d", __LINE__, ri));
754 /* check requested capabilities */
756 if ((IAP_PMC_CAPS & caps) != caps)
758 map = 0; /* XXX: silent GCC warning */
759 iap = &a->pm_md.pm_iap;
760 ev = IAP_EVSEL_GET(iap->pm_iap_config);
762 switch (core_cputype) {
763 case PMC_CPU_INTEL_COREI7:
764 case PMC_CPU_INTEL_NEHALEM_EX:
765 if (iap_event_corei7_ok_on_counter(ev, ri) == 0)
768 case PMC_CPU_INTEL_SKYLAKE:
769 case PMC_CPU_INTEL_SKYLAKE_XEON:
770 case PMC_CPU_INTEL_BROADWELL:
771 case PMC_CPU_INTEL_BROADWELL_XEON:
772 case PMC_CPU_INTEL_SANDYBRIDGE:
773 case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
774 case PMC_CPU_INTEL_IVYBRIDGE:
775 case PMC_CPU_INTEL_IVYBRIDGE_XEON:
776 case PMC_CPU_INTEL_HASWELL:
777 case PMC_CPU_INTEL_HASWELL_XEON:
778 if (iap_event_sb_sbx_ib_ibx_ok_on_counter(ev, ri) == 0)
781 case PMC_CPU_INTEL_WESTMERE:
782 case PMC_CPU_INTEL_WESTMERE_EX:
783 if (iap_event_westmere_ok_on_counter(ev, ri) == 0)
787 if (iap_event_ok_on_counter(ev, ri) == 0)
791 pm->pm_md.pm_iap.pm_iap_evsel = iap->pm_iap_config;
796 iap_config_pmc(int cpu, int ri, struct pmc *pm)
798 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
799 ("[core,%d] illegal CPU %d", __LINE__, cpu));
801 KASSERT(ri >= 0 && ri < core_iap_npmc,
802 ("[core,%d] illegal row-index %d", __LINE__, ri));
804 PMCDBG3(MDP,CFG,1, "iap-config cpu=%d ri=%d pm=%p", cpu, ri, pm);
806 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__,
809 core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc = pm;
815 iap_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
819 char iap_name[PMC_NAME_MAX];
821 phw = &core_pcpu[cpu]->pc_corepmcs[ri];
823 (void) snprintf(iap_name, sizeof(iap_name), "IAP-%d", ri);
824 if ((error = copystr(iap_name, pi->pm_name, PMC_NAME_MAX,
828 pi->pm_class = PMC_CLASS_IAP;
830 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
831 pi->pm_enabled = TRUE;
832 *ppmc = phw->phw_pmc;
834 pi->pm_enabled = FALSE;
842 iap_get_config(int cpu, int ri, struct pmc **ppm)
844 *ppm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc;
850 iap_get_msr(int ri, uint32_t *msr)
852 KASSERT(ri >= 0 && ri < core_iap_npmc,
853 ("[iap,%d] ri %d out of range", __LINE__, ri));
861 iap_read_pmc(int cpu, int ri, pmc_value_t *v)
866 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
867 ("[core,%d] illegal cpu value %d", __LINE__, cpu));
868 KASSERT(ri >= 0 && ri < core_iap_npmc,
869 ("[core,%d] illegal row-index %d", __LINE__, ri));
871 pm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc;
874 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu,
878 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
879 *v = iap_perfctr_value_to_reload_count(tmp);
881 *v = tmp & ((1ULL << core_iap_width) - 1);
883 PMCDBG4(MDP,REA,1, "iap-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri,
890 iap_release_pmc(int cpu, int ri, struct pmc *pm)
894 PMCDBG3(MDP,REL,1, "iap-release cpu=%d ri=%d pm=%p", cpu, ri,
897 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
898 ("[core,%d] illegal CPU value %d", __LINE__, cpu));
899 KASSERT(ri >= 0 && ri < core_iap_npmc,
900 ("[core,%d] illegal row-index %d", __LINE__, ri));
902 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc
903 == NULL, ("[core,%d] PHW pmc non-NULL", __LINE__));
909 iap_start_pmc(int cpu, int ri)
915 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
916 ("[core,%d] illegal CPU value %d", __LINE__, cpu));
917 KASSERT(ri >= 0 && ri < core_iap_npmc,
918 ("[core,%d] illegal row-index %d", __LINE__, ri));
921 pm = cc->pc_corepmcs[ri].phw_pmc;
924 ("[core,%d] starting cpu%d,ri%d with no pmc configured",
927 PMCDBG2(MDP,STA,1, "iap-start cpu=%d ri=%d", cpu, ri);
929 evsel = pm->pm_md.pm_iap.pm_iap_evsel;
931 PMCDBG4(MDP,STA,2, "iap-start/2 cpu=%d ri=%d evselmsr=0x%x evsel=0x%x",
932 cpu, ri, IAP_EVSEL0 + ri, evsel);
934 /* Event specific configuration. */
936 switch (IAP_EVSEL_GET(evsel)) {
938 wrmsr(IA_OFFCORE_RSP0, pm->pm_md.pm_iap.pm_iap_rsp);
941 wrmsr(IA_OFFCORE_RSP1, pm->pm_md.pm_iap.pm_iap_rsp);
947 wrmsr(IAP_EVSEL0 + ri, evsel | IAP_EN);
949 if (core_cputype == PMC_CPU_INTEL_CORE)
954 cc->pc_globalctrl |= (1ULL << ri);
955 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl);
956 } while (cc->pc_resync != 0);
962 iap_stop_pmc(int cpu, int ri)
968 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
969 ("[core,%d] illegal cpu value %d", __LINE__, cpu));
970 KASSERT(ri >= 0 && ri < core_iap_npmc,
971 ("[core,%d] illegal row index %d", __LINE__, ri));
974 pm = cc->pc_corepmcs[ri].phw_pmc;
977 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__,
980 PMCDBG2(MDP,STO,1, "iap-stop cpu=%d ri=%d", cpu, ri);
982 msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK;
983 wrmsr(IAP_EVSEL0 + ri, msr); /* stop hw */
985 if (core_cputype == PMC_CPU_INTEL_CORE)
991 cc->pc_globalctrl &= ~(1ULL << ri);
992 msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK;
993 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl);
994 } while (cc->pc_resync != 0);
1000 iap_write_pmc(int cpu, int ri, pmc_value_t v)
1003 struct core_cpu *cc;
1005 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
1006 ("[core,%d] illegal cpu value %d", __LINE__, cpu));
1007 KASSERT(ri >= 0 && ri < core_iap_npmc,
1008 ("[core,%d] illegal row index %d", __LINE__, ri));
1010 cc = core_pcpu[cpu];
1011 pm = cc->pc_corepmcs[ri].phw_pmc;
1014 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__,
1017 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
1018 v = iap_reload_count_to_perfctr_value(v);
1020 v &= (1ULL << core_iap_width) - 1;
1022 PMCDBG4(MDP,WRI,1, "iap-write cpu=%d ri=%d msr=0x%x v=%jx", cpu, ri,
1026 * Write the new value to the counter (or it's alias). The
1027 * counter will be in a stopped state when the pcd_write()
1028 * entry point is called.
1030 wrmsr(core_iap_wroffset + IAP_PMC0 + ri, v);
1036 iap_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth,
1039 struct pmc_classdep *pcd;
1041 KASSERT(md != NULL, ("[iap,%d] md is NULL", __LINE__));
1043 PMCDBG0(MDP,INI,1, "iap-initialize");
1045 /* Remember the set of architectural events supported. */
1046 core_architectural_events = ~flags;
1048 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP];
1050 pcd->pcd_caps = IAP_PMC_CAPS;
1051 pcd->pcd_class = PMC_CLASS_IAP;
1052 pcd->pcd_num = npmc;
1053 pcd->pcd_ri = md->pmd_npmc;
1054 pcd->pcd_width = pmcwidth;
1056 pcd->pcd_allocate_pmc = iap_allocate_pmc;
1057 pcd->pcd_config_pmc = iap_config_pmc;
1058 pcd->pcd_describe = iap_describe;
1059 pcd->pcd_get_config = iap_get_config;
1060 pcd->pcd_get_msr = iap_get_msr;
1061 pcd->pcd_pcpu_fini = core_pcpu_fini;
1062 pcd->pcd_pcpu_init = core_pcpu_init;
1063 pcd->pcd_read_pmc = iap_read_pmc;
1064 pcd->pcd_release_pmc = iap_release_pmc;
1065 pcd->pcd_start_pmc = iap_start_pmc;
1066 pcd->pcd_stop_pmc = iap_stop_pmc;
1067 pcd->pcd_write_pmc = iap_write_pmc;
1069 md->pmd_npmc += npmc;
1073 core_intr(struct trapframe *tf)
1077 struct core_cpu *cc;
1078 int error, found_interrupt, ri;
1081 PMCDBG3(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", curcpu, (void *) tf,
1082 TRAPF_USERMODE(tf));
1084 found_interrupt = 0;
1085 cc = core_pcpu[curcpu];
1087 for (ri = 0; ri < core_iap_npmc; ri++) {
1089 if ((pm = cc->pc_corepmcs[ri].phw_pmc) == NULL ||
1090 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
1093 if (!iap_pmc_has_overflowed(ri))
1096 found_interrupt = 1;
1098 if (pm->pm_state != PMC_STATE_RUNNING)
1101 error = pmc_process_interrupt(PMC_HR, pm, tf);
1103 v = pm->pm_sc.pm_reloadcount;
1104 v = iap_reload_count_to_perfctr_value(v);
1107 * Stop the counter, reload it but only restart it if
1108 * the PMC is not stalled.
1110 msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK;
1111 wrmsr(IAP_EVSEL0 + ri, msr);
1112 wrmsr(core_iap_wroffset + IAP_PMC0 + ri, v);
1117 wrmsr(IAP_EVSEL0 + ri, msr | (pm->pm_md.pm_iap.pm_iap_evsel |
1121 if (found_interrupt)
1122 lapic_reenable_pmc();
1124 if (found_interrupt)
1125 counter_u64_add(pmc_stats.pm_intr_processed, 1);
1127 counter_u64_add(pmc_stats.pm_intr_ignored, 1);
1129 return (found_interrupt);
1133 core2_intr(struct trapframe *tf)
1135 int error, found_interrupt, n, cpu;
1136 uint64_t flag, intrstatus, intrenable, msr;
1138 struct core_cpu *cc;
1142 PMCDBG3(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf,
1143 TRAPF_USERMODE(tf));
1146 * The IA_GLOBAL_STATUS (MSR 0x38E) register indicates which
1147 * PMCs have a pending PMI interrupt. We take a 'snapshot' of
1148 * the current set of interrupting PMCs and process these
1149 * after stopping them.
1151 intrstatus = rdmsr(IA_GLOBAL_STATUS);
1152 intrenable = intrstatus & core_pmcmask;
1154 PMCDBG2(MDP,INT, 1, "cpu=%d intrstatus=%jx", cpu,
1155 (uintmax_t) intrstatus);
1157 found_interrupt = 0;
1158 cc = core_pcpu[cpu];
1160 KASSERT(cc != NULL, ("[core,%d] null pcpu", __LINE__));
1162 cc->pc_globalctrl &= ~intrenable;
1163 cc->pc_resync = 1; /* MSRs now potentially out of sync. */
1166 * Stop PMCs and clear overflow status bits.
1168 msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK;
1169 wrmsr(IA_GLOBAL_CTRL, msr);
1170 wrmsr(IA_GLOBAL_OVF_CTRL, intrenable |
1171 IA_GLOBAL_STATUS_FLAG_OVFBUF |
1172 IA_GLOBAL_STATUS_FLAG_CONDCHG);
1175 * Look for interrupts from fixed function PMCs.
1177 for (n = 0, flag = (1ULL << IAF_OFFSET); n < core_iaf_npmc;
1180 if ((intrstatus & flag) == 0)
1183 found_interrupt = 1;
1185 pm = cc->pc_corepmcs[n + core_iaf_ri].phw_pmc;
1186 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING ||
1187 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
1190 error = pmc_process_interrupt(PMC_HR, pm, tf);
1193 intrenable &= ~flag;
1195 v = iaf_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount);
1197 /* Reload sampling count. */
1198 wrmsr(IAF_CTR0 + n, v);
1200 PMCDBG4(MDP,INT, 1, "iaf-intr cpu=%d error=%d v=%jx(%jx)", curcpu,
1201 error, (uintmax_t) v, (uintmax_t) rdpmc(IAF_RI_TO_MSR(n)));
1205 * Process interrupts from the programmable counters.
1207 for (n = 0, flag = 1; n < core_iap_npmc; n++, flag <<= 1) {
1208 if ((intrstatus & flag) == 0)
1211 found_interrupt = 1;
1213 pm = cc->pc_corepmcs[n].phw_pmc;
1214 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING ||
1215 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
1218 error = pmc_process_interrupt(PMC_HR, pm, tf);
1220 intrenable &= ~flag;
1222 v = iap_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount);
1224 PMCDBG3(MDP,INT, 1, "iap-intr cpu=%d error=%d v=%jx", cpu, error,
1227 /* Reload sampling count. */
1228 wrmsr(core_iap_wroffset + IAP_PMC0 + n, v);
1232 * Reenable all non-stalled PMCs.
1234 PMCDBG2(MDP,INT, 1, "cpu=%d intrenable=%jx", cpu,
1235 (uintmax_t) intrenable);
1237 cc->pc_globalctrl |= intrenable;
1239 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl & IA_GLOBAL_CTRL_MASK);
1241 PMCDBG5(MDP,INT, 1, "cpu=%d fixedctrl=%jx globalctrl=%jx status=%jx "
1242 "ovf=%jx", cpu, (uintmax_t) rdmsr(IAF_CTRL),
1243 (uintmax_t) rdmsr(IA_GLOBAL_CTRL),
1244 (uintmax_t) rdmsr(IA_GLOBAL_STATUS),
1245 (uintmax_t) rdmsr(IA_GLOBAL_OVF_CTRL));
1247 if (found_interrupt)
1248 lapic_reenable_pmc();
1250 if (found_interrupt)
1251 counter_u64_add(pmc_stats.pm_intr_processed, 1);
1253 counter_u64_add(pmc_stats.pm_intr_ignored, 1);
1255 return (found_interrupt);
1259 pmc_core_initialize(struct pmc_mdep *md, int maxcpu, int version_override)
1261 int cpuid[CORE_CPUID_REQUEST_SIZE];
1262 int ipa_version, flags, nflags;
1264 do_cpuid(CORE_CPUID_REQUEST, cpuid);
1266 ipa_version = (version_override > 0) ? version_override :
1267 cpuid[CORE_CPUID_EAX] & 0xFF;
1268 core_cputype = md->pmd_cputype;
1270 PMCDBG3(MDP,INI,1,"core-init cputype=%d ncpu=%d ipa-version=%d",
1271 core_cputype, maxcpu, ipa_version);
1273 if (ipa_version < 1 || ipa_version > 4 ||
1274 (core_cputype != PMC_CPU_INTEL_CORE && ipa_version == 1)) {
1275 /* Unknown PMC architecture. */
1276 printf("hwpc_core: unknown PMC architecture: %d\n",
1278 return (EPROGMISMATCH);
1281 core_iap_wroffset = 0;
1282 if (cpu_feature2 & CPUID2_PDCM) {
1283 if (rdmsr(IA32_PERF_CAPABILITIES) & PERFCAP_FW_WRITE) {
1284 PMCDBG0(MDP, INI, 1,
1285 "core-init full-width write supported");
1286 core_iap_wroffset = IAP_A_PMC0 - IAP_PMC0;
1288 PMCDBG0(MDP, INI, 1,
1289 "core-init full-width write NOT supported");
1291 PMCDBG0(MDP, INI, 1, "core-init pdcm not supported");
1296 * Initialize programmable counters.
1298 core_iap_npmc = (cpuid[CORE_CPUID_EAX] >> 8) & 0xFF;
1299 core_iap_width = (cpuid[CORE_CPUID_EAX] >> 16) & 0xFF;
1301 core_pmcmask |= ((1ULL << core_iap_npmc) - 1);
1303 nflags = (cpuid[CORE_CPUID_EAX] >> 24) & 0xFF;
1304 flags = cpuid[CORE_CPUID_EBX] & ((1 << nflags) - 1);
1306 iap_initialize(md, maxcpu, core_iap_npmc, core_iap_width, flags);
1309 * Initialize fixed function counters, if present.
1311 if (core_cputype != PMC_CPU_INTEL_CORE) {
1312 core_iaf_ri = core_iap_npmc;
1313 core_iaf_npmc = cpuid[CORE_CPUID_EDX] & 0x1F;
1314 core_iaf_width = (cpuid[CORE_CPUID_EDX] >> 5) & 0xFF;
1316 iaf_initialize(md, maxcpu, core_iaf_npmc, core_iaf_width);
1317 core_pmcmask |= ((1ULL << core_iaf_npmc) - 1) << IAF_OFFSET;
1320 PMCDBG2(MDP,INI,1,"core-init pmcmask=0x%jx iafri=%d", core_pmcmask,
1323 core_pcpu = malloc(sizeof(*core_pcpu) * maxcpu, M_PMC,
1327 * Choose the appropriate interrupt handler.
1329 if (ipa_version == 1)
1330 md->pmd_intr = core_intr;
1332 md->pmd_intr = core2_intr;
1334 md->pmd_pcpu_fini = NULL;
1335 md->pmd_pcpu_init = NULL;
1341 pmc_core_finalize(struct pmc_mdep *md)
1343 PMCDBG0(MDP,INI,1, "core-finalize");
1345 free(core_pcpu, M_PMC);