2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2008 Joseph Koshy
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #include <sys/param.h>
39 #include <sys/pmckern.h>
40 #include <sys/systm.h>
42 #include <machine/intr_machdep.h>
43 #if (__FreeBSD_version >= 1100000)
44 #include <x86/apicvar.h>
46 #include <machine/apicvar.h>
48 #include <machine/cpu.h>
49 #include <machine/cpufunc.h>
50 #include <machine/md_var.h>
51 #include <machine/specialreg.h>
53 #define CORE_CPUID_REQUEST 0xA
54 #define CORE_CPUID_REQUEST_SIZE 0x4
55 #define CORE_CPUID_EAX 0x0
56 #define CORE_CPUID_EBX 0x1
57 #define CORE_CPUID_ECX 0x2
58 #define CORE_CPUID_EDX 0x3
60 #define IAF_PMC_CAPS \
61 (PMC_CAP_READ | PMC_CAP_WRITE | PMC_CAP_INTERRUPT | \
62 PMC_CAP_USER | PMC_CAP_SYSTEM)
63 #define IAF_RI_TO_MSR(RI) ((RI) + (1 << 30))
65 #define IAP_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | PMC_CAP_SYSTEM | \
66 PMC_CAP_EDGE | PMC_CAP_THRESHOLD | PMC_CAP_READ | PMC_CAP_WRITE | \
67 PMC_CAP_INVERT | PMC_CAP_QUALIFIER | PMC_CAP_PRECISE)
69 #define EV_IS_NOTARCH 0
70 #define EV_IS_ARCH_SUPP 1
71 #define EV_IS_ARCH_NOTSUPP -1
74 * "Architectural" events defined by Intel. The values of these
75 * symbols correspond to positions in the bitmask returned by
76 * the CPUID.0AH instruction.
78 enum core_arch_events {
79 CORE_AE_BRANCH_INSTRUCTION_RETIRED = 5,
80 CORE_AE_BRANCH_MISSES_RETIRED = 6,
81 CORE_AE_INSTRUCTION_RETIRED = 1,
82 CORE_AE_LLC_MISSES = 4,
83 CORE_AE_LLC_REFERENCE = 3,
84 CORE_AE_UNHALTED_REFERENCE_CYCLES = 2,
85 CORE_AE_UNHALTED_CORE_CYCLES = 0
88 static enum pmc_cputype core_cputype;
91 volatile uint32_t pc_resync;
92 volatile uint32_t pc_iafctrl; /* Fixed function control. */
93 volatile uint64_t pc_globalctrl; /* Global control register. */
94 struct pmc_hw pc_corepmcs[];
97 static struct core_cpu **core_pcpu;
99 static uint32_t core_architectural_events;
100 static uint64_t core_pmcmask;
102 static int core_iaf_ri; /* relative index of fixed counters */
103 static int core_iaf_width;
104 static int core_iaf_npmc;
106 static int core_iap_width;
107 static int core_iap_npmc;
108 static int core_iap_wroffset;
111 core_pcpu_noop(struct pmc_mdep *md, int cpu)
119 core_pcpu_init(struct pmc_mdep *md, int cpu)
124 int core_ri, n, npmc;
126 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
127 ("[iaf,%d] insane cpu number %d", __LINE__, cpu));
129 PMCDBG1(MDP,INI,1,"core-init cpu=%d", cpu);
131 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri;
132 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num;
134 if (core_cputype != PMC_CPU_INTEL_CORE)
135 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num;
137 cc = malloc(sizeof(struct core_cpu) + npmc * sizeof(struct pmc_hw),
138 M_PMC, M_WAITOK | M_ZERO);
143 KASSERT(pc != NULL && cc != NULL,
144 ("[core,%d] NULL per-cpu structures cpu=%d", __LINE__, cpu));
146 for (n = 0, phw = cc->pc_corepmcs; n < npmc; n++, phw++) {
147 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED |
148 PMC_PHW_CPU_TO_STATE(cpu) |
149 PMC_PHW_INDEX_TO_STATE(n + core_ri);
151 pc->pc_hwpmcs[n + core_ri] = phw;
158 core_pcpu_fini(struct pmc_mdep *md, int cpu)
160 int core_ri, n, npmc;
165 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
166 ("[core,%d] insane cpu number (%d)", __LINE__, cpu));
168 PMCDBG1(MDP,INI,1,"core-pcpu-fini cpu=%d", cpu);
170 if ((cc = core_pcpu[cpu]) == NULL)
173 core_pcpu[cpu] = NULL;
177 KASSERT(pc != NULL, ("[core,%d] NULL per-cpu %d state", __LINE__,
180 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num;
181 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri;
183 for (n = 0; n < npmc; n++) {
184 msr = rdmsr(IAP_EVSEL0 + n) & ~IAP_EVSEL_MASK;
185 wrmsr(IAP_EVSEL0 + n, msr);
188 if (core_cputype != PMC_CPU_INTEL_CORE) {
189 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK;
190 wrmsr(IAF_CTRL, msr);
191 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num;
194 for (n = 0; n < npmc; n++)
195 pc->pc_hwpmcs[n + core_ri] = NULL;
203 * Fixed function counters.
207 iaf_perfctr_value_to_reload_count(pmc_value_t v)
210 /* If the PMC has overflowed, return a reload count of zero. */
211 if ((v & (1ULL << (core_iaf_width - 1))) == 0)
213 v &= (1ULL << core_iaf_width) - 1;
214 return (1ULL << core_iaf_width) - v;
218 iaf_reload_count_to_perfctr_value(pmc_value_t rlc)
220 return (1ULL << core_iaf_width) - rlc;
224 iaf_allocate_pmc(int cpu, int ri, struct pmc *pm,
225 const struct pmc_op_pmcallocate *a)
228 uint32_t caps, flags, config;
229 const struct pmc_md_iap_op_pmcallocate *iap;
231 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
232 ("[core,%d] illegal CPU %d", __LINE__, cpu));
234 PMCDBG2(MDP,ALL,1, "iaf-allocate ri=%d reqcaps=0x%x", ri, pm->pm_caps);
236 if (ri < 0 || ri > core_iaf_npmc)
241 if (a->pm_class != PMC_CLASS_IAF ||
242 (caps & IAF_PMC_CAPS) != caps)
245 iap = &a->pm_md.pm_iap;
246 config = iap->pm_iap_config;
247 ev = IAP_EVSEL_GET(config);
248 umask = IAP_UMASK_GET(config);
250 /* INST_RETIRED.ANY */
251 if (ev == 0xC0 && ri != 0)
253 /* CPU_CLK_UNHALTED.THREAD */
254 if (ev == 0x3C && ri != 1)
256 /* CPU_CLK_UNHALTED.REF */
257 if (ev == 0x0 && umask == 0x3 && ri != 2)
264 if (config & IAP_USR)
266 if (config & IAP_ANY)
268 if (config & IAP_INT)
271 if (caps & PMC_CAP_INTERRUPT)
273 if (caps & PMC_CAP_SYSTEM)
275 if (caps & PMC_CAP_USER)
277 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0)
278 flags |= (IAF_OS | IAF_USR);
280 pm->pm_md.pm_iaf.pm_iaf_ctrl = (flags << (ri * 4));
282 PMCDBG1(MDP,ALL,2, "iaf-allocate config=0x%jx",
283 (uintmax_t) pm->pm_md.pm_iaf.pm_iaf_ctrl);
289 iaf_config_pmc(int cpu, int ri, struct pmc *pm)
291 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
292 ("[core,%d] illegal CPU %d", __LINE__, cpu));
294 KASSERT(ri >= 0 && ri < core_iaf_npmc,
295 ("[core,%d] illegal row-index %d", __LINE__, ri));
297 PMCDBG3(MDP,CFG,1, "iaf-config cpu=%d ri=%d pm=%p", cpu, ri, pm);
299 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__,
302 core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc = pm;
308 iaf_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
312 char iaf_name[PMC_NAME_MAX];
314 phw = &core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri];
316 (void) snprintf(iaf_name, sizeof(iaf_name), "IAF-%d", ri);
317 if ((error = copystr(iaf_name, pi->pm_name, PMC_NAME_MAX,
321 pi->pm_class = PMC_CLASS_IAF;
323 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
324 pi->pm_enabled = TRUE;
325 *ppmc = phw->phw_pmc;
327 pi->pm_enabled = FALSE;
335 iaf_get_config(int cpu, int ri, struct pmc **ppm)
337 *ppm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc;
343 iaf_get_msr(int ri, uint32_t *msr)
345 KASSERT(ri >= 0 && ri < core_iaf_npmc,
346 ("[iaf,%d] ri %d out of range", __LINE__, ri));
348 *msr = IAF_RI_TO_MSR(ri);
354 iaf_read_pmc(int cpu, int ri, pmc_value_t *v)
359 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
360 ("[core,%d] illegal cpu value %d", __LINE__, cpu));
361 KASSERT(ri >= 0 && ri < core_iaf_npmc,
362 ("[core,%d] illegal row-index %d", __LINE__, ri));
364 pm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc;
367 ("[core,%d] cpu %d ri %d(%d) pmc not configured", __LINE__, cpu,
368 ri, ri + core_iaf_ri));
370 tmp = rdpmc(IAF_RI_TO_MSR(ri));
372 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
373 *v = iaf_perfctr_value_to_reload_count(tmp);
375 *v = tmp & ((1ULL << core_iaf_width) - 1);
377 PMCDBG4(MDP,REA,1, "iaf-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri,
378 IAF_RI_TO_MSR(ri), *v);
384 iaf_release_pmc(int cpu, int ri, struct pmc *pmc)
386 PMCDBG3(MDP,REL,1, "iaf-release cpu=%d ri=%d pm=%p", cpu, ri, pmc);
388 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
389 ("[core,%d] illegal CPU value %d", __LINE__, cpu));
390 KASSERT(ri >= 0 && ri < core_iaf_npmc,
391 ("[core,%d] illegal row-index %d", __LINE__, ri));
393 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc == NULL,
394 ("[core,%d] PHW pmc non-NULL", __LINE__));
400 iaf_start_pmc(int cpu, int ri)
403 struct core_cpu *iafc;
406 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
407 ("[core,%d] illegal CPU value %d", __LINE__, cpu));
408 KASSERT(ri >= 0 && ri < core_iaf_npmc,
409 ("[core,%d] illegal row-index %d", __LINE__, ri));
411 PMCDBG2(MDP,STA,1,"iaf-start cpu=%d ri=%d", cpu, ri);
413 iafc = core_pcpu[cpu];
414 pm = iafc->pc_corepmcs[ri + core_iaf_ri].phw_pmc;
416 iafc->pc_iafctrl |= pm->pm_md.pm_iaf.pm_iaf_ctrl;
418 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK;
419 wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK));
423 iafc->pc_globalctrl |= (1ULL << (ri + IAF_OFFSET));
424 msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK;
425 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl &
426 IAF_GLOBAL_CTRL_MASK));
427 } while (iafc->pc_resync != 0);
429 PMCDBG4(MDP,STA,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)",
430 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL),
431 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL));
437 iaf_stop_pmc(int cpu, int ri)
440 struct core_cpu *iafc;
443 PMCDBG2(MDP,STO,1,"iaf-stop cpu=%d ri=%d", cpu, ri);
445 iafc = core_pcpu[cpu];
447 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
448 ("[core,%d] illegal CPU value %d", __LINE__, cpu));
449 KASSERT(ri >= 0 && ri < core_iaf_npmc,
450 ("[core,%d] illegal row-index %d", __LINE__, ri));
452 fc = (IAF_MASK << (ri * 4));
454 iafc->pc_iafctrl &= ~fc;
456 PMCDBG1(MDP,STO,1,"iaf-stop iafctrl=%x", iafc->pc_iafctrl);
457 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK;
458 wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK));
462 iafc->pc_globalctrl &= ~(1ULL << (ri + IAF_OFFSET));
463 msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK;
464 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl &
465 IAF_GLOBAL_CTRL_MASK));
466 } while (iafc->pc_resync != 0);
468 PMCDBG4(MDP,STO,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)",
469 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL),
470 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL));
476 iaf_write_pmc(int cpu, int ri, pmc_value_t v)
482 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
483 ("[core,%d] illegal cpu value %d", __LINE__, cpu));
484 KASSERT(ri >= 0 && ri < core_iaf_npmc,
485 ("[core,%d] illegal row-index %d", __LINE__, ri));
488 pm = cc->pc_corepmcs[ri + core_iaf_ri].phw_pmc;
491 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, ri));
493 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
494 v = iaf_reload_count_to_perfctr_value(v);
496 /* Turn off fixed counters */
497 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK;
498 wrmsr(IAF_CTRL, msr);
500 wrmsr(IAF_CTR0 + ri, v & ((1ULL << core_iaf_width) - 1));
502 /* Turn on fixed counters */
503 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK;
504 wrmsr(IAF_CTRL, msr | (cc->pc_iafctrl & IAF_CTRL_MASK));
506 PMCDBG6(MDP,WRI,1, "iaf-write cpu=%d ri=%d msr=0x%x v=%jx iafctrl=%jx "
507 "pmc=%jx", cpu, ri, IAF_RI_TO_MSR(ri), v,
508 (uintmax_t) rdmsr(IAF_CTRL),
509 (uintmax_t) rdpmc(IAF_RI_TO_MSR(ri)));
516 iaf_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth)
518 struct pmc_classdep *pcd;
520 KASSERT(md != NULL, ("[iaf,%d] md is NULL", __LINE__));
522 PMCDBG0(MDP,INI,1, "iaf-initialize");
524 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF];
526 pcd->pcd_caps = IAF_PMC_CAPS;
527 pcd->pcd_class = PMC_CLASS_IAF;
529 pcd->pcd_ri = md->pmd_npmc;
530 pcd->pcd_width = pmcwidth;
532 pcd->pcd_allocate_pmc = iaf_allocate_pmc;
533 pcd->pcd_config_pmc = iaf_config_pmc;
534 pcd->pcd_describe = iaf_describe;
535 pcd->pcd_get_config = iaf_get_config;
536 pcd->pcd_get_msr = iaf_get_msr;
537 pcd->pcd_pcpu_fini = core_pcpu_noop;
538 pcd->pcd_pcpu_init = core_pcpu_noop;
539 pcd->pcd_read_pmc = iaf_read_pmc;
540 pcd->pcd_release_pmc = iaf_release_pmc;
541 pcd->pcd_start_pmc = iaf_start_pmc;
542 pcd->pcd_stop_pmc = iaf_stop_pmc;
543 pcd->pcd_write_pmc = iaf_write_pmc;
545 md->pmd_npmc += npmc;
549 * Intel programmable PMCs.
552 /* Sub fields of UMASK that this event supports. */
553 #define IAP_M_CORE (1 << 0) /* Core specificity */
554 #define IAP_M_AGENT (1 << 1) /* Agent specificity */
555 #define IAP_M_PREFETCH (1 << 2) /* Prefetch */
556 #define IAP_M_MESI (1 << 3) /* MESI */
557 #define IAP_M_SNOOPRESPONSE (1 << 4) /* Snoop response */
558 #define IAP_M_SNOOPTYPE (1 << 5) /* Snoop type */
559 #define IAP_M_TRANSITION (1 << 6) /* Transition */
561 #define IAP_F_CORE (0x3 << 14) /* Core specificity */
562 #define IAP_F_AGENT (0x1 << 13) /* Agent specificity */
563 #define IAP_F_PREFETCH (0x3 << 12) /* Prefetch */
564 #define IAP_F_MESI (0xF << 8) /* MESI */
565 #define IAP_F_SNOOPRESPONSE (0xB << 8) /* Snoop response */
566 #define IAP_F_SNOOPTYPE (0x3 << 8) /* Snoop type */
567 #define IAP_F_TRANSITION (0x1 << 12) /* Transition */
569 #define IAP_PREFETCH_RESERVED (0x2 << 12)
570 #define IAP_CORE_THIS (0x1 << 14)
571 #define IAP_CORE_ALL (0x3 << 14)
572 #define IAP_F_CMASK 0xFF000000
575 iap_perfctr_value_to_reload_count(pmc_value_t v)
578 /* If the PMC has overflowed, return a reload count of zero. */
579 if ((v & (1ULL << (core_iap_width - 1))) == 0)
581 v &= (1ULL << core_iap_width) - 1;
582 return (1ULL << core_iap_width) - v;
586 iap_reload_count_to_perfctr_value(pmc_value_t rlc)
588 return (1ULL << core_iap_width) - rlc;
592 iap_pmc_has_overflowed(int ri)
597 * We treat a Core (i.e., Intel architecture v1) PMC as has
598 * having overflowed if its MSB is zero.
601 return ((v & (1ULL << (core_iap_width - 1))) == 0);
605 iap_event_corei7_ok_on_counter(uint8_t evsel, int ri)
611 * Events valid only on counter 0, 1.
623 mask = ~0; /* Any row index is ok. */
626 return (mask & (1 << ri));
630 iap_event_westmere_ok_on_counter(uint8_t evsel, int ri)
636 * Events valid only on counter 0.
644 * Events valid only on counter 0, 1.
654 mask = ~0; /* Any row index is ok. */
657 return (mask & (1 << ri));
661 iap_event_sb_sbx_ib_ibx_ok_on_counter(uint8_t evsel, int ri)
666 /* Events valid only on counter 0. */
670 /* Events valid only on counter 1. */
674 /* Events valid only on counter 2. */
680 /* Events valid only on counter 3. */
686 mask = ~0; /* Any row index is ok. */
689 return (mask & (1 << ri));
693 iap_event_ok_on_counter(uint8_t evsel, int ri)
699 * Events valid only on counter 0.
711 * Events valid only on counter 1.
720 mask = ~0; /* Any row index is ok. */
723 return (mask & (1 << ri));
727 iap_allocate_pmc(int cpu, int ri, struct pmc *pm,
728 const struct pmc_op_pmcallocate *a)
733 const struct pmc_md_iap_op_pmcallocate *iap;
735 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
736 ("[core,%d] illegal CPU %d", __LINE__, cpu));
737 KASSERT(ri >= 0 && ri < core_iap_npmc,
738 ("[core,%d] illegal row-index value %d", __LINE__, ri));
740 /* check requested capabilities */
742 if ((IAP_PMC_CAPS & caps) != caps)
744 map = 0; /* XXX: silent GCC warning */
745 iap = &a->pm_md.pm_iap;
746 ev = IAP_EVSEL_GET(iap->pm_iap_config);
748 switch (core_cputype) {
749 case PMC_CPU_INTEL_COREI7:
750 case PMC_CPU_INTEL_NEHALEM_EX:
751 if (iap_event_corei7_ok_on_counter(ev, ri) == 0)
754 case PMC_CPU_INTEL_SKYLAKE:
755 case PMC_CPU_INTEL_SKYLAKE_XEON:
756 case PMC_CPU_INTEL_BROADWELL:
757 case PMC_CPU_INTEL_BROADWELL_XEON:
758 case PMC_CPU_INTEL_SANDYBRIDGE:
759 case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
760 case PMC_CPU_INTEL_IVYBRIDGE:
761 case PMC_CPU_INTEL_IVYBRIDGE_XEON:
762 case PMC_CPU_INTEL_HASWELL:
763 case PMC_CPU_INTEL_HASWELL_XEON:
764 if (iap_event_sb_sbx_ib_ibx_ok_on_counter(ev, ri) == 0)
767 case PMC_CPU_INTEL_WESTMERE:
768 case PMC_CPU_INTEL_WESTMERE_EX:
769 if (iap_event_westmere_ok_on_counter(ev, ri) == 0)
773 if (iap_event_ok_on_counter(ev, ri) == 0)
777 pm->pm_md.pm_iap.pm_iap_evsel = iap->pm_iap_config;
782 iap_config_pmc(int cpu, int ri, struct pmc *pm)
784 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
785 ("[core,%d] illegal CPU %d", __LINE__, cpu));
787 KASSERT(ri >= 0 && ri < core_iap_npmc,
788 ("[core,%d] illegal row-index %d", __LINE__, ri));
790 PMCDBG3(MDP,CFG,1, "iap-config cpu=%d ri=%d pm=%p", cpu, ri, pm);
792 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__,
795 core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc = pm;
801 iap_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
805 char iap_name[PMC_NAME_MAX];
807 phw = &core_pcpu[cpu]->pc_corepmcs[ri];
809 (void) snprintf(iap_name, sizeof(iap_name), "IAP-%d", ri);
810 if ((error = copystr(iap_name, pi->pm_name, PMC_NAME_MAX,
814 pi->pm_class = PMC_CLASS_IAP;
816 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
817 pi->pm_enabled = TRUE;
818 *ppmc = phw->phw_pmc;
820 pi->pm_enabled = FALSE;
828 iap_get_config(int cpu, int ri, struct pmc **ppm)
830 *ppm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc;
836 iap_get_msr(int ri, uint32_t *msr)
838 KASSERT(ri >= 0 && ri < core_iap_npmc,
839 ("[iap,%d] ri %d out of range", __LINE__, ri));
847 iap_read_pmc(int cpu, int ri, pmc_value_t *v)
852 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
853 ("[core,%d] illegal cpu value %d", __LINE__, cpu));
854 KASSERT(ri >= 0 && ri < core_iap_npmc,
855 ("[core,%d] illegal row-index %d", __LINE__, ri));
857 pm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc;
860 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu,
864 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
865 *v = iap_perfctr_value_to_reload_count(tmp);
867 *v = tmp & ((1ULL << core_iap_width) - 1);
869 PMCDBG4(MDP,REA,1, "iap-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri,
876 iap_release_pmc(int cpu, int ri, struct pmc *pm)
880 PMCDBG3(MDP,REL,1, "iap-release cpu=%d ri=%d pm=%p", cpu, ri,
883 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
884 ("[core,%d] illegal CPU value %d", __LINE__, cpu));
885 KASSERT(ri >= 0 && ri < core_iap_npmc,
886 ("[core,%d] illegal row-index %d", __LINE__, ri));
888 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc
889 == NULL, ("[core,%d] PHW pmc non-NULL", __LINE__));
895 iap_start_pmc(int cpu, int ri)
901 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
902 ("[core,%d] illegal CPU value %d", __LINE__, cpu));
903 KASSERT(ri >= 0 && ri < core_iap_npmc,
904 ("[core,%d] illegal row-index %d", __LINE__, ri));
907 pm = cc->pc_corepmcs[ri].phw_pmc;
910 ("[core,%d] starting cpu%d,ri%d with no pmc configured",
913 PMCDBG2(MDP,STA,1, "iap-start cpu=%d ri=%d", cpu, ri);
915 evsel = pm->pm_md.pm_iap.pm_iap_evsel;
917 PMCDBG4(MDP,STA,2, "iap-start/2 cpu=%d ri=%d evselmsr=0x%x evsel=0x%x",
918 cpu, ri, IAP_EVSEL0 + ri, evsel);
920 /* Event specific configuration. */
922 switch (IAP_EVSEL_GET(evsel)) {
924 wrmsr(IA_OFFCORE_RSP0, pm->pm_md.pm_iap.pm_iap_rsp);
927 wrmsr(IA_OFFCORE_RSP1, pm->pm_md.pm_iap.pm_iap_rsp);
933 wrmsr(IAP_EVSEL0 + ri, evsel | IAP_EN);
935 if (core_cputype == PMC_CPU_INTEL_CORE)
940 cc->pc_globalctrl |= (1ULL << ri);
941 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl);
942 } while (cc->pc_resync != 0);
948 iap_stop_pmc(int cpu, int ri)
954 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
955 ("[core,%d] illegal cpu value %d", __LINE__, cpu));
956 KASSERT(ri >= 0 && ri < core_iap_npmc,
957 ("[core,%d] illegal row index %d", __LINE__, ri));
960 pm = cc->pc_corepmcs[ri].phw_pmc;
963 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__,
966 PMCDBG2(MDP,STO,1, "iap-stop cpu=%d ri=%d", cpu, ri);
968 msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK;
969 wrmsr(IAP_EVSEL0 + ri, msr); /* stop hw */
971 if (core_cputype == PMC_CPU_INTEL_CORE)
977 cc->pc_globalctrl &= ~(1ULL << ri);
978 msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK;
979 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl);
980 } while (cc->pc_resync != 0);
986 iap_write_pmc(int cpu, int ri, pmc_value_t v)
991 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
992 ("[core,%d] illegal cpu value %d", __LINE__, cpu));
993 KASSERT(ri >= 0 && ri < core_iap_npmc,
994 ("[core,%d] illegal row index %d", __LINE__, ri));
997 pm = cc->pc_corepmcs[ri].phw_pmc;
1000 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__,
1003 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
1004 v = iap_reload_count_to_perfctr_value(v);
1006 v &= (1ULL << core_iap_width) - 1;
1008 PMCDBG4(MDP,WRI,1, "iap-write cpu=%d ri=%d msr=0x%x v=%jx", cpu, ri,
1012 * Write the new value to the counter (or it's alias). The
1013 * counter will be in a stopped state when the pcd_write()
1014 * entry point is called.
1016 wrmsr(core_iap_wroffset + IAP_PMC0 + ri, v);
1022 iap_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth,
1025 struct pmc_classdep *pcd;
1027 KASSERT(md != NULL, ("[iap,%d] md is NULL", __LINE__));
1029 PMCDBG0(MDP,INI,1, "iap-initialize");
1031 /* Remember the set of architectural events supported. */
1032 core_architectural_events = ~flags;
1034 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP];
1036 pcd->pcd_caps = IAP_PMC_CAPS;
1037 pcd->pcd_class = PMC_CLASS_IAP;
1038 pcd->pcd_num = npmc;
1039 pcd->pcd_ri = md->pmd_npmc;
1040 pcd->pcd_width = pmcwidth;
1042 pcd->pcd_allocate_pmc = iap_allocate_pmc;
1043 pcd->pcd_config_pmc = iap_config_pmc;
1044 pcd->pcd_describe = iap_describe;
1045 pcd->pcd_get_config = iap_get_config;
1046 pcd->pcd_get_msr = iap_get_msr;
1047 pcd->pcd_pcpu_fini = core_pcpu_fini;
1048 pcd->pcd_pcpu_init = core_pcpu_init;
1049 pcd->pcd_read_pmc = iap_read_pmc;
1050 pcd->pcd_release_pmc = iap_release_pmc;
1051 pcd->pcd_start_pmc = iap_start_pmc;
1052 pcd->pcd_stop_pmc = iap_stop_pmc;
1053 pcd->pcd_write_pmc = iap_write_pmc;
1055 md->pmd_npmc += npmc;
1059 core_intr(int cpu, struct trapframe *tf)
1063 struct core_cpu *cc;
1064 int error, found_interrupt, ri;
1067 PMCDBG3(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf,
1068 TRAPF_USERMODE(tf));
1070 found_interrupt = 0;
1071 cc = core_pcpu[cpu];
1073 for (ri = 0; ri < core_iap_npmc; ri++) {
1075 if ((pm = cc->pc_corepmcs[ri].phw_pmc) == NULL ||
1076 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
1079 if (!iap_pmc_has_overflowed(ri))
1082 found_interrupt = 1;
1084 if (pm->pm_state != PMC_STATE_RUNNING)
1087 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf,
1088 TRAPF_USERMODE(tf));
1090 v = pm->pm_sc.pm_reloadcount;
1091 v = iap_reload_count_to_perfctr_value(v);
1094 * Stop the counter, reload it but only restart it if
1095 * the PMC is not stalled.
1097 msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK;
1098 wrmsr(IAP_EVSEL0 + ri, msr);
1099 wrmsr(core_iap_wroffset + IAP_PMC0 + ri, v);
1104 wrmsr(IAP_EVSEL0 + ri, msr | (pm->pm_md.pm_iap.pm_iap_evsel |
1108 if (found_interrupt)
1109 lapic_reenable_pmc();
1111 if (found_interrupt)
1112 counter_u64_add(pmc_stats.pm_intr_processed, 1);
1114 counter_u64_add(pmc_stats.pm_intr_ignored, 1);
1116 return (found_interrupt);
1120 core2_intr(int cpu, struct trapframe *tf)
1122 int error, found_interrupt, n;
1123 uint64_t flag, intrstatus, intrenable, msr;
1125 struct core_cpu *cc;
1128 PMCDBG3(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf,
1129 TRAPF_USERMODE(tf));
1132 * The IA_GLOBAL_STATUS (MSR 0x38E) register indicates which
1133 * PMCs have a pending PMI interrupt. We take a 'snapshot' of
1134 * the current set of interrupting PMCs and process these
1135 * after stopping them.
1137 intrstatus = rdmsr(IA_GLOBAL_STATUS);
1138 intrenable = intrstatus & core_pmcmask;
1140 PMCDBG2(MDP,INT, 1, "cpu=%d intrstatus=%jx", cpu,
1141 (uintmax_t) intrstatus);
1143 found_interrupt = 0;
1144 cc = core_pcpu[cpu];
1146 KASSERT(cc != NULL, ("[core,%d] null pcpu", __LINE__));
1148 cc->pc_globalctrl &= ~intrenable;
1149 cc->pc_resync = 1; /* MSRs now potentially out of sync. */
1152 * Stop PMCs and clear overflow status bits.
1154 msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK;
1155 wrmsr(IA_GLOBAL_CTRL, msr);
1156 wrmsr(IA_GLOBAL_OVF_CTRL, intrenable |
1157 IA_GLOBAL_STATUS_FLAG_OVFBUF |
1158 IA_GLOBAL_STATUS_FLAG_CONDCHG);
1161 * Look for interrupts from fixed function PMCs.
1163 for (n = 0, flag = (1ULL << IAF_OFFSET); n < core_iaf_npmc;
1166 if ((intrstatus & flag) == 0)
1169 found_interrupt = 1;
1171 pm = cc->pc_corepmcs[n + core_iaf_ri].phw_pmc;
1172 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING ||
1173 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
1176 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf,
1177 TRAPF_USERMODE(tf));
1180 intrenable &= ~flag;
1182 v = iaf_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount);
1184 /* Reload sampling count. */
1185 wrmsr(IAF_CTR0 + n, v);
1187 PMCDBG4(MDP,INT, 1, "iaf-intr cpu=%d error=%d v=%jx(%jx)", cpu,
1188 error, (uintmax_t) v, (uintmax_t) rdpmc(IAF_RI_TO_MSR(n)));
1192 * Process interrupts from the programmable counters.
1194 for (n = 0, flag = 1; n < core_iap_npmc; n++, flag <<= 1) {
1195 if ((intrstatus & flag) == 0)
1198 found_interrupt = 1;
1200 pm = cc->pc_corepmcs[n].phw_pmc;
1201 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING ||
1202 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
1205 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf,
1206 TRAPF_USERMODE(tf));
1208 intrenable &= ~flag;
1210 v = iap_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount);
1212 PMCDBG3(MDP,INT, 1, "iap-intr cpu=%d error=%d v=%jx", cpu, error,
1215 /* Reload sampling count. */
1216 wrmsr(core_iap_wroffset + IAP_PMC0 + n, v);
1220 * Reenable all non-stalled PMCs.
1222 PMCDBG2(MDP,INT, 1, "cpu=%d intrenable=%jx", cpu,
1223 (uintmax_t) intrenable);
1225 cc->pc_globalctrl |= intrenable;
1227 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl & IA_GLOBAL_CTRL_MASK);
1229 PMCDBG5(MDP,INT, 1, "cpu=%d fixedctrl=%jx globalctrl=%jx status=%jx "
1230 "ovf=%jx", cpu, (uintmax_t) rdmsr(IAF_CTRL),
1231 (uintmax_t) rdmsr(IA_GLOBAL_CTRL),
1232 (uintmax_t) rdmsr(IA_GLOBAL_STATUS),
1233 (uintmax_t) rdmsr(IA_GLOBAL_OVF_CTRL));
1235 if (found_interrupt)
1236 lapic_reenable_pmc();
1238 if (found_interrupt)
1239 counter_u64_add(pmc_stats.pm_intr_processed, 1);
1241 counter_u64_add(pmc_stats.pm_intr_ignored, 1);
1243 return (found_interrupt);
1247 pmc_core_initialize(struct pmc_mdep *md, int maxcpu, int version_override)
1249 int cpuid[CORE_CPUID_REQUEST_SIZE];
1250 int ipa_version, flags, nflags;
1252 do_cpuid(CORE_CPUID_REQUEST, cpuid);
1254 ipa_version = (version_override > 0) ? version_override :
1255 cpuid[CORE_CPUID_EAX] & 0xFF;
1256 core_cputype = md->pmd_cputype;
1258 PMCDBG3(MDP,INI,1,"core-init cputype=%d ncpu=%d ipa-version=%d",
1259 core_cputype, maxcpu, ipa_version);
1261 if (ipa_version < 1 || ipa_version > 4 ||
1262 (core_cputype != PMC_CPU_INTEL_CORE && ipa_version == 1)) {
1263 /* Unknown PMC architecture. */
1264 printf("hwpc_core: unknown PMC architecture: %d\n",
1266 return (EPROGMISMATCH);
1269 core_iap_wroffset = 0;
1270 if (cpu_feature2 & CPUID2_PDCM) {
1271 if (rdmsr(IA32_PERF_CAPABILITIES) & PERFCAP_FW_WRITE) {
1272 PMCDBG0(MDP, INI, 1,
1273 "core-init full-width write supported");
1274 core_iap_wroffset = IAP_A_PMC0 - IAP_PMC0;
1276 PMCDBG0(MDP, INI, 1,
1277 "core-init full-width write NOT supported");
1279 PMCDBG0(MDP, INI, 1, "core-init pdcm not supported");
1284 * Initialize programmable counters.
1286 core_iap_npmc = (cpuid[CORE_CPUID_EAX] >> 8) & 0xFF;
1287 core_iap_width = (cpuid[CORE_CPUID_EAX] >> 16) & 0xFF;
1289 core_pmcmask |= ((1ULL << core_iap_npmc) - 1);
1291 nflags = (cpuid[CORE_CPUID_EAX] >> 24) & 0xFF;
1292 flags = cpuid[CORE_CPUID_EBX] & ((1 << nflags) - 1);
1294 iap_initialize(md, maxcpu, core_iap_npmc, core_iap_width, flags);
1297 * Initialize fixed function counters, if present.
1299 if (core_cputype != PMC_CPU_INTEL_CORE) {
1300 core_iaf_ri = core_iap_npmc;
1301 core_iaf_npmc = cpuid[CORE_CPUID_EDX] & 0x1F;
1302 core_iaf_width = (cpuid[CORE_CPUID_EDX] >> 5) & 0xFF;
1304 iaf_initialize(md, maxcpu, core_iaf_npmc, core_iaf_width);
1305 core_pmcmask |= ((1ULL << core_iaf_npmc) - 1) << IAF_OFFSET;
1308 PMCDBG2(MDP,INI,1,"core-init pmcmask=0x%jx iafri=%d", core_pmcmask,
1311 core_pcpu = malloc(sizeof(*core_pcpu) * maxcpu, M_PMC,
1315 * Choose the appropriate interrupt handler.
1317 if (ipa_version == 1)
1318 md->pmd_intr = core_intr;
1320 md->pmd_intr = core2_intr;
1322 md->pmd_pcpu_fini = NULL;
1323 md->pmd_pcpu_init = NULL;
1329 pmc_core_finalize(struct pmc_mdep *md)
1331 PMCDBG0(MDP,INI,1, "core-finalize");
1333 free(core_pcpu, M_PMC);