sys/dev/hwpmc/hwpmc_e500.c

   1 /*-
   2  * Copyright (c) 2015 Justin Hibbits
   3  * Copyright (c) 2005, Joseph Koshy
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  *
  27  */
  28
  29 #include <sys/cdefs.h>
  30 __FBSDID("$FreeBSD$");
  31
  32 #include <sys/param.h>
  33 #include <sys/pmc.h>
  34 #include <sys/pmckern.h>
  35 #include <sys/systm.h>
  36
  37 #include <machine/pmc_mdep.h>
  38 #include <machine/cpu.h>
  39
  40 #include <ddb/ddb.h>
  41
  42 #include "hwpmc_powerpc.h"
  43
  44 #define POWERPC_PMC_CAPS        (PMC_CAP_INTERRUPT | PMC_CAP_USER |     \
  45                                  PMC_CAP_SYSTEM | PMC_CAP_EDGE |        \
  46                                  PMC_CAP_THRESHOLD | PMC_CAP_READ |     \
  47                                  PMC_CAP_WRITE | PMC_CAP_INVERT |       \
  48                                  PMC_CAP_QUALIFIER)
  49
  50 #define E500_PMC_HAS_OVERFLOWED(x) (e500_pmcn_read(x) & (0x1 << 31))
  51
  52 struct e500_event_code_map {
  53         enum pmc_event  pe_ev;       /* enum value */
  54         uint8_t         pe_counter_mask;  /* Which counter this can be counted in. */
  55         uint8_t         pe_code;     /* numeric code */
  56         uint8_t         pe_cpu;      /* e500 core (v1,v2,mc), mask */
  57 };
  58
  59 #define E500_MAX_PMCS   4
  60 #define PMC_PPC_MASK0   0
  61 #define PMC_PPC_MASK1   1
  62 #define PMC_PPC_MASK2   2
  63 #define PMC_PPC_MASK3   3
  64 #define PMC_PPC_MASK_ALL        0x0f
  65 #define PMC_PPC_E500V1          1
  66 #define PMC_PPC_E500V2          2
  67 #define PMC_PPC_E500MC          4
  68 #define PMC_PPC_E500_ANY        7
  69 #define PMC_E500_EVENT(id, mask, number, core) \
  70         [PMC_EV_E500_##id - PMC_EV_E500_FIRST] = \
  71             { .pe_ev = PMC_EV_E500_##id, .pe_counter_mask = mask, \
  72               .pe_code = number, .pe_cpu = core }
  73 #define PMC_E500MC_ONLY(id, number) \
  74         PMC_E500_EVENT(id, PMC_PPC_MASK_ALL, number, PMC_PPC_E500MC)
  75 #define PMC_E500_COMMON(id, number) \
  76         PMC_E500_EVENT(id, PMC_PPC_MASK_ALL, number, PMC_PPC_E500_ANY)
  77
  78 static struct e500_event_code_map e500_event_codes[] = {
  79         PMC_E500_COMMON(CYCLES, 1),
  80         PMC_E500_COMMON(INSTR_COMPLETED, 2),
  81         PMC_E500_COMMON(UOPS_COMPLETED, 3),
  82         PMC_E500_COMMON(INSTR_FETCHED, 4),
  83         PMC_E500_COMMON(UOPS_DECODED, 5),
  84         PMC_E500_COMMON(PM_EVENT_TRANSITIONS, 6),
  85         PMC_E500_COMMON(PM_EVENT_CYCLES, 7),
  86         PMC_E500_COMMON(BRANCH_INSTRS_COMPLETED, 8),
  87         PMC_E500_COMMON(LOAD_UOPS_COMPLETED, 9),
  88         PMC_E500_COMMON(STORE_UOPS_COMPLETED, 10),
  89         PMC_E500_COMMON(CQ_REDIRECTS, 11),
  90         PMC_E500_COMMON(BRANCHES_FINISHED, 12),
  91         PMC_E500_COMMON(TAKEN_BRANCHES_FINISHED, 13),
  92         PMC_E500_COMMON(FINISHED_UNCOND_BRANCHES_MISS_BTB, 14),
  93         PMC_E500_COMMON(BRANCH_MISPRED, 15),
  94         PMC_E500_COMMON(BTB_BRANCH_MISPRED_FROM_DIRECTION, 16),
  95         PMC_E500_COMMON(BTB_HITS_PSEUDO_HITS, 17),
  96         PMC_E500_COMMON(CYCLES_DECODE_STALLED, 18),
  97         PMC_E500_COMMON(CYCLES_ISSUE_STALLED, 19),
  98         PMC_E500_COMMON(CYCLES_BRANCH_ISSUE_STALLED, 20),
  99         PMC_E500_COMMON(CYCLES_SU1_SCHED_STALLED, 21),
 100         PMC_E500_COMMON(CYCLES_SU2_SCHED_STALLED, 22),
 101         PMC_E500_COMMON(CYCLES_MU_SCHED_STALLED, 23),
 102         PMC_E500_COMMON(CYCLES_LRU_SCHED_STALLED, 24),
 103         PMC_E500_COMMON(CYCLES_BU_SCHED_STALLED, 25),
 104         PMC_E500_COMMON(TOTAL_TRANSLATED, 26),
 105         PMC_E500_COMMON(LOADS_TRANSLATED, 27),
 106         PMC_E500_COMMON(STORES_TRANSLATED, 28),
 107         PMC_E500_COMMON(TOUCHES_TRANSLATED, 29),
 108         PMC_E500_COMMON(CACHEOPS_TRANSLATED, 30),
 109         PMC_E500_COMMON(CACHE_INHIBITED_ACCESS_TRANSLATED, 31),
 110         PMC_E500_COMMON(GUARDED_LOADS_TRANSLATED, 32),
 111         PMC_E500_COMMON(WRITE_THROUGH_STORES_TRANSLATED, 33),
 112         PMC_E500_COMMON(MISALIGNED_LOAD_STORE_ACCESS_TRANSLATED, 34),
 113         PMC_E500_COMMON(TOTAL_ALLOCATED_TO_DLFB, 35),
 114         PMC_E500_COMMON(LOADS_TRANSLATED_ALLOCATED_TO_DLFB, 36),
 115         PMC_E500_COMMON(STORES_COMPLETED_ALLOCATED_TO_DLFB, 37),
 116         PMC_E500_COMMON(TOUCHES_TRANSLATED_ALLOCATED_TO_DLFB, 38),
 117         PMC_E500_COMMON(STORES_COMPLETED, 39),
 118         PMC_E500_COMMON(DATA_L1_CACHE_LOCKS, 40),
 119         PMC_E500_COMMON(DATA_L1_CACHE_RELOADS, 41),
 120         PMC_E500_COMMON(DATA_L1_CACHE_CASTOUTS, 42),
 121         PMC_E500_COMMON(LOAD_MISS_DLFB_FULL, 43),
 122         PMC_E500_COMMON(LOAD_MISS_LDQ_FULL, 44),
 123         PMC_E500_COMMON(LOAD_GUARDED_MISS, 45),
 124         PMC_E500_COMMON(STORE_TRANSLATE_WHEN_QUEUE_FULL, 46),
 125         PMC_E500_COMMON(ADDRESS_COLLISION, 47),
 126         PMC_E500_COMMON(DATA_MMU_MISS, 48),
 127         PMC_E500_COMMON(DATA_MMU_BUSY, 49),
 128         PMC_E500_COMMON(PART2_MISALIGNED_CACHE_ACCESS, 50),
 129         PMC_E500_COMMON(LOAD_MISS_DLFB_FULL_CYCLES, 51),
 130         PMC_E500_COMMON(LOAD_MISS_LDQ_FULL_CYCLES, 52),
 131         PMC_E500_COMMON(LOAD_GUARDED_MISS_CYCLES, 53),
 132         PMC_E500_COMMON(STORE_TRANSLATE_WHEN_QUEUE_FULL_CYCLES, 54),
 133         PMC_E500_COMMON(ADDRESS_COLLISION_CYCLES, 55),
 134         PMC_E500_COMMON(DATA_MMU_MISS_CYCLES, 56),
 135         PMC_E500_COMMON(DATA_MMU_BUSY_CYCLES, 57),
 136         PMC_E500_COMMON(PART2_MISALIGNED_CACHE_ACCESS_CYCLES, 58),
 137         PMC_E500_COMMON(INSTR_L1_CACHE_LOCKS, 59),
 138         PMC_E500_COMMON(INSTR_L1_CACHE_RELOADS, 60),
 139         PMC_E500_COMMON(INSTR_L1_CACHE_FETCHES, 61),
 140         PMC_E500_COMMON(INSTR_MMU_TLB4K_RELOADS, 62),
 141         PMC_E500_COMMON(INSTR_MMU_VSP_RELOADS, 63),
 142         PMC_E500_COMMON(DATA_MMU_TLB4K_RELOADS, 64),
 143         PMC_E500_COMMON(DATA_MMU_VSP_RELOADS, 65),
 144         PMC_E500_COMMON(L2MMU_MISSES, 66),
 145         PMC_E500_COMMON(BIU_MASTER_REQUESTS, 67),
 146         PMC_E500_COMMON(BIU_MASTER_INSTR_SIDE_REQUESTS, 68),
 147         PMC_E500_COMMON(BIU_MASTER_DATA_SIDE_REQUESTS, 69),
 148         PMC_E500_COMMON(BIU_MASTER_DATA_SIDE_CASTOUT_REQUESTS, 70),
 149         PMC_E500_COMMON(BIU_MASTER_RETRIES, 71),
 150         PMC_E500_COMMON(SNOOP_REQUESTS, 72),
 151         PMC_E500_COMMON(SNOOP_HITS, 73),
 152         PMC_E500_COMMON(SNOOP_PUSHES, 74),
 153         PMC_E500_COMMON(SNOOP_RETRIES, 75),
 154         PMC_E500_EVENT(DLFB_LOAD_MISS_CYCLES, PMC_PPC_MASK0|PMC_PPC_MASK1,
 155             76, PMC_PPC_E500_ANY),
 156         PMC_E500_EVENT(ILFB_FETCH_MISS_CYCLES, PMC_PPC_MASK0|PMC_PPC_MASK1,
 157             77, PMC_PPC_E500_ANY),
 158         PMC_E500_EVENT(EXT_INPU_INTR_LATENCY_CYCLES, PMC_PPC_MASK0|PMC_PPC_MASK1,
 159             78, PMC_PPC_E500_ANY),
 160         PMC_E500_EVENT(CRIT_INPUT_INTR_LATENCY_CYCLES, PMC_PPC_MASK0|PMC_PPC_MASK1,
 161             79, PMC_PPC_E500_ANY),
 162         PMC_E500_EVENT(EXT_INPUT_INTR_PENDING_LATENCY_CYCLES,
 163             PMC_PPC_MASK0|PMC_PPC_MASK1, 80, PMC_PPC_E500_ANY),
 164         PMC_E500_EVENT(CRIT_INPUT_INTR_PENDING_LATENCY_CYCLES,
 165             PMC_PPC_MASK0|PMC_PPC_MASK1, 81, PMC_PPC_E500_ANY),
 166         PMC_E500_COMMON(PMC0_OVERFLOW, 82),
 167         PMC_E500_COMMON(PMC1_OVERFLOW, 83),
 168         PMC_E500_COMMON(PMC2_OVERFLOW, 84),
 169         PMC_E500_COMMON(PMC3_OVERFLOW, 85),
 170         PMC_E500_COMMON(INTERRUPTS_TAKEN, 86),
 171         PMC_E500_COMMON(EXT_INPUT_INTR_TAKEN, 87),
 172         PMC_E500_COMMON(CRIT_INPUT_INTR_TAKEN, 88),
 173         PMC_E500_COMMON(SYSCALL_TRAP_INTR, 89),
 174         PMC_E500_EVENT(TLB_BIT_TRANSITIONS, PMC_PPC_MASK_ALL, 90,
 175             PMC_PPC_E500V2 | PMC_PPC_E500MC),
 176         PMC_E500MC_ONLY(L2_LINEFILL_BUFFER, 91),
 177         PMC_E500MC_ONLY(LV2_VS, 92),
 178         PMC_E500MC_ONLY(CASTOUTS_RELEASED, 93),
 179         PMC_E500MC_ONLY(INTV_ALLOCATIONS, 94),
 180         PMC_E500MC_ONLY(DLFB_RETRIES_TO_MBAR, 95),
 181         PMC_E500MC_ONLY(STORE_RETRIES, 96),
 182         PMC_E500MC_ONLY(STASH_L1_HITS, 97),
 183         PMC_E500MC_ONLY(STASH_L2_HITS, 98),
 184         PMC_E500MC_ONLY(STASH_BUSY_1, 99),
 185         PMC_E500MC_ONLY(STASH_BUSY_2, 100),
 186         PMC_E500MC_ONLY(STASH_BUSY_3, 101),
 187         PMC_E500MC_ONLY(STASH_HITS, 102),
 188         PMC_E500MC_ONLY(STASH_HIT_DLFB, 103),
 189         PMC_E500MC_ONLY(STASH_REQUESTS, 106),
 190         PMC_E500MC_ONLY(STASH_REQUESTS_L1, 107),
 191         PMC_E500MC_ONLY(STASH_REQUESTS_L2, 108),
 192         PMC_E500MC_ONLY(STALLS_NO_CAQ_OR_COB, 109),
 193         PMC_E500MC_ONLY(L2_CACHE_ACCESSES, 110),
 194         PMC_E500MC_ONLY(L2_HIT_CACHE_ACCESSES, 111),
 195         PMC_E500MC_ONLY(L2_CACHE_DATA_ACCESSES, 112),
 196         PMC_E500MC_ONLY(L2_CACHE_DATA_HITS, 113),
 197         PMC_E500MC_ONLY(L2_CACHE_INSTR_ACCESSES, 114),
 198         PMC_E500MC_ONLY(L2_CACHE_INSTR_HITS, 115),
 199         PMC_E500MC_ONLY(L2_CACHE_ALLOCATIONS, 116),
 200         PMC_E500MC_ONLY(L2_CACHE_DATA_ALLOCATIONS, 117),
 201         PMC_E500MC_ONLY(L2_CACHE_DIRTY_DATA_ALLOCATIONS, 118),
 202         PMC_E500MC_ONLY(L2_CACHE_INSTR_ALLOCATIONS, 119),
 203         PMC_E500MC_ONLY(L2_CACHE_UPDATES, 120),
 204         PMC_E500MC_ONLY(L2_CACHE_CLEAN_UPDATES, 121),
 205         PMC_E500MC_ONLY(L2_CACHE_DIRTY_UPDATES, 122),
 206         PMC_E500MC_ONLY(L2_CACHE_CLEAN_REDUNDANT_UPDATES, 123),
 207         PMC_E500MC_ONLY(L2_CACHE_DIRTY_REDUNDANT_UPDATES, 124),
 208         PMC_E500MC_ONLY(L2_CACHE_LOCKS, 125),
 209         PMC_E500MC_ONLY(L2_CACHE_CASTOUTS, 126),
 210         PMC_E500MC_ONLY(L2_CACHE_DATA_DIRTY_HITS, 127),
 211         PMC_E500MC_ONLY(INSTR_LFB_WENT_HIGH_PRIORITY, 128),
 212         PMC_E500MC_ONLY(SNOOP_THROTTLING_TURNED_ON, 129),
 213         PMC_E500MC_ONLY(L2_CLEAN_LINE_INVALIDATIONS, 130),
 214         PMC_E500MC_ONLY(L2_INCOHERENT_LINE_INVALIDATIONS, 131),
 215         PMC_E500MC_ONLY(L2_COHERENT_LINE_INVALIDATIONS, 132),
 216         PMC_E500MC_ONLY(COHERENT_LOOKUP_MISS_DUE_TO_VALID_BUT_INCOHERENT_MATCHES, 133),
 217         PMC_E500MC_ONLY(IAC1S_DETECTED, 140),
 218         PMC_E500MC_ONLY(IAC2S_DETECTED, 141),
 219         PMC_E500MC_ONLY(DAC1S_DTECTED, 144),
 220         PMC_E500MC_ONLY(DAC2S_DTECTED, 145),
 221         PMC_E500MC_ONLY(DVT0_DETECTED, 148),
 222         PMC_E500MC_ONLY(DVT1_DETECTED, 149),
 223         PMC_E500MC_ONLY(DVT2_DETECTED, 150),
 224         PMC_E500MC_ONLY(DVT3_DETECTED, 151),
 225         PMC_E500MC_ONLY(DVT4_DETECTED, 152),
 226         PMC_E500MC_ONLY(DVT5_DETECTED, 153),
 227         PMC_E500MC_ONLY(DVT6_DETECTED, 154),
 228         PMC_E500MC_ONLY(DVT7_DETECTED, 155),
 229         PMC_E500MC_ONLY(CYCLES_COMPLETION_STALLED_NEXUS_FIFO_FULL, 156),
 230         PMC_E500MC_ONLY(FPU_DOUBLE_PUMP, 160),
 231         PMC_E500MC_ONLY(FPU_FINISH, 161),
 232         PMC_E500MC_ONLY(FPU_DIVIDE_CYCLES, 162),
 233         PMC_E500MC_ONLY(FPU_DENORM_INPUT_CYCLES, 163),
 234         PMC_E500MC_ONLY(FPU_RESULT_STALL_CYCLES, 164),
 235         PMC_E500MC_ONLY(FPU_FPSCR_FULL_STALL, 165),
 236         PMC_E500MC_ONLY(FPU_PIPE_SYNC_STALLS, 166),
 237         PMC_E500MC_ONLY(FPU_INPUT_DATA_STALLS, 167),
 238         PMC_E500MC_ONLY(DECORATED_LOADS, 176),
 239         PMC_E500MC_ONLY(DECORATED_STORES, 177),
 240         PMC_E500MC_ONLY(LOAD_RETRIES, 178),
 241         PMC_E500MC_ONLY(STWCX_SUCCESSES, 179),
 242         PMC_E500MC_ONLY(STWCX_FAILURES, 180),
 243 };
 244
 245 const size_t e500_event_codes_size =
 246         sizeof(e500_event_codes) / sizeof(e500_event_codes[0]);
 247
 248 static pmc_value_t
 249 e500_pmcn_read(unsigned int pmc)
 250 {
 251         switch (pmc) {
 252                 case 0:
 253                         return mfpmr(PMR_PMC0);
 254                         break;
 255                 case 1:
 256                         return mfpmr(PMR_PMC1);
 257                         break;
 258                 case 2:
 259                         return mfpmr(PMR_PMC2);
 260                         break;
 261                 case 3:
 262                         return mfpmr(PMR_PMC3);
 263                         break;
 264                 default:
 265                         panic("Invalid PMC number: %d\n", pmc);
 266         }
 267 }
 268
 269 static void
 270 e500_pmcn_write(unsigned int pmc, uint32_t val)
 271 {
 272         switch (pmc) {
 273                 case 0:
 274                         mtpmr(PMR_PMC0, val);
 275                         break;
 276                 case 1:
 277                         mtpmr(PMR_PMC1, val);
 278                         break;
 279                 case 2:
 280                         mtpmr(PMR_PMC2, val);
 281                         break;
 282                 case 3:
 283                         mtpmr(PMR_PMC3, val);
 284                         break;
 285                 default:
 286                         panic("Invalid PMC number: %d\n", pmc);
 287         }
 288 }
 289
 290 static int
 291 e500_read_pmc(int cpu, int ri, pmc_value_t *v)
 292 {
 293         struct pmc *pm;
 294         pmc_value_t tmp;
 295
 296         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 297             ("[powerpc,%d] illegal CPU value %d", __LINE__, cpu));
 298         KASSERT(ri >= 0 && ri < E500_MAX_PMCS,
 299             ("[powerpc,%d] illegal row index %d", __LINE__, ri));
 300
 301         pm  = powerpc_pcpu[cpu]->pc_ppcpmcs[ri].phw_pmc;
 302         KASSERT(pm,
 303             ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu,
 304                 ri));
 305
 306         tmp = e500_pmcn_read(ri);
 307         PMCDBG2(MDP,REA,2,"ppc-read id=%d -> %jd", ri, tmp);
 308         if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
 309                 *v = POWERPC_PERFCTR_VALUE_TO_RELOAD_COUNT(tmp);
 310         else
 311                 *v = tmp;
 312
 313         return 0;
 314 }
 315
 316 static int
 317 e500_write_pmc(int cpu, int ri, pmc_value_t v)
 318 {
 319         struct pmc *pm;
 320
 321         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 322             ("[powerpc,%d] illegal CPU value %d", __LINE__, cpu));
 323         KASSERT(ri >= 0 && ri < E500_MAX_PMCS,
 324             ("[powerpc,%d] illegal row-index %d", __LINE__, ri));
 325
 326         pm  = powerpc_pcpu[cpu]->pc_ppcpmcs[ri].phw_pmc;
 327
 328         if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
 329                 v = POWERPC_RELOAD_COUNT_TO_PERFCTR_VALUE(v);
 330
 331         PMCDBG3(MDP,WRI,1,"powerpc-write cpu=%d ri=%d v=%jx", cpu, ri, v);
 332
 333         e500_pmcn_write(ri, v);
 334
 335         return 0;
 336 }
 337
 338 static int
 339 e500_config_pmc(int cpu, int ri, struct pmc *pm)
 340 {
 341         struct pmc_hw *phw;
 342
 343         PMCDBG3(MDP,CFG,1, "cpu=%d ri=%d pm=%p", cpu, ri, pm);
 344
 345         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 346             ("[powerpc,%d] illegal CPU value %d", __LINE__, cpu));
 347         KASSERT(ri >= 0 && ri < E500_MAX_PMCS,
 348             ("[powerpc,%d] illegal row-index %d", __LINE__, ri));
 349
 350         phw = &powerpc_pcpu[cpu]->pc_ppcpmcs[ri];
 351
 352         KASSERT(pm == NULL || phw->phw_pmc == NULL,
 353             ("[powerpc,%d] pm=%p phw->pm=%p hwpmc not unconfigured",
 354             __LINE__, pm, phw->phw_pmc));
 355
 356         phw->phw_pmc = pm;
 357
 358         return 0;
 359 }
 360
 361 static int
 362 e500_start_pmc(int cpu, int ri)
 363 {
 364         uint32_t config;
 365         struct pmc *pm;
 366         struct pmc_hw *phw;
 367
 368         phw    = &powerpc_pcpu[cpu]->pc_ppcpmcs[ri];
 369         pm     = phw->phw_pmc;
 370         config = pm->pm_md.pm_powerpc.pm_powerpc_evsel;
 371
 372         if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
 373                 config |= PMLCax_CE;
 374
 375         /* Enable the PMC. */
 376         switch (ri) {
 377         case 0:
 378                 mtpmr(PMR_PMLCa0, config);
 379                 break;
 380         case 1:
 381                 mtpmr(PMR_PMLCa1, config);
 382                 break;
 383         case 2:
 384                 mtpmr(PMR_PMLCa2, config);
 385                 break;
 386         case 3:
 387                 mtpmr(PMR_PMLCa3, config);
 388                 break;
 389         default:
 390                 break;
 391         }
 392
 393         return 0;
 394 }
 395
 396 static int
 397 e500_stop_pmc(int cpu, int ri)
 398 {
 399         struct pmc *pm;
 400         struct pmc_hw *phw;
 401         register_t pmc_pmlc;
 402
 403         phw    = &powerpc_pcpu[cpu]->pc_ppcpmcs[ri];
 404         pm     = phw->phw_pmc;
 405
 406         /*
 407          * Disable the PMCs.
 408          */
 409         switch (ri) {
 410         case 0:
 411                 pmc_pmlc = mfpmr(PMR_PMLCa0);
 412                 pmc_pmlc |= PMLCax_FC;
 413                 mtpmr(PMR_PMLCa0, pmc_pmlc);
 414                 break;
 415         case 1:
 416                 pmc_pmlc = mfpmr(PMR_PMLCa1);
 417                 pmc_pmlc |= PMLCax_FC;
 418                 mtpmr(PMR_PMLCa1, pmc_pmlc);
 419                 break;
 420         case 2:
 421                 pmc_pmlc = mfpmr(PMR_PMLCa2);
 422                 pmc_pmlc |= PMLCax_FC;
 423                 mtpmr(PMR_PMLCa2, pmc_pmlc);
 424                 break;
 425         case 3:
 426                 pmc_pmlc = mfpmr(PMR_PMLCa3);
 427                 pmc_pmlc |= PMLCax_FC;
 428                 mtpmr(PMR_PMLCa3, pmc_pmlc);
 429                 break;
 430         default:
 431                 break;
 432         }
 433         return 0;
 434 }
 435
 436 static int
 437 e500_pcpu_init(struct pmc_mdep *md, int cpu)
 438 {
 439         int first_ri, i;
 440         struct pmc_cpu *pc;
 441         struct powerpc_cpu *pac;
 442         struct pmc_hw  *phw;
 443
 444         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 445             ("[powerpc,%d] wrong cpu number %d", __LINE__, cpu));
 446         PMCDBG1(MDP,INI,1,"powerpc-init cpu=%d", cpu);
 447
 448         /* Freeze all counters. */
 449         mtpmr(PMR_PMGC0, PMGC_FAC | PMGC_PMIE | PMGC_FCECE);
 450
 451         powerpc_pcpu[cpu] = pac = malloc(sizeof(struct powerpc_cpu), M_PMC,
 452             M_WAITOK|M_ZERO);
 453         pac->pc_ppcpmcs = malloc(sizeof(struct pmc_hw) * E500_MAX_PMCS,
 454             M_PMC, M_WAITOK|M_ZERO);
 455         pac->pc_class = PMC_CLASS_E500;
 456         pc = pmc_pcpu[cpu];
 457         first_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_POWERPC].pcd_ri;
 458         KASSERT(pc != NULL, ("[powerpc,%d] NULL per-cpu pointer", __LINE__));
 459
 460         for (i = 0, phw = pac->pc_ppcpmcs; i < E500_MAX_PMCS; i++, phw++) {
 461                 phw->phw_state    = PMC_PHW_FLAG_IS_ENABLED |
 462                     PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(i);
 463                 phw->phw_pmc      = NULL;
 464                 pc->pc_hwpmcs[i + first_ri] = phw;
 465
 466                 /* Initialize the PMC to stopped */
 467                 e500_stop_pmc(cpu, i);
 468         }
 469         /* Unfreeze global register. */
 470         mtpmr(PMR_PMGC0, PMGC_PMIE | PMGC_FCECE);
 471
 472         return 0;
 473 }
 474
 475 static int
 476 e500_pcpu_fini(struct pmc_mdep *md, int cpu)
 477 {
 478         uint32_t pmgc0 = mfpmr(PMR_PMGC0);
 479
 480         pmgc0 |= PMGC_FAC;
 481         mtpmr(PMR_PMGC0, pmgc0);
 482         mtmsr(mfmsr() & ~PSL_PMM);
 483
 484         free(powerpc_pcpu[cpu]->pc_ppcpmcs, M_PMC);
 485         free(powerpc_pcpu[cpu], M_PMC);
 486
 487         return 0;
 488 }
 489
 490 static int
 491 e500_allocate_pmc(int cpu, int ri, struct pmc *pm,
 492   const struct pmc_op_pmcallocate *a)
 493 {
 494         enum pmc_event pe;
 495         uint32_t caps, config, counter;
 496         struct e500_event_code_map *ev;
 497         uint16_t vers;
 498         uint8_t pe_cpu_mask;
 499
 500         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 501             ("[powerpc,%d] illegal CPU value %d", __LINE__, cpu));
 502         KASSERT(ri >= 0 && ri < E500_MAX_PMCS,
 503             ("[powerpc,%d] illegal row index %d", __LINE__, ri));
 504
 505         caps = a->pm_caps;
 506
 507         pe = a->pm_ev;
 508         config = PMLCax_FCS | PMLCax_FCU |
 509             PMLCax_FCM1 | PMLCax_FCM1;
 510
 511         if (pe < PMC_EV_E500_FIRST || pe > PMC_EV_E500_LAST)
 512                 return (EINVAL);
 513
 514         ev = &e500_event_codes[pe-PMC_EV_E500_FIRST];
 515         if (ev->pe_code == 0)
 516                 return (EINVAL);
 517
 518         vers = mfpvr() >> 16;
 519         switch (vers) {
 520         case FSL_E500v1:
 521                 pe_cpu_mask = ev->pe_cpu & PMC_PPC_E500V1;
 522                 break;
 523         case FSL_E500v2:
 524                 pe_cpu_mask = ev->pe_cpu & PMC_PPC_E500V2;
 525                 break;
 526         case FSL_E500mc:
 527         case FSL_E5500:
 528                 pe_cpu_mask = ev->pe_cpu & PMC_PPC_E500MC;
 529                 break;
 530         }
 531         if (pe_cpu_mask == 0)
 532                 return (EINVAL);
 533
 534         config |= PMLCax_EVENT(ev->pe_code);
 535         counter =  ev->pe_counter_mask;
 536         if ((counter & (1 << ri)) == 0)
 537                 return (EINVAL);
 538
 539         if (caps & PMC_CAP_SYSTEM)
 540                 config &= ~PMLCax_FCS;
 541         if (caps & PMC_CAP_USER)
 542                 config &= ~PMLCax_FCU;
 543         if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0)
 544                 config &= ~(PMLCax_FCS|PMLCax_FCU);
 545
 546         pm->pm_md.pm_powerpc.pm_powerpc_evsel = config;
 547
 548         PMCDBG2(MDP,ALL,2,"powerpc-allocate ri=%d -> config=0x%x", ri, config);
 549
 550         return 0;
 551 }
 552
 553 static int
 554 e500_release_pmc(int cpu, int ri, struct pmc *pmc)
 555 {
 556         struct pmc_hw *phw;
 557
 558         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 559             ("[powerpc,%d] illegal CPU value %d", __LINE__, cpu));
 560         KASSERT(ri >= 0 && ri < E500_MAX_PMCS,
 561             ("[powerpc,%d] illegal row-index %d", __LINE__, ri));
 562
 563         phw = &powerpc_pcpu[cpu]->pc_ppcpmcs[ri];
 564         KASSERT(phw->phw_pmc == NULL,
 565             ("[powerpc,%d] PHW pmc %p non-NULL", __LINE__, phw->phw_pmc));
 566
 567         return 0;
 568 }
 569
 570 static int
 571 e500_intr(int cpu, struct trapframe *tf)
 572 {
 573         int i, error, retval;
 574         uint32_t config;
 575         struct pmc *pm;
 576         struct powerpc_cpu *pac;
 577
 578         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 579             ("[powerpc,%d] out of range CPU %d", __LINE__, cpu));
 580
 581         PMCDBG3(MDP,INT,1, "cpu=%d tf=%p um=%d", cpu, (void *) tf,
 582             TRAPF_USERMODE(tf));
 583
 584         retval = 0;
 585
 586         pac = powerpc_pcpu[cpu];
 587
 588         config  = mfpmr(PMR_PMGC0) & ~PMGC_FAC;
 589
 590         /*
 591          * look for all PMCs that have interrupted:
 592          * - look for a running, sampling PMC which has overflowed
 593          *   and which has a valid 'struct pmc' association
 594          *
 595          * If found, we call a helper to process the interrupt.
 596          */
 597
 598         for (i = 0; i < E500_MAX_PMCS; i++) {
 599                 if ((pm = pac->pc_ppcpmcs[i].phw_pmc) == NULL ||
 600                     !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) {
 601                         continue;
 602                 }
 603
 604                 if (!E500_PMC_HAS_OVERFLOWED(i))
 605                         continue;
 606
 607                 retval = 1;     /* Found an interrupting PMC. */
 608
 609                 if (pm->pm_state != PMC_STATE_RUNNING)
 610                         continue;
 611
 612                 /* Stop the counter if logging fails. */
 613                 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf,
 614                     TRAPF_USERMODE(tf));
 615                 if (error != 0)
 616                         e500_stop_pmc(cpu, i);
 617
 618                 /* reload count. */
 619                 e500_write_pmc(cpu, i, pm->pm_sc.pm_reloadcount);
 620         }
 621
 622         atomic_add_int(retval ? &pmc_stats.pm_intr_processed :
 623             &pmc_stats.pm_intr_ignored, 1);
 624
 625         /* Re-enable PERF exceptions. */
 626         if (retval)
 627                 mtpmr(PMR_PMGC0, config | PMGC_PMIE);
 628
 629         return (retval);
 630 }
 631
 632 int
 633 pmc_e500_initialize(struct pmc_mdep *pmc_mdep)
 634 {
 635         struct pmc_classdep *pcd;
 636
 637         pmc_mdep->pmd_cputype = PMC_CPU_PPC_E500;
 638
 639         pcd = &pmc_mdep->pmd_classdep[PMC_MDEP_CLASS_INDEX_POWERPC];
 640         pcd->pcd_caps  = POWERPC_PMC_CAPS;
 641         pcd->pcd_class = PMC_CLASS_E500;
 642         pcd->pcd_num   = E500_MAX_PMCS;
 643         pcd->pcd_ri    = pmc_mdep->pmd_npmc;
 644         pcd->pcd_width = 32;
 645
 646         pcd->pcd_allocate_pmc   = e500_allocate_pmc;
 647         pcd->pcd_config_pmc     = e500_config_pmc;
 648         pcd->pcd_pcpu_fini      = e500_pcpu_fini;
 649         pcd->pcd_pcpu_init      = e500_pcpu_init;
 650         pcd->pcd_describe       = powerpc_describe;
 651         pcd->pcd_get_config     = powerpc_get_config;
 652         pcd->pcd_read_pmc       = e500_read_pmc;
 653         pcd->pcd_release_pmc    = e500_release_pmc;
 654         pcd->pcd_start_pmc      = e500_start_pmc;
 655         pcd->pcd_stop_pmc       = e500_stop_pmc;
 656         pcd->pcd_write_pmc      = e500_write_pmc;
 657
 658         pmc_mdep->pmd_npmc   += E500_MAX_PMCS;
 659         pmc_mdep->pmd_intr   =  e500_intr;
 660
 661         return (0);
 662 }