2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2008 Joseph Koshy
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * Common code for handling Intel CPUs.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #include <sys/param.h>
38 #include <sys/pmckern.h>
39 #include <sys/systm.h>
41 #include <machine/cpu.h>
42 #include <machine/cputypes.h>
43 #include <machine/md_var.h>
44 #include <machine/specialreg.h>
47 intel_switch_in(struct pmc_cpu *pc, struct pmc_process *pp)
51 PMCDBG3(MDP,SWI,1, "pc=%p pp=%p enable-msr=%d", pc, pp,
52 pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS);
54 /* allow the RDPMC instruction if needed */
55 if (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS)
56 load_cr4(rcr4() | CR4_PCE);
58 PMCDBG1(MDP,SWI,1, "cr4=0x%jx", (uintmax_t) rcr4());
64 intel_switch_out(struct pmc_cpu *pc, struct pmc_process *pp)
67 (void) pp; /* can be NULL */
69 PMCDBG3(MDP,SWO,1, "pc=%p pp=%p cr4=0x%jx", pc, pp,
72 /* always turn off the RDPMC instruction */
73 load_cr4(rcr4() & ~CR4_PCE);
79 pmc_intel_initialize(void)
81 struct pmc_mdep *pmc_mdep;
82 enum pmc_cputype cputype;
83 int error, family, model, nclasses, ncpus, stepping, verov;
85 KASSERT(cpu_vendor_id == CPU_VENDOR_INTEL,
86 ("[intel,%d] Initializing non-intel processor", __LINE__));
88 PMCDBG1(MDP,INI,0, "intel-initialize cpuid=0x%x", cpu_id);
94 family = CPUID_TO_FAMILY(cpu_id);
95 model = CPUID_TO_MODEL(cpu_id);
96 stepping = CPUID_TO_STEPPING(cpu_id);
98 snprintf(pmc_cpuid, sizeof(pmc_cpuid), "GenuineIntel-%d-%02X-%X",
99 family, model, stepping);
101 switch (cpu_id & 0xF00) {
102 case 0x600: /* Pentium Pro, Celeron, Pentium II & III */
105 cputype = PMC_CPU_INTEL_CORE;
108 /* Per Intel document 315338-020. */
109 if (stepping == 0x7) {
110 cputype = PMC_CPU_INTEL_CORE;
113 cputype = PMC_CPU_INTEL_CORE2;
118 cputype = PMC_CPU_INTEL_CORE2EXTREME;
121 case 0x1C: /* Per Intel document 320047-002. */
122 cputype = PMC_CPU_INTEL_ATOM;
127 * Per Intel document 253669-032 9/2009,
131 * Per Intel document 253669-032 9/2009,
134 cputype = PMC_CPU_INTEL_COREI7;
138 cputype = PMC_CPU_INTEL_NEHALEM_EX;
141 case 0x25: /* Per Intel document 253669-033US 12/2009. */
142 case 0x2C: /* Per Intel document 253669-033US 12/2009. */
143 cputype = PMC_CPU_INTEL_WESTMERE;
146 case 0x2F: /* Westmere-EX, seen in wild */
147 cputype = PMC_CPU_INTEL_WESTMERE_EX;
150 case 0x2A: /* Per Intel document 253669-039US 05/2011. */
151 cputype = PMC_CPU_INTEL_SANDYBRIDGE;
154 case 0x2D: /* Per Intel document 253669-044US 08/2012. */
155 cputype = PMC_CPU_INTEL_SANDYBRIDGE_XEON;
158 case 0x3A: /* Per Intel document 253669-043US 05/2012. */
159 cputype = PMC_CPU_INTEL_IVYBRIDGE;
162 case 0x3E: /* Per Intel document 325462-045US 01/2013. */
163 cputype = PMC_CPU_INTEL_IVYBRIDGE_XEON;
170 case 0x8E: /* Per Intel document 325462-063US July 2017. */
171 case 0x9E: /* Per Intel document 325462-063US July 2017. */
172 cputype = PMC_CPU_INTEL_SKYLAKE;
175 case 0x55: /* SDM rev 63 */
176 cputype = PMC_CPU_INTEL_SKYLAKE_XEON;
181 cputype = PMC_CPU_INTEL_BROADWELL;
186 cputype = PMC_CPU_INTEL_BROADWELL_XEON;
189 case 0x3F: /* Per Intel document 325462-045US 09/2014. */
190 case 0x46: /* Per Intel document 325462-045US 09/2014. */
191 /* Should 46 be XEON. probably its own? */
192 cputype = PMC_CPU_INTEL_HASWELL_XEON;
195 case 0x3C: /* Per Intel document 325462-045US 01/2013. */
196 case 0x45: /* Per Intel document 325462-045US 09/2014. */
197 cputype = PMC_CPU_INTEL_HASWELL;
202 case 0x4D: /* Per Intel document 330061-001 01/2014. */
205 cputype = PMC_CPU_INTEL_ATOM_SILVERMONT;
208 case 0x5C: /* Per Intel document 325462-071US 10/2019. */
210 cputype = PMC_CPU_INTEL_ATOM_GOLDMONT;
218 if ((int) cputype == -1) {
219 printf("pmc: Unknown Intel CPU.\n");
223 /* Allocate base class and initialize machine dependent struct */
224 pmc_mdep = pmc_mdep_alloc(nclasses);
226 pmc_mdep->pmd_cputype = cputype;
227 pmc_mdep->pmd_switch_in = intel_switch_in;
228 pmc_mdep->pmd_switch_out = intel_switch_out;
230 ncpus = pmc_cpu_max();
231 error = pmc_tsc_initialize(pmc_mdep, ncpus);
236 * Intel Core, Core 2 and Atom processors.
238 case PMC_CPU_INTEL_ATOM:
239 case PMC_CPU_INTEL_ATOM_SILVERMONT:
240 case PMC_CPU_INTEL_ATOM_GOLDMONT:
241 case PMC_CPU_INTEL_BROADWELL:
242 case PMC_CPU_INTEL_BROADWELL_XEON:
243 case PMC_CPU_INTEL_SKYLAKE_XEON:
244 case PMC_CPU_INTEL_SKYLAKE:
245 case PMC_CPU_INTEL_CORE:
246 case PMC_CPU_INTEL_CORE2:
247 case PMC_CPU_INTEL_CORE2EXTREME:
248 case PMC_CPU_INTEL_COREI7:
249 case PMC_CPU_INTEL_NEHALEM_EX:
250 case PMC_CPU_INTEL_IVYBRIDGE:
251 case PMC_CPU_INTEL_SANDYBRIDGE:
252 case PMC_CPU_INTEL_WESTMERE:
253 case PMC_CPU_INTEL_WESTMERE_EX:
254 case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
255 case PMC_CPU_INTEL_IVYBRIDGE_XEON:
256 case PMC_CPU_INTEL_HASWELL:
257 case PMC_CPU_INTEL_HASWELL_XEON:
258 error = pmc_core_initialize(pmc_mdep, ncpus, verov);
262 KASSERT(0, ("[intel,%d] Unknown CPU type", __LINE__));
266 pmc_tsc_finalize(pmc_mdep);
271 * Init the uncore class.
275 * Intel Corei7 and Westmere processors.
277 case PMC_CPU_INTEL_COREI7:
278 case PMC_CPU_INTEL_HASWELL:
279 case PMC_CPU_INTEL_SANDYBRIDGE:
280 case PMC_CPU_INTEL_WESTMERE:
281 case PMC_CPU_INTEL_BROADWELL:
282 error = pmc_uncore_initialize(pmc_mdep, ncpus);
289 pmc_mdep_free(pmc_mdep);
297 pmc_intel_finalize(struct pmc_mdep *md)
299 pmc_tsc_finalize(md);
301 switch (md->pmd_cputype) {
302 case PMC_CPU_INTEL_ATOM:
303 case PMC_CPU_INTEL_ATOM_SILVERMONT:
304 case PMC_CPU_INTEL_ATOM_GOLDMONT:
305 case PMC_CPU_INTEL_BROADWELL:
306 case PMC_CPU_INTEL_BROADWELL_XEON:
307 case PMC_CPU_INTEL_SKYLAKE_XEON:
308 case PMC_CPU_INTEL_SKYLAKE:
309 case PMC_CPU_INTEL_CORE:
310 case PMC_CPU_INTEL_CORE2:
311 case PMC_CPU_INTEL_CORE2EXTREME:
312 case PMC_CPU_INTEL_COREI7:
313 case PMC_CPU_INTEL_NEHALEM_EX:
314 case PMC_CPU_INTEL_HASWELL:
315 case PMC_CPU_INTEL_HASWELL_XEON:
316 case PMC_CPU_INTEL_IVYBRIDGE:
317 case PMC_CPU_INTEL_SANDYBRIDGE:
318 case PMC_CPU_INTEL_WESTMERE:
319 case PMC_CPU_INTEL_WESTMERE_EX:
320 case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
321 case PMC_CPU_INTEL_IVYBRIDGE_XEON:
322 pmc_core_finalize(md);
325 KASSERT(0, ("[intel,%d] unknown CPU type", __LINE__));
331 switch (md->pmd_cputype) {
332 case PMC_CPU_INTEL_BROADWELL:
333 case PMC_CPU_INTEL_COREI7:
334 case PMC_CPU_INTEL_HASWELL:
335 case PMC_CPU_INTEL_SANDYBRIDGE:
336 case PMC_CPU_INTEL_WESTMERE:
337 pmc_uncore_finalize(md);