2 * Copyright (c) 2008 Joseph Koshy
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * Common code for handling Intel CPUs.
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
36 #include <sys/pmckern.h>
37 #include <sys/systm.h>
39 #include <machine/cpu.h>
40 #include <machine/cputypes.h>
41 #include <machine/md_var.h>
42 #include <machine/specialreg.h>
45 intel_switch_in(struct pmc_cpu *pc, struct pmc_process *pp)
49 PMCDBG3(MDP,SWI,1, "pc=%p pp=%p enable-msr=%d", pc, pp,
50 pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS);
52 /* allow the RDPMC instruction if needed */
53 if (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS)
54 load_cr4(rcr4() | CR4_PCE);
56 PMCDBG1(MDP,SWI,1, "cr4=0x%jx", (uintmax_t) rcr4());
62 intel_switch_out(struct pmc_cpu *pc, struct pmc_process *pp)
65 (void) pp; /* can be NULL */
67 PMCDBG3(MDP,SWO,1, "pc=%p pp=%p cr4=0x%jx", pc, pp,
70 /* always turn off the RDPMC instruction */
71 load_cr4(rcr4() & ~CR4_PCE);
77 pmc_intel_initialize(void)
79 struct pmc_mdep *pmc_mdep;
80 enum pmc_cputype cputype;
81 int error, model, nclasses, ncpus, stepping, verov;
83 KASSERT(cpu_vendor_id == CPU_VENDOR_INTEL,
84 ("[intel,%d] Initializing non-intel processor", __LINE__));
86 PMCDBG1(MDP,INI,0, "intel-initialize cpuid=0x%x", cpu_id);
92 model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4);
93 stepping = cpu_id & 0xF;
95 switch (cpu_id & 0xF00) {
97 case 0x500: /* Pentium family processors */
98 cputype = PMC_CPU_INTEL_P5;
101 case 0x600: /* Pentium Pro, Celeron, Pentium II & III */
103 #if defined(__i386__)
105 cputype = PMC_CPU_INTEL_P6;
108 cputype = PMC_CPU_INTEL_PII;
111 cputype = PMC_CPU_INTEL_CL;
113 case 0x7: case 0x8: case 0xA: case 0xB:
114 cputype = PMC_CPU_INTEL_PIII;
117 cputype = PMC_CPU_INTEL_PM;
121 cputype = PMC_CPU_INTEL_CORE;
124 /* Per Intel document 315338-020. */
125 if (stepping == 0x7) {
126 cputype = PMC_CPU_INTEL_CORE;
129 cputype = PMC_CPU_INTEL_CORE2;
134 cputype = PMC_CPU_INTEL_CORE2EXTREME;
137 case 0x1C: /* Per Intel document 320047-002. */
138 cputype = PMC_CPU_INTEL_ATOM;
143 * Per Intel document 253669-032 9/2009,
147 * Per Intel document 253669-032 9/2009,
150 cputype = PMC_CPU_INTEL_COREI7;
154 cputype = PMC_CPU_INTEL_NEHALEM_EX;
157 case 0x25: /* Per Intel document 253669-033US 12/2009. */
158 case 0x2C: /* Per Intel document 253669-033US 12/2009. */
159 cputype = PMC_CPU_INTEL_WESTMERE;
162 case 0x2F: /* Westmere-EX, seen in wild */
163 cputype = PMC_CPU_INTEL_WESTMERE_EX;
166 case 0x2A: /* Per Intel document 253669-039US 05/2011. */
167 cputype = PMC_CPU_INTEL_SANDYBRIDGE;
170 case 0x2D: /* Per Intel document 253669-044US 08/2012. */
171 cputype = PMC_CPU_INTEL_SANDYBRIDGE_XEON;
174 case 0x3A: /* Per Intel document 253669-043US 05/2012. */
175 cputype = PMC_CPU_INTEL_IVYBRIDGE;
178 case 0x3E: /* Per Intel document 325462-045US 01/2013. */
179 cputype = PMC_CPU_INTEL_IVYBRIDGE_XEON;
184 cputype = PMC_CPU_INTEL_SKYLAKE;
187 case 0x55: /* SDM rev 63 */
188 cputype = PMC_CPU_INTEL_SKYLAKE_XEON;
193 cputype = PMC_CPU_INTEL_BROADWELL;
198 cputype = PMC_CPU_INTEL_BROADWELL_XEON;
201 case 0x3F: /* Per Intel document 325462-045US 09/2014. */
202 case 0x46: /* Per Intel document 325462-045US 09/2014. */
203 /* Should 46 be XEON. probably its own? */
204 cputype = PMC_CPU_INTEL_HASWELL_XEON;
207 case 0x3C: /* Per Intel document 325462-045US 01/2013. */
208 case 0x45: /* Per Intel document 325462-045US 09/2014. */
209 cputype = PMC_CPU_INTEL_HASWELL;
212 case 0x4D: /* Per Intel document 330061-001 01/2014. */
213 cputype = PMC_CPU_INTEL_ATOM_SILVERMONT;
218 #if defined(__i386__) || defined(__amd64__)
220 if (model >= 0 && model <= 6) /* known models */
221 cputype = PMC_CPU_INTEL_PIV;
226 if ((int) cputype == -1) {
227 printf("pmc: Unknown Intel CPU.\n");
231 /* Allocate base class and initialize machine dependent struct */
232 pmc_mdep = pmc_mdep_alloc(nclasses);
234 pmc_mdep->pmd_cputype = cputype;
235 pmc_mdep->pmd_switch_in = intel_switch_in;
236 pmc_mdep->pmd_switch_out = intel_switch_out;
238 ncpus = pmc_cpu_max();
239 error = pmc_tsc_initialize(pmc_mdep, ncpus);
243 #if defined(__i386__) || defined(__amd64__)
245 * Intel Core, Core 2 and Atom processors.
247 case PMC_CPU_INTEL_ATOM:
248 case PMC_CPU_INTEL_ATOM_SILVERMONT:
249 case PMC_CPU_INTEL_BROADWELL:
250 case PMC_CPU_INTEL_BROADWELL_XEON:
251 case PMC_CPU_INTEL_SKYLAKE_XEON:
252 case PMC_CPU_INTEL_SKYLAKE:
253 case PMC_CPU_INTEL_CORE:
254 case PMC_CPU_INTEL_CORE2:
255 case PMC_CPU_INTEL_CORE2EXTREME:
256 case PMC_CPU_INTEL_COREI7:
257 case PMC_CPU_INTEL_NEHALEM_EX:
258 case PMC_CPU_INTEL_IVYBRIDGE:
259 case PMC_CPU_INTEL_SANDYBRIDGE:
260 case PMC_CPU_INTEL_WESTMERE:
261 case PMC_CPU_INTEL_WESTMERE_EX:
262 case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
263 case PMC_CPU_INTEL_IVYBRIDGE_XEON:
264 case PMC_CPU_INTEL_HASWELL:
265 case PMC_CPU_INTEL_HASWELL_XEON:
266 error = pmc_core_initialize(pmc_mdep, ncpus, verov);
270 * Intel Pentium 4 Processors, and P4/EMT64 processors.
273 case PMC_CPU_INTEL_PIV:
274 error = pmc_p4_initialize(pmc_mdep, ncpus);
278 #if defined(__i386__)
280 * P6 Family Processors
283 case PMC_CPU_INTEL_P6:
284 case PMC_CPU_INTEL_CL:
285 case PMC_CPU_INTEL_PII:
286 case PMC_CPU_INTEL_PIII:
287 case PMC_CPU_INTEL_PM:
288 error = pmc_p6_initialize(pmc_mdep, ncpus);
292 * Intel Pentium PMCs.
295 case PMC_CPU_INTEL_P5:
296 error = pmc_p5_initialize(pmc_mdep, ncpus);
301 KASSERT(0, ("[intel,%d] Unknown CPU type", __LINE__));
305 pmc_tsc_finalize(pmc_mdep);
310 * Init the uncore class.
312 #if defined(__i386__) || defined(__amd64__)
315 * Intel Corei7 and Westmere processors.
317 case PMC_CPU_INTEL_COREI7:
318 case PMC_CPU_INTEL_HASWELL:
319 case PMC_CPU_INTEL_SANDYBRIDGE:
320 case PMC_CPU_INTEL_WESTMERE:
321 case PMC_CPU_INTEL_BROADWELL:
322 error = pmc_uncore_initialize(pmc_mdep, ncpus);
330 pmc_mdep_free(pmc_mdep);
338 pmc_intel_finalize(struct pmc_mdep *md)
340 pmc_tsc_finalize(md);
342 switch (md->pmd_cputype) {
343 #if defined(__i386__) || defined(__amd64__)
344 case PMC_CPU_INTEL_ATOM:
345 case PMC_CPU_INTEL_ATOM_SILVERMONT:
346 case PMC_CPU_INTEL_BROADWELL:
347 case PMC_CPU_INTEL_BROADWELL_XEON:
348 case PMC_CPU_INTEL_SKYLAKE_XEON:
349 case PMC_CPU_INTEL_SKYLAKE:
350 case PMC_CPU_INTEL_CORE:
351 case PMC_CPU_INTEL_CORE2:
352 case PMC_CPU_INTEL_CORE2EXTREME:
353 case PMC_CPU_INTEL_COREI7:
354 case PMC_CPU_INTEL_NEHALEM_EX:
355 case PMC_CPU_INTEL_HASWELL:
356 case PMC_CPU_INTEL_HASWELL_XEON:
357 case PMC_CPU_INTEL_IVYBRIDGE:
358 case PMC_CPU_INTEL_SANDYBRIDGE:
359 case PMC_CPU_INTEL_WESTMERE:
360 case PMC_CPU_INTEL_WESTMERE_EX:
361 case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
362 case PMC_CPU_INTEL_IVYBRIDGE_XEON:
363 pmc_core_finalize(md);
366 case PMC_CPU_INTEL_PIV:
370 #if defined(__i386__)
371 case PMC_CPU_INTEL_P6:
372 case PMC_CPU_INTEL_CL:
373 case PMC_CPU_INTEL_PII:
374 case PMC_CPU_INTEL_PIII:
375 case PMC_CPU_INTEL_PM:
378 case PMC_CPU_INTEL_P5:
383 KASSERT(0, ("[intel,%d] unknown CPU type", __LINE__));
389 #if defined(__i386__) || defined(__amd64__)
390 switch (md->pmd_cputype) {
391 case PMC_CPU_INTEL_BROADWELL:
392 case PMC_CPU_INTEL_COREI7:
393 case PMC_CPU_INTEL_HASWELL:
394 case PMC_CPU_INTEL_SANDYBRIDGE:
395 case PMC_CPU_INTEL_WESTMERE:
396 pmc_uncore_finalize(md);