2 * Copyright (c) 2008 Joseph Koshy
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * Common code for handling Intel CPUs.
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
36 #include <sys/pmckern.h>
37 #include <sys/systm.h>
39 #include <machine/cpu.h>
40 #include <machine/cputypes.h>
41 #include <machine/md_var.h>
42 #include <machine/specialreg.h>
45 intel_switch_in(struct pmc_cpu *pc, struct pmc_process *pp)
49 PMCDBG3(MDP,SWI,1, "pc=%p pp=%p enable-msr=%d", pc, pp,
50 pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS);
52 /* allow the RDPMC instruction if needed */
53 if (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS)
54 load_cr4(rcr4() | CR4_PCE);
56 PMCDBG1(MDP,SWI,1, "cr4=0x%jx", (uintmax_t) rcr4());
62 intel_switch_out(struct pmc_cpu *pc, struct pmc_process *pp)
65 (void) pp; /* can be NULL */
67 PMCDBG3(MDP,SWO,1, "pc=%p pp=%p cr4=0x%jx", pc, pp,
70 /* always turn off the RDPMC instruction */
71 load_cr4(rcr4() & ~CR4_PCE);
77 pmc_intel_initialize(void)
79 struct pmc_mdep *pmc_mdep;
80 enum pmc_cputype cputype;
81 int error, model, nclasses, ncpus, stepping, verov;
83 KASSERT(cpu_vendor_id == CPU_VENDOR_INTEL,
84 ("[intel,%d] Initializing non-intel processor", __LINE__));
86 PMCDBG1(MDP,INI,0, "intel-initialize cpuid=0x%x", cpu_id);
92 model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4);
93 stepping = cpu_id & 0xF;
95 switch (cpu_id & 0xF00) {
97 case 0x500: /* Pentium family processors */
98 cputype = PMC_CPU_INTEL_P5;
101 case 0x600: /* Pentium Pro, Celeron, Pentium II & III */
103 #if defined(__i386__)
105 cputype = PMC_CPU_INTEL_P6;
108 cputype = PMC_CPU_INTEL_PII;
111 cputype = PMC_CPU_INTEL_CL;
113 case 0x7: case 0x8: case 0xA: case 0xB:
114 cputype = PMC_CPU_INTEL_PIII;
117 cputype = PMC_CPU_INTEL_PM;
121 cputype = PMC_CPU_INTEL_CORE;
124 /* Per Intel document 315338-020. */
125 if (stepping == 0x7) {
126 cputype = PMC_CPU_INTEL_CORE;
129 cputype = PMC_CPU_INTEL_CORE2;
134 cputype = PMC_CPU_INTEL_CORE2EXTREME;
137 case 0x1C: /* Per Intel document 320047-002. */
138 cputype = PMC_CPU_INTEL_ATOM;
143 * Per Intel document 253669-032 9/2009,
147 * Per Intel document 253669-032 9/2009,
150 cputype = PMC_CPU_INTEL_COREI7;
154 cputype = PMC_CPU_INTEL_NEHALEM_EX;
157 case 0x25: /* Per Intel document 253669-033US 12/2009. */
158 case 0x2C: /* Per Intel document 253669-033US 12/2009. */
159 cputype = PMC_CPU_INTEL_WESTMERE;
162 case 0x2F: /* Westmere-EX, seen in wild */
163 cputype = PMC_CPU_INTEL_WESTMERE_EX;
166 case 0x2A: /* Per Intel document 253669-039US 05/2011. */
167 cputype = PMC_CPU_INTEL_SANDYBRIDGE;
170 case 0x2D: /* Per Intel document 253669-044US 08/2012. */
171 cputype = PMC_CPU_INTEL_SANDYBRIDGE_XEON;
174 case 0x3A: /* Per Intel document 253669-043US 05/2012. */
175 cputype = PMC_CPU_INTEL_IVYBRIDGE;
178 case 0x3E: /* Per Intel document 325462-045US 01/2013. */
179 cputype = PMC_CPU_INTEL_IVYBRIDGE_XEON;
184 cputype = PMC_CPU_INTEL_SKYLAKE;
189 cputype = PMC_CPU_INTEL_BROADWELL;
194 cputype = PMC_CPU_INTEL_BROADWELL_XEON;
197 case 0x3F: /* Per Intel document 325462-045US 09/2014. */
198 case 0x46: /* Per Intel document 325462-045US 09/2014. */
199 /* Should 46 be XEON. probably its own? */
200 cputype = PMC_CPU_INTEL_HASWELL_XEON;
203 case 0x3C: /* Per Intel document 325462-045US 01/2013. */
204 case 0x45: /* Per Intel document 325462-045US 09/2014. */
205 cputype = PMC_CPU_INTEL_HASWELL;
208 case 0x4D: /* Per Intel document 330061-001 01/2014. */
209 cputype = PMC_CPU_INTEL_ATOM_SILVERMONT;
214 #if defined(__i386__) || defined(__amd64__)
216 if (model >= 0 && model <= 6) /* known models */
217 cputype = PMC_CPU_INTEL_PIV;
222 if ((int) cputype == -1) {
223 printf("pmc: Unknown Intel CPU.\n");
227 /* Allocate base class and initialize machine dependent struct */
228 pmc_mdep = pmc_mdep_alloc(nclasses);
230 pmc_mdep->pmd_cputype = cputype;
231 pmc_mdep->pmd_switch_in = intel_switch_in;
232 pmc_mdep->pmd_switch_out = intel_switch_out;
234 ncpus = pmc_cpu_max();
235 error = pmc_tsc_initialize(pmc_mdep, ncpus);
239 #if defined(__i386__) || defined(__amd64__)
241 * Intel Core, Core 2 and Atom processors.
243 case PMC_CPU_INTEL_ATOM:
244 case PMC_CPU_INTEL_ATOM_SILVERMONT:
245 case PMC_CPU_INTEL_BROADWELL:
246 case PMC_CPU_INTEL_BROADWELL_XEON:
247 case PMC_CPU_INTEL_SKYLAKE:
248 case PMC_CPU_INTEL_CORE:
249 case PMC_CPU_INTEL_CORE2:
250 case PMC_CPU_INTEL_CORE2EXTREME:
251 case PMC_CPU_INTEL_COREI7:
252 case PMC_CPU_INTEL_NEHALEM_EX:
253 case PMC_CPU_INTEL_IVYBRIDGE:
254 case PMC_CPU_INTEL_SANDYBRIDGE:
255 case PMC_CPU_INTEL_WESTMERE:
256 case PMC_CPU_INTEL_WESTMERE_EX:
257 case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
258 case PMC_CPU_INTEL_IVYBRIDGE_XEON:
259 case PMC_CPU_INTEL_HASWELL:
260 case PMC_CPU_INTEL_HASWELL_XEON:
261 error = pmc_core_initialize(pmc_mdep, ncpus, verov);
265 * Intel Pentium 4 Processors, and P4/EMT64 processors.
268 case PMC_CPU_INTEL_PIV:
269 error = pmc_p4_initialize(pmc_mdep, ncpus);
273 #if defined(__i386__)
275 * P6 Family Processors
278 case PMC_CPU_INTEL_P6:
279 case PMC_CPU_INTEL_CL:
280 case PMC_CPU_INTEL_PII:
281 case PMC_CPU_INTEL_PIII:
282 case PMC_CPU_INTEL_PM:
283 error = pmc_p6_initialize(pmc_mdep, ncpus);
287 * Intel Pentium PMCs.
290 case PMC_CPU_INTEL_P5:
291 error = pmc_p5_initialize(pmc_mdep, ncpus);
296 KASSERT(0, ("[intel,%d] Unknown CPU type", __LINE__));
300 pmc_tsc_finalize(pmc_mdep);
305 * Init the uncore class.
307 #if defined(__i386__) || defined(__amd64__)
310 * Intel Corei7 and Westmere processors.
312 case PMC_CPU_INTEL_COREI7:
313 case PMC_CPU_INTEL_HASWELL:
314 case PMC_CPU_INTEL_SANDYBRIDGE:
315 case PMC_CPU_INTEL_WESTMERE:
316 case PMC_CPU_INTEL_BROADWELL:
317 error = pmc_uncore_initialize(pmc_mdep, ncpus);
325 pmc_mdep_free(pmc_mdep);
333 pmc_intel_finalize(struct pmc_mdep *md)
335 pmc_tsc_finalize(md);
337 switch (md->pmd_cputype) {
338 #if defined(__i386__) || defined(__amd64__)
339 case PMC_CPU_INTEL_ATOM:
340 case PMC_CPU_INTEL_ATOM_SILVERMONT:
341 case PMC_CPU_INTEL_BROADWELL:
342 case PMC_CPU_INTEL_BROADWELL_XEON:
343 case PMC_CPU_INTEL_SKYLAKE:
344 case PMC_CPU_INTEL_CORE:
345 case PMC_CPU_INTEL_CORE2:
346 case PMC_CPU_INTEL_CORE2EXTREME:
347 case PMC_CPU_INTEL_COREI7:
348 case PMC_CPU_INTEL_NEHALEM_EX:
349 case PMC_CPU_INTEL_HASWELL:
350 case PMC_CPU_INTEL_HASWELL_XEON:
351 case PMC_CPU_INTEL_IVYBRIDGE:
352 case PMC_CPU_INTEL_SANDYBRIDGE:
353 case PMC_CPU_INTEL_WESTMERE:
354 case PMC_CPU_INTEL_WESTMERE_EX:
355 case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
356 case PMC_CPU_INTEL_IVYBRIDGE_XEON:
357 pmc_core_finalize(md);
360 case PMC_CPU_INTEL_PIV:
364 #if defined(__i386__)
365 case PMC_CPU_INTEL_P6:
366 case PMC_CPU_INTEL_CL:
367 case PMC_CPU_INTEL_PII:
368 case PMC_CPU_INTEL_PIII:
369 case PMC_CPU_INTEL_PM:
372 case PMC_CPU_INTEL_P5:
377 KASSERT(0, ("[intel,%d] unknown CPU type", __LINE__));
383 #if defined(__i386__) || defined(__amd64__)
384 switch (md->pmd_cputype) {
385 case PMC_CPU_INTEL_BROADWELL:
386 case PMC_CPU_INTEL_COREI7:
387 case PMC_CPU_INTEL_HASWELL:
388 case PMC_CPU_INTEL_SANDYBRIDGE:
389 case PMC_CPU_INTEL_WESTMERE:
390 pmc_uncore_finalize(md);