sys/dev/hwpmc/hwpmc_intel.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 2008 Joseph Koshy
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  */
  28
  29 /*
  30  * Common code for handling Intel CPUs.
  31  */
  32
  33 #include <sys/cdefs.h>
  34 __FBSDID("$FreeBSD$");
  35
  36 #include <sys/param.h>
  37 #include <sys/pmc.h>
  38 #include <sys/pmckern.h>
  39 #include <sys/systm.h>
  40
  41 #include <machine/cpu.h>
  42 #include <machine/cputypes.h>
  43 #include <machine/md_var.h>
  44 #include <machine/specialreg.h>
  45
  46 static int
  47 intel_switch_in(struct pmc_cpu *pc, struct pmc_process *pp)
  48 {
  49         (void) pc;
  50
  51         PMCDBG3(MDP,SWI,1, "pc=%p pp=%p enable-msr=%d", pc, pp,
  52             pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS);
  53
  54         /* allow the RDPMC instruction if needed */
  55         if (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS)
  56                 load_cr4(rcr4() | CR4_PCE);
  57
  58         PMCDBG1(MDP,SWI,1, "cr4=0x%jx", (uintmax_t) rcr4());
  59
  60         return 0;
  61 }
  62
  63 static int
  64 intel_switch_out(struct pmc_cpu *pc, struct pmc_process *pp)
  65 {
  66         (void) pc;
  67         (void) pp;              /* can be NULL */
  68
  69         PMCDBG3(MDP,SWO,1, "pc=%p pp=%p cr4=0x%jx", pc, pp,
  70             (uintmax_t) rcr4());
  71
  72         /* always turn off the RDPMC instruction */
  73         load_cr4(rcr4() & ~CR4_PCE);
  74
  75         return 0;
  76 }
  77
  78 struct pmc_mdep *
  79 pmc_intel_initialize(void)
  80 {
  81         struct pmc_mdep *pmc_mdep;
  82         enum pmc_cputype cputype;
  83         int error, model, nclasses, ncpus, stepping, verov;
  84
  85         KASSERT(cpu_vendor_id == CPU_VENDOR_INTEL,
  86             ("[intel,%d] Initializing non-intel processor", __LINE__));
  87
  88         PMCDBG1(MDP,INI,0, "intel-initialize cpuid=0x%x", cpu_id);
  89
  90         cputype = -1;
  91         nclasses = 2;
  92         error = 0;
  93         verov = 0;
  94         model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4);
  95         stepping = cpu_id & 0xF;
  96
  97         snprintf(pmc_cpuid, sizeof(pmc_cpuid), "GenuineIntel-%d-%02X",
  98                          (cpu_id & 0xF00) >> 8, model);
  99         switch (cpu_id & 0xF00) {
 100         case 0x600:             /* Pentium Pro, Celeron, Pentium II & III */
 101                 switch (model) {
 102                 case 0xE:
 103                         cputype = PMC_CPU_INTEL_CORE;
 104                         break;
 105                 case 0xF:
 106                         /* Per Intel document 315338-020. */
 107                         if (stepping == 0x7) {
 108                                 cputype = PMC_CPU_INTEL_CORE;
 109                                 verov = 1;
 110                         } else {
 111                                 cputype = PMC_CPU_INTEL_CORE2;
 112                                 nclasses = 3;
 113                         }
 114                         break;
 115                 case 0x17:
 116                         cputype = PMC_CPU_INTEL_CORE2EXTREME;
 117                         nclasses = 3;
 118                         break;
 119                 case 0x1C:      /* Per Intel document 320047-002. */
 120                         cputype = PMC_CPU_INTEL_ATOM;
 121                         nclasses = 3;
 122                         break;
 123                 case 0x1A:
 124                 case 0x1E:      /*
 125                                  * Per Intel document 253669-032 9/2009,
 126                                  * pages A-2 and A-57
 127                                  */
 128                 case 0x1F:      /*
 129                                  * Per Intel document 253669-032 9/2009,
 130                                  * pages A-2 and A-57
 131                                  */
 132                         cputype = PMC_CPU_INTEL_COREI7;
 133                         nclasses = 5;
 134                         break;
 135                 case 0x2E:
 136                         cputype = PMC_CPU_INTEL_NEHALEM_EX;
 137                         nclasses = 3;
 138                         break;
 139                 case 0x25:      /* Per Intel document 253669-033US 12/2009. */
 140                 case 0x2C:      /* Per Intel document 253669-033US 12/2009. */
 141                         cputype = PMC_CPU_INTEL_WESTMERE;
 142                         nclasses = 5;
 143                         break;
 144                 case 0x2F:      /* Westmere-EX, seen in wild */
 145                         cputype = PMC_CPU_INTEL_WESTMERE_EX;
 146                         nclasses = 3;
 147                         break;
 148                 case 0x2A:      /* Per Intel document 253669-039US 05/2011. */
 149                         cputype = PMC_CPU_INTEL_SANDYBRIDGE;
 150                         nclasses = 5;
 151                         break;
 152                 case 0x2D:      /* Per Intel document 253669-044US 08/2012. */
 153                         cputype = PMC_CPU_INTEL_SANDYBRIDGE_XEON;
 154                         nclasses = 3;
 155                         break;
 156                 case 0x3A:      /* Per Intel document 253669-043US 05/2012. */
 157                         cputype = PMC_CPU_INTEL_IVYBRIDGE;
 158                         nclasses = 3;
 159                         break;
 160                 case 0x3E:      /* Per Intel document 325462-045US 01/2013. */
 161                         cputype = PMC_CPU_INTEL_IVYBRIDGE_XEON;
 162                         nclasses = 3;
 163                         break;
 164                         /* Skylake */
 165                 case 0x4e:
 166                 case 0x5e:
 167                         /* Kabylake */
 168                 case 0x8E:      /* Per Intel document 325462-063US July 2017. */
 169                 case 0x9E:      /* Per Intel document 325462-063US July 2017. */
 170                         cputype = PMC_CPU_INTEL_SKYLAKE;
 171                         nclasses = 3;
 172                         break;
 173                 case 0x55:      /* SDM rev 63 */
 174                         cputype = PMC_CPU_INTEL_SKYLAKE_XEON;
 175                         nclasses = 3;
 176                         break;
 177                 case 0x3D:
 178                 case 0x47:
 179                         cputype = PMC_CPU_INTEL_BROADWELL;
 180                         nclasses = 3;
 181                         break;
 182                 case 0x4f:
 183                 case 0x56:
 184                         cputype = PMC_CPU_INTEL_BROADWELL_XEON;
 185                         nclasses = 3;
 186                         break;
 187                 case 0x3F:      /* Per Intel document 325462-045US 09/2014. */
 188                 case 0x46:      /* Per Intel document 325462-045US 09/2014. */
 189                                 /* Should 46 be XEON. probably its own? */
 190                         cputype = PMC_CPU_INTEL_HASWELL_XEON;
 191                         nclasses = 3;
 192                         break;
 193                 case 0x3C:      /* Per Intel document 325462-045US 01/2013. */
 194                 case 0x45:      /* Per Intel document 325462-045US 09/2014. */
 195                         cputype = PMC_CPU_INTEL_HASWELL;
 196                         nclasses = 5;
 197                         break;
 198                 case 0x37:
 199                 case 0x4A:
 200                 case 0x4D:      /* Per Intel document 330061-001 01/2014. */
 201                 case 0x5A:
 202                 case 0x5D:
 203                         cputype = PMC_CPU_INTEL_ATOM_SILVERMONT;
 204                         nclasses = 3;
 205                         break;
 206                 case 0x5C:      /* Per Intel document 325462-071US 10/2019. */
 207                 case 0x5F:
 208                         cputype = PMC_CPU_INTEL_ATOM_GOLDMONT;
 209                         nclasses = 3;
 210                         break;
 211                 }
 212                 break;
 213         }
 214
 215
 216         if ((int) cputype == -1) {
 217                 printf("pmc: Unknown Intel CPU.\n");
 218                 return (NULL);
 219         }
 220
 221         /* Allocate base class and initialize machine dependent struct */
 222         pmc_mdep = pmc_mdep_alloc(nclasses);
 223
 224         pmc_mdep->pmd_cputype    = cputype;
 225         pmc_mdep->pmd_switch_in  = intel_switch_in;
 226         pmc_mdep->pmd_switch_out = intel_switch_out;
 227
 228         ncpus = pmc_cpu_max();
 229         error = pmc_tsc_initialize(pmc_mdep, ncpus);
 230         if (error)
 231                 goto error;
 232         switch (cputype) {
 233                 /*
 234                  * Intel Core, Core 2 and Atom processors.
 235                  */
 236         case PMC_CPU_INTEL_ATOM:
 237         case PMC_CPU_INTEL_ATOM_SILVERMONT:
 238         case PMC_CPU_INTEL_ATOM_GOLDMONT:
 239         case PMC_CPU_INTEL_BROADWELL:
 240         case PMC_CPU_INTEL_BROADWELL_XEON:
 241         case PMC_CPU_INTEL_SKYLAKE_XEON:
 242         case PMC_CPU_INTEL_SKYLAKE:
 243         case PMC_CPU_INTEL_CORE:
 244         case PMC_CPU_INTEL_CORE2:
 245         case PMC_CPU_INTEL_CORE2EXTREME:
 246         case PMC_CPU_INTEL_COREI7:
 247         case PMC_CPU_INTEL_NEHALEM_EX:
 248         case PMC_CPU_INTEL_IVYBRIDGE:
 249         case PMC_CPU_INTEL_SANDYBRIDGE:
 250         case PMC_CPU_INTEL_WESTMERE:
 251         case PMC_CPU_INTEL_WESTMERE_EX:
 252         case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
 253         case PMC_CPU_INTEL_IVYBRIDGE_XEON:
 254         case PMC_CPU_INTEL_HASWELL:
 255         case PMC_CPU_INTEL_HASWELL_XEON:
 256                 error = pmc_core_initialize(pmc_mdep, ncpus, verov);
 257                 break;
 258
 259         default:
 260                 KASSERT(0, ("[intel,%d] Unknown CPU type", __LINE__));
 261         }
 262
 263         if (error) {
 264                 pmc_tsc_finalize(pmc_mdep);
 265                 goto error;
 266         }
 267
 268         /*
 269          * Init the uncore class.
 270          */
 271         switch (cputype) {
 272                 /*
 273                  * Intel Corei7 and Westmere processors.
 274                  */
 275         case PMC_CPU_INTEL_COREI7:
 276         case PMC_CPU_INTEL_HASWELL:
 277         case PMC_CPU_INTEL_SANDYBRIDGE:
 278         case PMC_CPU_INTEL_WESTMERE:
 279         case PMC_CPU_INTEL_BROADWELL:
 280                 error = pmc_uncore_initialize(pmc_mdep, ncpus);
 281                 break;
 282         default:
 283                 break;
 284         }
 285   error:
 286         if (error) {
 287                 pmc_mdep_free(pmc_mdep);
 288                 pmc_mdep = NULL;
 289         }
 290
 291         return (pmc_mdep);
 292 }
 293
 294 void
 295 pmc_intel_finalize(struct pmc_mdep *md)
 296 {
 297         pmc_tsc_finalize(md);
 298
 299         switch (md->pmd_cputype) {
 300         case PMC_CPU_INTEL_ATOM:
 301         case PMC_CPU_INTEL_ATOM_SILVERMONT:
 302         case PMC_CPU_INTEL_ATOM_GOLDMONT:
 303         case PMC_CPU_INTEL_BROADWELL:
 304         case PMC_CPU_INTEL_BROADWELL_XEON:
 305         case PMC_CPU_INTEL_SKYLAKE_XEON:
 306         case PMC_CPU_INTEL_SKYLAKE:
 307         case PMC_CPU_INTEL_CORE:
 308         case PMC_CPU_INTEL_CORE2:
 309         case PMC_CPU_INTEL_CORE2EXTREME:
 310         case PMC_CPU_INTEL_COREI7:
 311         case PMC_CPU_INTEL_NEHALEM_EX:
 312         case PMC_CPU_INTEL_HASWELL:
 313         case PMC_CPU_INTEL_HASWELL_XEON:
 314         case PMC_CPU_INTEL_IVYBRIDGE:
 315         case PMC_CPU_INTEL_SANDYBRIDGE:
 316         case PMC_CPU_INTEL_WESTMERE:
 317         case PMC_CPU_INTEL_WESTMERE_EX:
 318         case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
 319         case PMC_CPU_INTEL_IVYBRIDGE_XEON:
 320                 pmc_core_finalize(md);
 321                 break;
 322         default:
 323                 KASSERT(0, ("[intel,%d] unknown CPU type", __LINE__));
 324         }
 325
 326         /*
 327          * Uncore.
 328          */
 329         switch (md->pmd_cputype) {
 330         case PMC_CPU_INTEL_BROADWELL:
 331         case PMC_CPU_INTEL_COREI7:
 332         case PMC_CPU_INTEL_HASWELL:
 333         case PMC_CPU_INTEL_SANDYBRIDGE:
 334         case PMC_CPU_INTEL_WESTMERE:
 335                 pmc_uncore_finalize(md);
 336                 break;
 337         default:
 338                 break;
 339         }
 340 }