2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2008 Joseph Koshy
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * Common code for handling Intel CPUs.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #include <sys/param.h>
38 #include <sys/pmckern.h>
39 #include <sys/systm.h>
41 #include <machine/cpu.h>
42 #include <machine/cputypes.h>
43 #include <machine/md_var.h>
44 #include <machine/specialreg.h>
47 intel_switch_in(struct pmc_cpu *pc, struct pmc_process *pp)
51 PMCDBG3(MDP,SWI,1, "pc=%p pp=%p enable-msr=%d", pc, pp,
52 pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS);
54 /* allow the RDPMC instruction if needed */
55 if (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS)
56 load_cr4(rcr4() | CR4_PCE);
58 PMCDBG1(MDP,SWI,1, "cr4=0x%jx", (uintmax_t) rcr4());
64 intel_switch_out(struct pmc_cpu *pc, struct pmc_process *pp)
67 (void) pp; /* can be NULL */
69 PMCDBG3(MDP,SWO,1, "pc=%p pp=%p cr4=0x%jx", pc, pp,
72 /* always turn off the RDPMC instruction */
73 load_cr4(rcr4() & ~CR4_PCE);
79 pmc_intel_initialize(void)
81 struct pmc_mdep *pmc_mdep;
82 enum pmc_cputype cputype;
83 int error, model, nclasses, ncpus, stepping, verov;
85 KASSERT(cpu_vendor_id == CPU_VENDOR_INTEL,
86 ("[intel,%d] Initializing non-intel processor", __LINE__));
88 PMCDBG1(MDP,INI,0, "intel-initialize cpuid=0x%x", cpu_id);
94 model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4);
95 stepping = cpu_id & 0xF;
97 snprintf(pmc_cpuid, sizeof(pmc_cpuid), "GenuineIntel-%d-%02X",
98 (cpu_id & 0xF00) >> 8, model);
99 switch (cpu_id & 0xF00) {
100 case 0x600: /* Pentium Pro, Celeron, Pentium II & III */
103 cputype = PMC_CPU_INTEL_CORE;
106 /* Per Intel document 315338-020. */
107 if (stepping == 0x7) {
108 cputype = PMC_CPU_INTEL_CORE;
111 cputype = PMC_CPU_INTEL_CORE2;
116 cputype = PMC_CPU_INTEL_CORE2EXTREME;
119 case 0x1C: /* Per Intel document 320047-002. */
120 cputype = PMC_CPU_INTEL_ATOM;
125 * Per Intel document 253669-032 9/2009,
129 * Per Intel document 253669-032 9/2009,
132 cputype = PMC_CPU_INTEL_COREI7;
136 cputype = PMC_CPU_INTEL_NEHALEM_EX;
139 case 0x25: /* Per Intel document 253669-033US 12/2009. */
140 case 0x2C: /* Per Intel document 253669-033US 12/2009. */
141 cputype = PMC_CPU_INTEL_WESTMERE;
144 case 0x2F: /* Westmere-EX, seen in wild */
145 cputype = PMC_CPU_INTEL_WESTMERE_EX;
148 case 0x2A: /* Per Intel document 253669-039US 05/2011. */
149 cputype = PMC_CPU_INTEL_SANDYBRIDGE;
152 case 0x2D: /* Per Intel document 253669-044US 08/2012. */
153 cputype = PMC_CPU_INTEL_SANDYBRIDGE_XEON;
156 case 0x3A: /* Per Intel document 253669-043US 05/2012. */
157 cputype = PMC_CPU_INTEL_IVYBRIDGE;
160 case 0x3E: /* Per Intel document 325462-045US 01/2013. */
161 cputype = PMC_CPU_INTEL_IVYBRIDGE_XEON;
168 case 0x8E: /* Per Intel document 325462-063US July 2017. */
169 case 0x9E: /* Per Intel document 325462-063US July 2017. */
170 cputype = PMC_CPU_INTEL_SKYLAKE;
173 case 0x55: /* SDM rev 63 */
174 cputype = PMC_CPU_INTEL_SKYLAKE_XEON;
179 cputype = PMC_CPU_INTEL_BROADWELL;
184 cputype = PMC_CPU_INTEL_BROADWELL_XEON;
187 case 0x3F: /* Per Intel document 325462-045US 09/2014. */
188 case 0x46: /* Per Intel document 325462-045US 09/2014. */
189 /* Should 46 be XEON. probably its own? */
190 cputype = PMC_CPU_INTEL_HASWELL_XEON;
193 case 0x3C: /* Per Intel document 325462-045US 01/2013. */
194 case 0x45: /* Per Intel document 325462-045US 09/2014. */
195 cputype = PMC_CPU_INTEL_HASWELL;
198 case 0x4D: /* Per Intel document 330061-001 01/2014. */
199 cputype = PMC_CPU_INTEL_ATOM_SILVERMONT;
207 if ((int) cputype == -1) {
208 printf("pmc: Unknown Intel CPU.\n");
212 /* Allocate base class and initialize machine dependent struct */
213 pmc_mdep = pmc_mdep_alloc(nclasses);
215 pmc_mdep->pmd_cputype = cputype;
216 pmc_mdep->pmd_switch_in = intel_switch_in;
217 pmc_mdep->pmd_switch_out = intel_switch_out;
219 ncpus = pmc_cpu_max();
220 error = pmc_tsc_initialize(pmc_mdep, ncpus);
225 * Intel Core, Core 2 and Atom processors.
227 case PMC_CPU_INTEL_ATOM:
228 case PMC_CPU_INTEL_ATOM_SILVERMONT:
229 case PMC_CPU_INTEL_BROADWELL:
230 case PMC_CPU_INTEL_BROADWELL_XEON:
231 case PMC_CPU_INTEL_SKYLAKE_XEON:
232 case PMC_CPU_INTEL_SKYLAKE:
233 case PMC_CPU_INTEL_CORE:
234 case PMC_CPU_INTEL_CORE2:
235 case PMC_CPU_INTEL_CORE2EXTREME:
236 case PMC_CPU_INTEL_COREI7:
237 case PMC_CPU_INTEL_NEHALEM_EX:
238 case PMC_CPU_INTEL_IVYBRIDGE:
239 case PMC_CPU_INTEL_SANDYBRIDGE:
240 case PMC_CPU_INTEL_WESTMERE:
241 case PMC_CPU_INTEL_WESTMERE_EX:
242 case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
243 case PMC_CPU_INTEL_IVYBRIDGE_XEON:
244 case PMC_CPU_INTEL_HASWELL:
245 case PMC_CPU_INTEL_HASWELL_XEON:
246 error = pmc_core_initialize(pmc_mdep, ncpus, verov);
250 KASSERT(0, ("[intel,%d] Unknown CPU type", __LINE__));
254 pmc_tsc_finalize(pmc_mdep);
259 * Init the uncore class.
263 * Intel Corei7 and Westmere processors.
265 case PMC_CPU_INTEL_COREI7:
266 case PMC_CPU_INTEL_HASWELL:
267 case PMC_CPU_INTEL_SANDYBRIDGE:
268 case PMC_CPU_INTEL_WESTMERE:
269 case PMC_CPU_INTEL_BROADWELL:
270 error = pmc_uncore_initialize(pmc_mdep, ncpus);
277 pmc_mdep_free(pmc_mdep);
285 pmc_intel_finalize(struct pmc_mdep *md)
287 pmc_tsc_finalize(md);
289 switch (md->pmd_cputype) {
290 case PMC_CPU_INTEL_ATOM:
291 case PMC_CPU_INTEL_ATOM_SILVERMONT:
292 case PMC_CPU_INTEL_BROADWELL:
293 case PMC_CPU_INTEL_BROADWELL_XEON:
294 case PMC_CPU_INTEL_SKYLAKE_XEON:
295 case PMC_CPU_INTEL_SKYLAKE:
296 case PMC_CPU_INTEL_CORE:
297 case PMC_CPU_INTEL_CORE2:
298 case PMC_CPU_INTEL_CORE2EXTREME:
299 case PMC_CPU_INTEL_COREI7:
300 case PMC_CPU_INTEL_NEHALEM_EX:
301 case PMC_CPU_INTEL_HASWELL:
302 case PMC_CPU_INTEL_HASWELL_XEON:
303 case PMC_CPU_INTEL_IVYBRIDGE:
304 case PMC_CPU_INTEL_SANDYBRIDGE:
305 case PMC_CPU_INTEL_WESTMERE:
306 case PMC_CPU_INTEL_WESTMERE_EX:
307 case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
308 case PMC_CPU_INTEL_IVYBRIDGE_XEON:
309 pmc_core_finalize(md);
312 KASSERT(0, ("[intel,%d] unknown CPU type", __LINE__));
318 switch (md->pmd_cputype) {
319 case PMC_CPU_INTEL_BROADWELL:
320 case PMC_CPU_INTEL_COREI7:
321 case PMC_CPU_INTEL_HASWELL:
322 case PMC_CPU_INTEL_SANDYBRIDGE:
323 case PMC_CPU_INTEL_WESTMERE:
324 pmc_uncore_finalize(md);