2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2008 Joseph Koshy
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * Common code for handling Intel CPUs.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #include <sys/param.h>
38 #include <sys/pmckern.h>
39 #include <sys/systm.h>
41 #include <machine/cpu.h>
42 #include <machine/cputypes.h>
43 #include <machine/md_var.h>
44 #include <machine/specialreg.h>
47 intel_switch_in(struct pmc_cpu *pc, struct pmc_process *pp)
51 PMCDBG3(MDP,SWI,1, "pc=%p pp=%p enable-msr=%d", pc, pp,
52 pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS);
54 /* allow the RDPMC instruction if needed */
55 if (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS)
56 load_cr4(rcr4() | CR4_PCE);
58 PMCDBG1(MDP,SWI,1, "cr4=0x%jx", (uintmax_t) rcr4());
64 intel_switch_out(struct pmc_cpu *pc, struct pmc_process *pp)
67 (void) pp; /* can be NULL */
69 PMCDBG3(MDP,SWO,1, "pc=%p pp=%p cr4=0x%jx", pc, pp,
72 /* always turn off the RDPMC instruction */
73 load_cr4(rcr4() & ~CR4_PCE);
79 pmc_intel_initialize(void)
81 struct pmc_mdep *pmc_mdep;
82 enum pmc_cputype cputype;
83 int error, model, nclasses, ncpus, stepping, verov;
85 KASSERT(cpu_vendor_id == CPU_VENDOR_INTEL,
86 ("[intel,%d] Initializing non-intel processor", __LINE__));
88 PMCDBG1(MDP,INI,0, "intel-initialize cpuid=0x%x", cpu_id);
94 model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4);
95 stepping = cpu_id & 0xF;
97 switch (cpu_id & 0xF00) {
99 case 0x500: /* Pentium family processors */
100 cputype = PMC_CPU_INTEL_P5;
103 case 0x600: /* Pentium Pro, Celeron, Pentium II & III */
105 #if defined(__i386__)
107 cputype = PMC_CPU_INTEL_P6;
110 cputype = PMC_CPU_INTEL_PII;
113 cputype = PMC_CPU_INTEL_CL;
115 case 0x7: case 0x8: case 0xA: case 0xB:
116 cputype = PMC_CPU_INTEL_PIII;
119 cputype = PMC_CPU_INTEL_PM;
123 cputype = PMC_CPU_INTEL_CORE;
126 /* Per Intel document 315338-020. */
127 if (stepping == 0x7) {
128 cputype = PMC_CPU_INTEL_CORE;
131 cputype = PMC_CPU_INTEL_CORE2;
136 cputype = PMC_CPU_INTEL_CORE2EXTREME;
139 case 0x1C: /* Per Intel document 320047-002. */
140 cputype = PMC_CPU_INTEL_ATOM;
145 * Per Intel document 253669-032 9/2009,
149 * Per Intel document 253669-032 9/2009,
152 cputype = PMC_CPU_INTEL_COREI7;
156 cputype = PMC_CPU_INTEL_NEHALEM_EX;
159 case 0x25: /* Per Intel document 253669-033US 12/2009. */
160 case 0x2C: /* Per Intel document 253669-033US 12/2009. */
161 cputype = PMC_CPU_INTEL_WESTMERE;
164 case 0x2F: /* Westmere-EX, seen in wild */
165 cputype = PMC_CPU_INTEL_WESTMERE_EX;
168 case 0x2A: /* Per Intel document 253669-039US 05/2011. */
169 cputype = PMC_CPU_INTEL_SANDYBRIDGE;
172 case 0x2D: /* Per Intel document 253669-044US 08/2012. */
173 cputype = PMC_CPU_INTEL_SANDYBRIDGE_XEON;
176 case 0x3A: /* Per Intel document 253669-043US 05/2012. */
177 cputype = PMC_CPU_INTEL_IVYBRIDGE;
180 case 0x3E: /* Per Intel document 325462-045US 01/2013. */
181 cputype = PMC_CPU_INTEL_IVYBRIDGE_XEON;
188 case 0x8E: /* Per Intel document 325462-063US July 2017. */
189 case 0x9E: /* Per Intel document 325462-063US July 2017. */
190 cputype = PMC_CPU_INTEL_SKYLAKE;
193 case 0x55: /* SDM rev 63 */
194 cputype = PMC_CPU_INTEL_SKYLAKE_XEON;
199 cputype = PMC_CPU_INTEL_BROADWELL;
204 cputype = PMC_CPU_INTEL_BROADWELL_XEON;
207 case 0x3F: /* Per Intel document 325462-045US 09/2014. */
208 case 0x46: /* Per Intel document 325462-045US 09/2014. */
209 /* Should 46 be XEON. probably its own? */
210 cputype = PMC_CPU_INTEL_HASWELL_XEON;
213 case 0x3C: /* Per Intel document 325462-045US 01/2013. */
214 case 0x45: /* Per Intel document 325462-045US 09/2014. */
215 cputype = PMC_CPU_INTEL_HASWELL;
218 case 0x4D: /* Per Intel document 330061-001 01/2014. */
219 cputype = PMC_CPU_INTEL_ATOM_SILVERMONT;
224 #if defined(__i386__) || defined(__amd64__)
226 if (model >= 0 && model <= 6) /* known models */
227 cputype = PMC_CPU_INTEL_PIV;
232 if ((int) cputype == -1) {
233 printf("pmc: Unknown Intel CPU.\n");
237 /* Allocate base class and initialize machine dependent struct */
238 pmc_mdep = pmc_mdep_alloc(nclasses);
240 pmc_mdep->pmd_cputype = cputype;
241 pmc_mdep->pmd_switch_in = intel_switch_in;
242 pmc_mdep->pmd_switch_out = intel_switch_out;
244 ncpus = pmc_cpu_max();
245 error = pmc_tsc_initialize(pmc_mdep, ncpus);
249 #if defined(__i386__) || defined(__amd64__)
251 * Intel Core, Core 2 and Atom processors.
253 case PMC_CPU_INTEL_ATOM:
254 case PMC_CPU_INTEL_ATOM_SILVERMONT:
255 case PMC_CPU_INTEL_BROADWELL:
256 case PMC_CPU_INTEL_BROADWELL_XEON:
257 case PMC_CPU_INTEL_SKYLAKE_XEON:
258 case PMC_CPU_INTEL_SKYLAKE:
259 case PMC_CPU_INTEL_CORE:
260 case PMC_CPU_INTEL_CORE2:
261 case PMC_CPU_INTEL_CORE2EXTREME:
262 case PMC_CPU_INTEL_COREI7:
263 case PMC_CPU_INTEL_NEHALEM_EX:
264 case PMC_CPU_INTEL_IVYBRIDGE:
265 case PMC_CPU_INTEL_SANDYBRIDGE:
266 case PMC_CPU_INTEL_WESTMERE:
267 case PMC_CPU_INTEL_WESTMERE_EX:
268 case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
269 case PMC_CPU_INTEL_IVYBRIDGE_XEON:
270 case PMC_CPU_INTEL_HASWELL:
271 case PMC_CPU_INTEL_HASWELL_XEON:
272 error = pmc_core_initialize(pmc_mdep, ncpus, verov);
276 * Intel Pentium 4 Processors, and P4/EMT64 processors.
279 case PMC_CPU_INTEL_PIV:
280 error = pmc_p4_initialize(pmc_mdep, ncpus);
284 #if defined(__i386__)
286 * P6 Family Processors
289 case PMC_CPU_INTEL_P6:
290 case PMC_CPU_INTEL_CL:
291 case PMC_CPU_INTEL_PII:
292 case PMC_CPU_INTEL_PIII:
293 case PMC_CPU_INTEL_PM:
294 error = pmc_p6_initialize(pmc_mdep, ncpus);
298 * Intel Pentium PMCs.
301 case PMC_CPU_INTEL_P5:
302 error = pmc_p5_initialize(pmc_mdep, ncpus);
307 KASSERT(0, ("[intel,%d] Unknown CPU type", __LINE__));
311 pmc_tsc_finalize(pmc_mdep);
316 * Init the uncore class.
318 #if defined(__i386__) || defined(__amd64__)
321 * Intel Corei7 and Westmere processors.
323 case PMC_CPU_INTEL_COREI7:
324 case PMC_CPU_INTEL_HASWELL:
325 case PMC_CPU_INTEL_SANDYBRIDGE:
326 case PMC_CPU_INTEL_WESTMERE:
327 case PMC_CPU_INTEL_BROADWELL:
328 error = pmc_uncore_initialize(pmc_mdep, ncpus);
336 pmc_mdep_free(pmc_mdep);
344 pmc_intel_finalize(struct pmc_mdep *md)
346 pmc_tsc_finalize(md);
348 switch (md->pmd_cputype) {
349 #if defined(__i386__) || defined(__amd64__)
350 case PMC_CPU_INTEL_ATOM:
351 case PMC_CPU_INTEL_ATOM_SILVERMONT:
352 case PMC_CPU_INTEL_BROADWELL:
353 case PMC_CPU_INTEL_BROADWELL_XEON:
354 case PMC_CPU_INTEL_SKYLAKE_XEON:
355 case PMC_CPU_INTEL_SKYLAKE:
356 case PMC_CPU_INTEL_CORE:
357 case PMC_CPU_INTEL_CORE2:
358 case PMC_CPU_INTEL_CORE2EXTREME:
359 case PMC_CPU_INTEL_COREI7:
360 case PMC_CPU_INTEL_NEHALEM_EX:
361 case PMC_CPU_INTEL_HASWELL:
362 case PMC_CPU_INTEL_HASWELL_XEON:
363 case PMC_CPU_INTEL_IVYBRIDGE:
364 case PMC_CPU_INTEL_SANDYBRIDGE:
365 case PMC_CPU_INTEL_WESTMERE:
366 case PMC_CPU_INTEL_WESTMERE_EX:
367 case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
368 case PMC_CPU_INTEL_IVYBRIDGE_XEON:
369 pmc_core_finalize(md);
372 case PMC_CPU_INTEL_PIV:
376 #if defined(__i386__)
377 case PMC_CPU_INTEL_P6:
378 case PMC_CPU_INTEL_CL:
379 case PMC_CPU_INTEL_PII:
380 case PMC_CPU_INTEL_PIII:
381 case PMC_CPU_INTEL_PM:
384 case PMC_CPU_INTEL_P5:
389 KASSERT(0, ("[intel,%d] unknown CPU type", __LINE__));
395 #if defined(__i386__) || defined(__amd64__)
396 switch (md->pmd_cputype) {
397 case PMC_CPU_INTEL_BROADWELL:
398 case PMC_CPU_INTEL_COREI7:
399 case PMC_CPU_INTEL_HASWELL:
400 case PMC_CPU_INTEL_SANDYBRIDGE:
401 case PMC_CPU_INTEL_WESTMERE:
402 pmc_uncore_finalize(md);