sys/dev/hwpmc/hwpmc_mips.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 2010, George V. Neville-Neil <gnn@freebsd.org>
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  *
  28  */
  29
  30 #include <sys/cdefs.h>
  31 __FBSDID("$FreeBSD$");
  32
  33 #include "opt_hwpmc_hooks.h"
  34
  35 #include <sys/param.h>
  36 #include <sys/pmc.h>
  37 #include <sys/pmckern.h>
  38 #include <sys/systm.h>
  39
  40 #include <machine/pmc_mdep.h>
  41 #include <machine/md_var.h>
  42 #include <machine/mips_opcode.h>
  43 #include <machine/vmparam.h>
  44
  45 int mips_npmcs;
  46
  47 /*
  48  * Per-processor information.
  49  */
  50 struct mips_cpu {
  51         struct pmc_hw   *pc_mipspmcs;
  52 };
  53
  54 static struct mips_cpu **mips_pcpu;
  55
  56 #if defined(__mips_n64)
  57 #       define  MIPS_IS_VALID_KERNELADDR(reg)   ((((reg) & 3) == 0) && \
  58                                         ((vm_offset_t)(reg) >= MIPS_XKPHYS_START))
  59 #else
  60 #       define  MIPS_IS_VALID_KERNELADDR(reg)   ((((reg) & 3) == 0) && \
  61                                         ((vm_offset_t)(reg) >= MIPS_KSEG0_START))
  62 #endif
  63
  64 /*
  65  * We need some reasonable default to prevent backtrace code
  66  * from wandering too far
  67  */
  68 #define MAX_FUNCTION_SIZE 0x10000
  69 #define MAX_PROLOGUE_SIZE 0x100
  70
  71 static int
  72 mips_allocate_pmc(int cpu, int ri, struct pmc *pm,
  73   const struct pmc_op_pmcallocate *a)
  74 {
  75         enum pmc_event pe;
  76         uint32_t caps, config, counter;
  77         uint32_t event;
  78         int i;
  79
  80         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
  81             ("[mips,%d] illegal CPU value %d", __LINE__, cpu));
  82         KASSERT(ri >= 0 && ri < mips_npmcs,
  83             ("[mips,%d] illegal row index %d", __LINE__, ri));
  84
  85         caps = a->pm_caps;
  86         if (a->pm_class != mips_pmc_spec.ps_cpuclass)
  87                 return (EINVAL);
  88         pe = a->pm_ev;
  89         counter = MIPS_CTR_ALL;
  90         event = 0;
  91         for (i = 0; i < mips_event_codes_size; i++) {
  92                 if (mips_event_codes[i].pe_ev == pe) {
  93                         event = mips_event_codes[i].pe_code;
  94                         counter =  mips_event_codes[i].pe_counter;
  95                         break;
  96                 }
  97         }
  98
  99         if (i == mips_event_codes_size)
 100                 return (EINVAL);
 101
 102         if ((counter != MIPS_CTR_ALL) && (counter != ri))
 103                 return (EINVAL);
 104
 105         config = mips_get_perfctl(cpu, ri, event, caps);
 106
 107         pm->pm_md.pm_mips_evsel = config;
 108
 109         PMCDBG2(MDP,ALL,2,"mips-allocate ri=%d -> config=0x%x", ri, config);
 110
 111         return 0;
 112 }
 113
 114
 115 static int
 116 mips_read_pmc(int cpu, int ri, pmc_value_t *v)
 117 {
 118         struct pmc *pm;
 119         pmc_value_t tmp;
 120
 121         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 122             ("[mips,%d] illegal CPU value %d", __LINE__, cpu));
 123         KASSERT(ri >= 0 && ri < mips_npmcs,
 124             ("[mips,%d] illegal row index %d", __LINE__, ri));
 125
 126         pm  = mips_pcpu[cpu]->pc_mipspmcs[ri].phw_pmc;
 127         tmp = mips_pmcn_read(ri);
 128         PMCDBG2(MDP,REA,2,"mips-read id=%d -> %jd", ri, tmp);
 129
 130         if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
 131                 *v = tmp - (1UL << (mips_pmc_spec.ps_counter_width - 1));
 132         else
 133                 *v = tmp;
 134
 135         return 0;
 136 }
 137
 138 static int
 139 mips_write_pmc(int cpu, int ri, pmc_value_t v)
 140 {
 141         struct pmc *pm;
 142
 143         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 144             ("[mips,%d] illegal CPU value %d", __LINE__, cpu));
 145         KASSERT(ri >= 0 && ri < mips_npmcs,
 146             ("[mips,%d] illegal row-index %d", __LINE__, ri));
 147
 148         pm  = mips_pcpu[cpu]->pc_mipspmcs[ri].phw_pmc;
 149
 150         if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
 151                 v = (1UL << (mips_pmc_spec.ps_counter_width - 1)) - v;
 152
 153         PMCDBG3(MDP,WRI,1,"mips-write cpu=%d ri=%d v=%jx", cpu, ri, v);
 154
 155         mips_pmcn_write(ri, v);
 156
 157         return 0;
 158 }
 159
 160 static int
 161 mips_config_pmc(int cpu, int ri, struct pmc *pm)
 162 {
 163         struct pmc_hw *phw;
 164
 165         PMCDBG3(MDP,CFG,1, "cpu=%d ri=%d pm=%p", cpu, ri, pm);
 166
 167         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 168             ("[mips,%d] illegal CPU value %d", __LINE__, cpu));
 169         KASSERT(ri >= 0 && ri < mips_npmcs,
 170             ("[mips,%d] illegal row-index %d", __LINE__, ri));
 171
 172         phw = &mips_pcpu[cpu]->pc_mipspmcs[ri];
 173
 174         KASSERT(pm == NULL || phw->phw_pmc == NULL,
 175             ("[mips,%d] pm=%p phw->pm=%p hwpmc not unconfigured",
 176             __LINE__, pm, phw->phw_pmc));
 177
 178         phw->phw_pmc = pm;
 179
 180         return 0;
 181 }
 182
 183 static int
 184 mips_start_pmc(int cpu, int ri)
 185 {
 186         uint32_t config;
 187         struct pmc *pm;
 188         struct pmc_hw *phw;
 189
 190         phw    = &mips_pcpu[cpu]->pc_mipspmcs[ri];
 191         pm     = phw->phw_pmc;
 192         config = pm->pm_md.pm_mips_evsel;
 193
 194         /* Enable the PMC. */
 195         switch (ri) {
 196         case 0:
 197                 mips_wr_perfcnt0(config);
 198                 break;
 199         case 1:
 200                 mips_wr_perfcnt2(config);
 201                 break;
 202         default:
 203                 break;
 204         }
 205
 206         return 0;
 207 }
 208
 209 static int
 210 mips_stop_pmc(int cpu, int ri)
 211 {
 212         struct pmc *pm;
 213         struct pmc_hw *phw;
 214
 215         phw    = &mips_pcpu[cpu]->pc_mipspmcs[ri];
 216         pm     = phw->phw_pmc;
 217
 218         /*
 219          * Disable the PMCs.
 220          *
 221          * Clearing the entire register turns the counter off as well
 222          * as removes the previously sampled event.
 223          */
 224         switch (ri) {
 225         case 0:
 226                 mips_wr_perfcnt0(0);
 227                 break;
 228         case 1:
 229                 mips_wr_perfcnt2(0);
 230                 break;
 231         default:
 232                 break;
 233         }
 234         return 0;
 235 }
 236
 237 static int
 238 mips_release_pmc(int cpu, int ri, struct pmc *pmc)
 239 {
 240         struct pmc_hw *phw;
 241
 242         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 243             ("[mips,%d] illegal CPU value %d", __LINE__, cpu));
 244         KASSERT(ri >= 0 && ri < mips_npmcs,
 245             ("[mips,%d] illegal row-index %d", __LINE__, ri));
 246
 247         phw = &mips_pcpu[cpu]->pc_mipspmcs[ri];
 248         KASSERT(phw->phw_pmc == NULL,
 249             ("[mips,%d] PHW pmc %p non-NULL", __LINE__, phw->phw_pmc));
 250
 251         return 0;
 252 }
 253
 254 static int
 255 mips_pmc_intr(int cpu, struct trapframe *tf)
 256 {
 257         int error;
 258         int retval, ri;
 259         struct pmc *pm;
 260         struct mips_cpu *pc;
 261         uint32_t r0, r2;
 262         pmc_value_t r;
 263
 264         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 265             ("[mips,%d] CPU %d out of range", __LINE__, cpu));
 266
 267         retval = 0;
 268         pc = mips_pcpu[cpu];
 269
 270         /* Stop PMCs without clearing the counter */
 271         r0 = mips_rd_perfcnt0();
 272         mips_wr_perfcnt0(r0 & ~(0x1f));
 273         r2 = mips_rd_perfcnt2();
 274         mips_wr_perfcnt2(r2 & ~(0x1f));
 275
 276         for (ri = 0; ri < mips_npmcs; ri++) {
 277                 pm = mips_pcpu[cpu]->pc_mipspmcs[ri].phw_pmc;
 278                 if (pm == NULL)
 279                         continue;
 280                 if (! PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
 281                         continue;
 282
 283                 r = mips_pmcn_read(ri);
 284
 285                 /* If bit 31 is set, the counter has overflowed */
 286                 if ((r & (1UL << (mips_pmc_spec.ps_counter_width - 1))) == 0)
 287                         continue;
 288
 289                 retval = 1;
 290                 if (pm->pm_state != PMC_STATE_RUNNING)
 291                         continue;
 292                 error = pmc_process_interrupt(PMC_HR, pm, tf);
 293                 if (error) {
 294                         /* Clear/disable the relevant counter */
 295                         if (ri == 0)
 296                                 r0 = 0;
 297                         else if (ri == 1)
 298                                 r2 = 0;
 299                         mips_stop_pmc(cpu, ri);
 300                 }
 301
 302                 /* Reload sampling count */
 303                 mips_write_pmc(cpu, ri, pm->pm_sc.pm_reloadcount);
 304         }
 305
 306         /*
 307          * Re-enable the PMC counters where they left off.
 308          *
 309          * Any counter which overflowed will have its sample count
 310          * reloaded in the loop above.
 311          */
 312         mips_wr_perfcnt0(r0);
 313         mips_wr_perfcnt2(r2);
 314
 315         return retval;
 316 }
 317
 318 static int
 319 mips_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
 320 {
 321         int error;
 322         struct pmc_hw *phw;
 323         char mips_name[PMC_NAME_MAX];
 324
 325         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 326             ("[mips,%d], illegal CPU %d", __LINE__, cpu));
 327         KASSERT(ri >= 0 && ri < mips_npmcs,
 328             ("[mips,%d] row-index %d out of range", __LINE__, ri));
 329
 330         phw = &mips_pcpu[cpu]->pc_mipspmcs[ri];
 331         snprintf(mips_name, sizeof(mips_name), "MIPS-%d", ri);
 332         if ((error = copystr(mips_name, pi->pm_name, PMC_NAME_MAX,
 333             NULL)) != 0)
 334                 return error;
 335         pi->pm_class = mips_pmc_spec.ps_cpuclass;
 336         if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
 337                 pi->pm_enabled = TRUE;
 338                 *ppmc          = phw->phw_pmc;
 339         } else {
 340                 pi->pm_enabled = FALSE;
 341                 *ppmc          = NULL;
 342         }
 343
 344         return (0);
 345 }
 346
 347 static int
 348 mips_get_config(int cpu, int ri, struct pmc **ppm)
 349 {
 350         *ppm = mips_pcpu[cpu]->pc_mipspmcs[ri].phw_pmc;
 351
 352         return 0;
 353 }
 354
 355 /*
 356  * XXX don't know what we should do here.
 357  */
 358 static int
 359 mips_pmc_switch_in(struct pmc_cpu *pc, struct pmc_process *pp)
 360 {
 361         return 0;
 362 }
 363
 364 static int
 365 mips_pmc_switch_out(struct pmc_cpu *pc, struct pmc_process *pp)
 366 {
 367         return 0;
 368 }
 369
 370 static int
 371 mips_pcpu_init(struct pmc_mdep *md, int cpu)
 372 {
 373         int first_ri, i;
 374         struct pmc_cpu *pc;
 375         struct mips_cpu *pac;
 376         struct pmc_hw  *phw;
 377
 378         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 379             ("[mips,%d] wrong cpu number %d", __LINE__, cpu));
 380         PMCDBG1(MDP,INI,1,"mips-init cpu=%d", cpu);
 381
 382         mips_pcpu[cpu] = pac = malloc(sizeof(struct mips_cpu), M_PMC,
 383             M_WAITOK|M_ZERO);
 384         pac->pc_mipspmcs = malloc(sizeof(struct pmc_hw) * mips_npmcs,
 385             M_PMC, M_WAITOK|M_ZERO);
 386         pc = pmc_pcpu[cpu];
 387         first_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_MIPS].pcd_ri;
 388         KASSERT(pc != NULL, ("[mips,%d] NULL per-cpu pointer", __LINE__));
 389
 390         for (i = 0, phw = pac->pc_mipspmcs; i < mips_npmcs; i++, phw++) {
 391                 phw->phw_state    = PMC_PHW_FLAG_IS_ENABLED |
 392                     PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(i);
 393                 phw->phw_pmc      = NULL;
 394                 pc->pc_hwpmcs[i + first_ri] = phw;
 395         }
 396
 397         /*
 398          * Clear the counter control register which has the effect
 399          * of disabling counting.
 400          */
 401         for (i = 0; i < mips_npmcs; i++)
 402                 mips_pmcn_write(i, 0);
 403
 404         return 0;
 405 }
 406
 407 static int
 408 mips_pcpu_fini(struct pmc_mdep *md, int cpu)
 409 {
 410         return 0;
 411 }
 412
 413 struct pmc_mdep *
 414 pmc_mips_initialize()
 415 {
 416         struct pmc_mdep *pmc_mdep;
 417         struct pmc_classdep *pcd;
 418
 419         /*
 420          * TODO: Use More bit of PerfCntlX register to detect actual
 421          * number of counters
 422          */
 423         mips_npmcs = 2;
 424
 425         PMCDBG1(MDP,INI,1,"mips-init npmcs=%d", mips_npmcs);
 426
 427         /*
 428          * Allocate space for pointers to PMC HW descriptors and for
 429          * the MDEP structure used by MI code.
 430          */
 431         mips_pcpu = malloc(sizeof(struct mips_cpu *) * pmc_cpu_max(), M_PMC,
 432                            M_WAITOK|M_ZERO);
 433
 434         /* Just one class */
 435         pmc_mdep = pmc_mdep_alloc(1);
 436
 437         pmc_mdep->pmd_cputype = mips_pmc_spec.ps_cputype;
 438
 439         pcd = &pmc_mdep->pmd_classdep[PMC_MDEP_CLASS_INDEX_MIPS];
 440         pcd->pcd_caps  = mips_pmc_spec.ps_capabilities;
 441         pcd->pcd_class = mips_pmc_spec.ps_cpuclass;
 442         pcd->pcd_num   = mips_npmcs;
 443         pcd->pcd_ri    = pmc_mdep->pmd_npmc;
 444         pcd->pcd_width = mips_pmc_spec.ps_counter_width;
 445
 446         pcd->pcd_allocate_pmc   = mips_allocate_pmc;
 447         pcd->pcd_config_pmc     = mips_config_pmc;
 448         pcd->pcd_pcpu_fini      = mips_pcpu_fini;
 449         pcd->pcd_pcpu_init      = mips_pcpu_init;
 450         pcd->pcd_describe       = mips_describe;
 451         pcd->pcd_get_config     = mips_get_config;
 452         pcd->pcd_read_pmc       = mips_read_pmc;
 453         pcd->pcd_release_pmc    = mips_release_pmc;
 454         pcd->pcd_start_pmc      = mips_start_pmc;
 455         pcd->pcd_stop_pmc       = mips_stop_pmc;
 456         pcd->pcd_write_pmc      = mips_write_pmc;
 457
 458         pmc_mdep->pmd_intr       = mips_pmc_intr;
 459         pmc_mdep->pmd_switch_in  = mips_pmc_switch_in;
 460         pmc_mdep->pmd_switch_out = mips_pmc_switch_out;
 461
 462         pmc_mdep->pmd_npmc   += mips_npmcs;
 463
 464         return (pmc_mdep);
 465 }
 466
 467 void
 468 pmc_mips_finalize(struct pmc_mdep *md)
 469 {
 470         (void) md;
 471 }
 472
 473 #ifdef  HWPMC_MIPS_BACKTRACE
 474
 475 static int
 476 pmc_next_frame(register_t *pc, register_t *sp)
 477 {
 478         InstFmt i;
 479         uintptr_t va;
 480         uint32_t instr, mask;
 481         int more, stksize;
 482         register_t ra = 0;
 483
 484         /* Jump here after a nonstandard (interrupt handler) frame */
 485         stksize = 0;
 486
 487         /* check for bad SP: could foul up next frame */
 488         if (!MIPS_IS_VALID_KERNELADDR(*sp)) {
 489                 goto error;
 490         }
 491
 492         /* check for bad PC */
 493         if (!MIPS_IS_VALID_KERNELADDR(*pc)) {
 494                 goto error;
 495         }
 496
 497         /*
 498          * Find the beginning of the current subroutine by scanning
 499          * backwards from the current PC for the end of the previous
 500          * subroutine.
 501          */
 502         va = *pc - sizeof(int);
 503         while (1) {
 504                 instr = *((uint32_t *)va);
 505
 506                 /* [d]addiu sp,sp,-X */
 507                 if (((instr & 0xffff8000) == 0x27bd8000)
 508                     || ((instr & 0xffff8000) == 0x67bd8000))
 509                         break;
 510
 511                 /* jr   ra */
 512                 if (instr == 0x03e00008) {
 513                         /* skip over branch-delay slot instruction */
 514                         va += 2 * sizeof(int);
 515                         break;
 516                 }
 517
 518                 va -= sizeof(int);
 519         }
 520
 521         /* skip over nulls which might separate .o files */
 522         while ((instr = *((uint32_t *)va)) == 0)
 523                 va += sizeof(int);
 524
 525         /* scan forwards to find stack size and any saved registers */
 526         stksize = 0;
 527         more = 3;
 528         mask = 0;
 529         for (; more; va += sizeof(int),
 530             more = (more == 3) ? 3 : more - 1) {
 531                 /* stop if hit our current position */
 532                 if (va >= *pc)
 533                         break;
 534                 instr = *((uint32_t *)va);
 535                 i.word = instr;
 536                 switch (i.JType.op) {
 537                 case OP_SPECIAL:
 538                         switch (i.RType.func) {
 539                         case OP_JR:
 540                         case OP_JALR:
 541                                 more = 2;       /* stop after next instruction */
 542                                 break;
 543
 544                         case OP_SYSCALL:
 545                         case OP_BREAK:
 546                                 more = 1;       /* stop now */
 547                         }
 548                         break;
 549
 550                 case OP_BCOND:
 551                 case OP_J:
 552                 case OP_JAL:
 553                 case OP_BEQ:
 554                 case OP_BNE:
 555                 case OP_BLEZ:
 556                 case OP_BGTZ:
 557                         more = 2;       /* stop after next instruction */
 558                         break;
 559
 560                 case OP_COP0:
 561                 case OP_COP1:
 562                 case OP_COP2:
 563                 case OP_COP3:
 564                         switch (i.RType.rs) {
 565                         case OP_BCx:
 566                         case OP_BCy:
 567                                 more = 2;       /* stop after next instruction */
 568                         }
 569                         break;
 570
 571                 case OP_SW:
 572                 case OP_SD:
 573                         /*
 574                          * SP is being saved using S8(FP). Most likely it indicates
 575                          * that SP is modified in the function and we can't get
 576                          * its value safely without emulating code backward
 577                          * So just bail out on functions like this
 578                          */
 579                         if ((i.IType.rs == 30) && (i.IType.rt = 29))
 580                                 return (-1);
 581
 582                         /* look for saved registers on the stack */
 583                         if (i.IType.rs != 29)
 584                                 break;
 585                         /* only restore the first one */
 586                         if (mask & (1 << i.IType.rt))
 587                                 break;
 588                         mask |= (1 << i.IType.rt);
 589                         if (i.IType.rt == 31)
 590                                 ra = *((register_t *)(*sp + (short)i.IType.imm));
 591                         break;
 592
 593                 case OP_ADDI:
 594                 case OP_ADDIU:
 595                 case OP_DADDI:
 596                 case OP_DADDIU:
 597                         /* look for stack pointer adjustment */
 598                         if (i.IType.rs != 29 || i.IType.rt != 29)
 599                                 break;
 600                         stksize = -((short)i.IType.imm);
 601                 }
 602         }
 603
 604         if (!MIPS_IS_VALID_KERNELADDR(ra))
 605                 return (-1);
 606
 607         *pc = ra;
 608         *sp += stksize;
 609
 610         return (0);
 611
 612 error:
 613         return (-1);
 614 }
 615
 616 static int
 617 pmc_next_uframe(register_t *pc, register_t *sp, register_t *ra)
 618 {
 619         int offset, registers_on_stack;
 620         uint32_t opcode, mask;
 621         register_t function_start;
 622         int stksize;
 623         InstFmt i;
 624
 625         registers_on_stack = 0;
 626         mask = 0;
 627         function_start = 0;
 628         offset = 0;
 629         stksize = 0;
 630
 631         while (offset < MAX_FUNCTION_SIZE) {
 632                 opcode = fuword32((void *)(*pc - offset));
 633
 634                 /* [d]addiu sp, sp, -X*/
 635                 if (((opcode & 0xffff8000) == 0x27bd8000)
 636                     || ((opcode & 0xffff8000) == 0x67bd8000)) {
 637                         function_start = *pc - offset;
 638                         registers_on_stack = 1;
 639                         break;
 640                 }
 641
 642                 /* lui gp, X */
 643                 if ((opcode & 0xffff8000) == 0x3c1c0000) {
 644                         /*
 645                          * Function might start with this instruction
 646                          * Keep an eye on "jr ra" and sp correction
 647                          * with positive value further on
 648                          */
 649                         function_start = *pc - offset;
 650                 }
 651
 652                 if (function_start) {
 653                         /*
 654                          * Stop looking further. Possible end of
 655                          * function instruction: it means there is no
 656                          * stack modifications, sp is unchanged
 657                          */
 658
 659                         /* [d]addiu sp,sp,X */
 660                         if (((opcode & 0xffff8000) == 0x27bd0000)
 661                             || ((opcode & 0xffff8000) == 0x67bd0000))
 662                                 break;
 663
 664                         if (opcode == 0x03e00008)
 665                                 break;
 666                 }
 667
 668                 offset += sizeof(int);
 669         }
 670
 671         if (!function_start)
 672                 return (-1);
 673
 674         if (registers_on_stack) {
 675                 offset = 0;
 676                 while ((offset < MAX_PROLOGUE_SIZE)
 677                     && ((function_start + offset) < *pc)) {
 678                         i.word = fuword32((void *)(function_start + offset));
 679                         switch (i.JType.op) {
 680                         case OP_SW:
 681                                 /* look for saved registers on the stack */
 682                                 if (i.IType.rs != 29)
 683                                         break;
 684                                 /* only restore the first one */
 685                                 if (mask & (1 << i.IType.rt))
 686                                         break;
 687                                 mask |= (1 << i.IType.rt);
 688                                 if (i.IType.rt == 31)
 689                                         *ra = fuword32((void *)(*sp + (short)i.IType.imm));
 690                                 break;
 691
 692 #if defined(__mips_n64)
 693                         case OP_SD:
 694                                 /* look for saved registers on the stack */
 695                                 if (i.IType.rs != 29)
 696                                         break;
 697                                 /* only restore the first one */
 698                                 if (mask & (1 << i.IType.rt))
 699                                         break;
 700                                 mask |= (1 << i.IType.rt);
 701                                 /* ra */
 702                                 if (i.IType.rt == 31)
 703                                         *ra = fuword64((void *)(*sp + (short)i.IType.imm));
 704                         break;
 705 #endif
 706
 707                         case OP_ADDI:
 708                         case OP_ADDIU:
 709                         case OP_DADDI:
 710                         case OP_DADDIU:
 711                                 /* look for stack pointer adjustment */
 712                                 if (i.IType.rs != 29 || i.IType.rt != 29)
 713                                         break;
 714                                 stksize = -((short)i.IType.imm);
 715                         }
 716
 717                         offset += sizeof(int);
 718                 }
 719         }
 720
 721         /*
 722          * We reached the end of backtrace
 723          */
 724         if (*pc == *ra)
 725                 return (-1);
 726
 727         *pc = *ra;
 728         *sp += stksize;
 729
 730         return (0);
 731 }
 732
 733 #endif /* HWPMC_MIPS_BACKTRACE */
 734
 735 struct pmc_mdep *
 736 pmc_md_initialize()
 737 {
 738         return pmc_mips_initialize();
 739 }
 740
 741 void
 742 pmc_md_finalize(struct pmc_mdep *md)
 743 {
 744         return pmc_mips_finalize(md);
 745 }
 746
 747 int
 748 pmc_save_kernel_callchain(uintptr_t *cc, int nframes,
 749     struct trapframe *tf)
 750 {
 751         register_t pc, ra, sp;
 752         int frames = 0;
 753
 754         pc = tf->pc;
 755         sp = tf->sp;
 756         ra = tf->ra;
 757
 758         cc[frames++] = pc;
 759
 760 #ifdef  HWPMC_MIPS_BACKTRACE
 761         /*
 762          * Unwind, and unwind, and unwind
 763          */
 764         while (1) {
 765                 if (frames >= nframes)
 766                         break;
 767
 768                 if (pmc_next_frame(&pc, &sp) < 0)
 769                         break;
 770
 771                 cc[frames++] = pc;
 772         }
 773 #endif
 774
 775         return (frames);
 776 }
 777
 778 int
 779 pmc_save_user_callchain(uintptr_t *cc, int nframes,
 780     struct trapframe *tf)
 781 {
 782         register_t pc, ra, sp;
 783         int frames = 0;
 784
 785         pc = tf->pc;
 786         sp = tf->sp;
 787         ra = tf->ra;
 788
 789         cc[frames++] = pc;
 790
 791 #ifdef  HWPMC_MIPS_BACKTRACE
 792
 793         /*
 794          * Unwind, and unwind, and unwind
 795          */
 796         while (1) {
 797                 if (frames >= nframes)
 798                         break;
 799
 800                 if (pmc_next_uframe(&pc, &sp, &ra) < 0)
 801                         break;
 802
 803                 cc[frames++] = pc;
 804         }
 805 #endif
 806
 807         return (frames);
 808 }