2 * Copyright (c) 2010, George V. Neville-Neil <gnn@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
31 #include "opt_hwpmc_hooks.h"
33 #include <sys/param.h>
35 #include <sys/pmckern.h>
36 #include <sys/systm.h>
38 #include <machine/pmc_mdep.h>
39 #include <machine/md_var.h>
40 #include <machine/mips_opcode.h>
41 #include <machine/vmparam.h>
46 * Per-processor information.
49 struct pmc_hw *pc_mipspmcs;
52 static struct mips_cpu **mips_pcpu;
54 #if defined(__mips_n64)
55 # define MIPS_IS_VALID_KERNELADDR(reg) ((((reg) & 3) == 0) && \
56 ((vm_offset_t)(reg) >= MIPS_XKPHYS_START))
58 # define MIPS_IS_VALID_KERNELADDR(reg) ((((reg) & 3) == 0) && \
59 ((vm_offset_t)(reg) >= MIPS_KSEG0_START))
63 * We need some reasonable default to prevent backtrace code
64 * from wandering too far
66 #define MAX_FUNCTION_SIZE 0x10000
67 #define MAX_PROLOGUE_SIZE 0x100
70 mips_allocate_pmc(int cpu, int ri, struct pmc *pm,
71 const struct pmc_op_pmcallocate *a)
74 uint32_t caps, config, counter;
78 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
79 ("[mips,%d] illegal CPU value %d", __LINE__, cpu));
80 KASSERT(ri >= 0 && ri < mips_npmcs,
81 ("[mips,%d] illegal row index %d", __LINE__, ri));
84 if (a->pm_class != mips_pmc_spec.ps_cpuclass)
87 counter = MIPS_CTR_ALL;
89 for (i = 0; i < mips_event_codes_size; i++) {
90 if (mips_event_codes[i].pe_ev == pe) {
91 event = mips_event_codes[i].pe_code;
92 counter = mips_event_codes[i].pe_counter;
97 if (i == mips_event_codes_size)
100 if ((counter != MIPS_CTR_ALL) && (counter != ri))
103 config = mips_get_perfctl(cpu, ri, event, caps);
105 pm->pm_md.pm_mips_evsel = config;
107 PMCDBG2(MDP,ALL,2,"mips-allocate ri=%d -> config=0x%x", ri, config);
114 mips_read_pmc(int cpu, int ri, pmc_value_t *v)
119 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
120 ("[mips,%d] illegal CPU value %d", __LINE__, cpu));
121 KASSERT(ri >= 0 && ri < mips_npmcs,
122 ("[mips,%d] illegal row index %d", __LINE__, ri));
124 pm = mips_pcpu[cpu]->pc_mipspmcs[ri].phw_pmc;
125 tmp = mips_pmcn_read(ri);
126 PMCDBG2(MDP,REA,2,"mips-read id=%d -> %jd", ri, tmp);
128 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
129 *v = tmp - (1UL << (mips_pmc_spec.ps_counter_width - 1));
137 mips_write_pmc(int cpu, int ri, pmc_value_t v)
141 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
142 ("[mips,%d] illegal CPU value %d", __LINE__, cpu));
143 KASSERT(ri >= 0 && ri < mips_npmcs,
144 ("[mips,%d] illegal row-index %d", __LINE__, ri));
146 pm = mips_pcpu[cpu]->pc_mipspmcs[ri].phw_pmc;
148 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
149 v = (1UL << (mips_pmc_spec.ps_counter_width - 1)) - v;
151 PMCDBG3(MDP,WRI,1,"mips-write cpu=%d ri=%d v=%jx", cpu, ri, v);
153 mips_pmcn_write(ri, v);
159 mips_config_pmc(int cpu, int ri, struct pmc *pm)
163 PMCDBG3(MDP,CFG,1, "cpu=%d ri=%d pm=%p", cpu, ri, pm);
165 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
166 ("[mips,%d] illegal CPU value %d", __LINE__, cpu));
167 KASSERT(ri >= 0 && ri < mips_npmcs,
168 ("[mips,%d] illegal row-index %d", __LINE__, ri));
170 phw = &mips_pcpu[cpu]->pc_mipspmcs[ri];
172 KASSERT(pm == NULL || phw->phw_pmc == NULL,
173 ("[mips,%d] pm=%p phw->pm=%p hwpmc not unconfigured",
174 __LINE__, pm, phw->phw_pmc));
182 mips_start_pmc(int cpu, int ri)
188 phw = &mips_pcpu[cpu]->pc_mipspmcs[ri];
190 config = pm->pm_md.pm_mips_evsel;
192 /* Enable the PMC. */
195 mips_wr_perfcnt0(config);
198 mips_wr_perfcnt2(config);
208 mips_stop_pmc(int cpu, int ri)
213 phw = &mips_pcpu[cpu]->pc_mipspmcs[ri];
219 * Clearing the entire register turns the counter off as well
220 * as removes the previously sampled event.
236 mips_release_pmc(int cpu, int ri, struct pmc *pmc)
240 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
241 ("[mips,%d] illegal CPU value %d", __LINE__, cpu));
242 KASSERT(ri >= 0 && ri < mips_npmcs,
243 ("[mips,%d] illegal row-index %d", __LINE__, ri));
245 phw = &mips_pcpu[cpu]->pc_mipspmcs[ri];
246 KASSERT(phw->phw_pmc == NULL,
247 ("[mips,%d] PHW pmc %p non-NULL", __LINE__, phw->phw_pmc));
253 mips_pmc_intr(int cpu, struct trapframe *tf)
262 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
263 ("[mips,%d] CPU %d out of range", __LINE__, cpu));
268 /* Stop PMCs without clearing the counter */
269 r0 = mips_rd_perfcnt0();
270 mips_wr_perfcnt0(r0 & ~(0x1f));
271 r2 = mips_rd_perfcnt2();
272 mips_wr_perfcnt2(r2 & ~(0x1f));
274 for (ri = 0; ri < mips_npmcs; ri++) {
275 pm = mips_pcpu[cpu]->pc_mipspmcs[ri].phw_pmc;
278 if (! PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
281 r = mips_pmcn_read(ri);
283 /* If bit 31 is set, the counter has overflowed */
284 if ((r & (1UL << (mips_pmc_spec.ps_counter_width - 1))) == 0)
288 if (pm->pm_state != PMC_STATE_RUNNING)
290 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf,
293 /* Clear/disable the relevant counter */
298 mips_stop_pmc(cpu, ri);
301 /* Reload sampling count */
302 mips_write_pmc(cpu, ri, pm->pm_sc.pm_reloadcount);
306 * Re-enable the PMC counters where they left off.
308 * Any counter which overflowed will have its sample count
309 * reloaded in the loop above.
311 mips_wr_perfcnt0(r0);
312 mips_wr_perfcnt2(r2);
318 mips_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
322 char mips_name[PMC_NAME_MAX];
324 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
325 ("[mips,%d], illegal CPU %d", __LINE__, cpu));
326 KASSERT(ri >= 0 && ri < mips_npmcs,
327 ("[mips,%d] row-index %d out of range", __LINE__, ri));
329 phw = &mips_pcpu[cpu]->pc_mipspmcs[ri];
330 snprintf(mips_name, sizeof(mips_name), "MIPS-%d", ri);
331 if ((error = copystr(mips_name, pi->pm_name, PMC_NAME_MAX,
334 pi->pm_class = mips_pmc_spec.ps_cpuclass;
335 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
336 pi->pm_enabled = TRUE;
337 *ppmc = phw->phw_pmc;
339 pi->pm_enabled = FALSE;
347 mips_get_config(int cpu, int ri, struct pmc **ppm)
349 *ppm = mips_pcpu[cpu]->pc_mipspmcs[ri].phw_pmc;
355 * XXX don't know what we should do here.
358 mips_pmc_switch_in(struct pmc_cpu *pc, struct pmc_process *pp)
364 mips_pmc_switch_out(struct pmc_cpu *pc, struct pmc_process *pp)
370 mips_pcpu_init(struct pmc_mdep *md, int cpu)
374 struct mips_cpu *pac;
377 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
378 ("[mips,%d] wrong cpu number %d", __LINE__, cpu));
379 PMCDBG1(MDP,INI,1,"mips-init cpu=%d", cpu);
381 mips_pcpu[cpu] = pac = malloc(sizeof(struct mips_cpu), M_PMC,
383 pac->pc_mipspmcs = malloc(sizeof(struct pmc_hw) * mips_npmcs,
384 M_PMC, M_WAITOK|M_ZERO);
386 first_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_MIPS].pcd_ri;
387 KASSERT(pc != NULL, ("[mips,%d] NULL per-cpu pointer", __LINE__));
389 for (i = 0, phw = pac->pc_mipspmcs; i < mips_npmcs; i++, phw++) {
390 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED |
391 PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(i);
393 pc->pc_hwpmcs[i + first_ri] = phw;
397 * Clear the counter control register which has the effect
398 * of disabling counting.
400 for (i = 0; i < mips_npmcs; i++)
401 mips_pmcn_write(i, 0);
407 mips_pcpu_fini(struct pmc_mdep *md, int cpu)
413 pmc_mips_initialize()
415 struct pmc_mdep *pmc_mdep;
416 struct pmc_classdep *pcd;
419 * TODO: Use More bit of PerfCntlX register to detect actual
424 PMCDBG1(MDP,INI,1,"mips-init npmcs=%d", mips_npmcs);
427 * Allocate space for pointers to PMC HW descriptors and for
428 * the MDEP structure used by MI code.
430 mips_pcpu = malloc(sizeof(struct mips_cpu *) * pmc_cpu_max(), M_PMC,
434 pmc_mdep = pmc_mdep_alloc(1);
436 pmc_mdep->pmd_cputype = mips_pmc_spec.ps_cputype;
438 pcd = &pmc_mdep->pmd_classdep[PMC_MDEP_CLASS_INDEX_MIPS];
439 pcd->pcd_caps = mips_pmc_spec.ps_capabilities;
440 pcd->pcd_class = mips_pmc_spec.ps_cpuclass;
441 pcd->pcd_num = mips_npmcs;
442 pcd->pcd_ri = pmc_mdep->pmd_npmc;
443 pcd->pcd_width = mips_pmc_spec.ps_counter_width;
445 pcd->pcd_allocate_pmc = mips_allocate_pmc;
446 pcd->pcd_config_pmc = mips_config_pmc;
447 pcd->pcd_pcpu_fini = mips_pcpu_fini;
448 pcd->pcd_pcpu_init = mips_pcpu_init;
449 pcd->pcd_describe = mips_describe;
450 pcd->pcd_get_config = mips_get_config;
451 pcd->pcd_read_pmc = mips_read_pmc;
452 pcd->pcd_release_pmc = mips_release_pmc;
453 pcd->pcd_start_pmc = mips_start_pmc;
454 pcd->pcd_stop_pmc = mips_stop_pmc;
455 pcd->pcd_write_pmc = mips_write_pmc;
457 pmc_mdep->pmd_intr = mips_pmc_intr;
458 pmc_mdep->pmd_switch_in = mips_pmc_switch_in;
459 pmc_mdep->pmd_switch_out = mips_pmc_switch_out;
461 pmc_mdep->pmd_npmc += mips_npmcs;
467 pmc_mips_finalize(struct pmc_mdep *md)
472 #ifdef HWPMC_MIPS_BACKTRACE
475 pmc_next_frame(register_t *pc, register_t *sp)
479 uint32_t instr, mask;
483 /* Jump here after a nonstandard (interrupt handler) frame */
486 /* check for bad SP: could foul up next frame */
487 if (!MIPS_IS_VALID_KERNELADDR(*sp)) {
491 /* check for bad PC */
492 if (!MIPS_IS_VALID_KERNELADDR(*pc)) {
497 * Find the beginning of the current subroutine by scanning
498 * backwards from the current PC for the end of the previous
501 va = *pc - sizeof(int);
503 instr = *((uint32_t *)va);
505 /* [d]addiu sp,sp,-X */
506 if (((instr & 0xffff8000) == 0x27bd8000)
507 || ((instr & 0xffff8000) == 0x67bd8000))
511 if (instr == 0x03e00008) {
512 /* skip over branch-delay slot instruction */
513 va += 2 * sizeof(int);
520 /* skip over nulls which might separate .o files */
521 while ((instr = *((uint32_t *)va)) == 0)
524 /* scan forwards to find stack size and any saved registers */
528 for (; more; va += sizeof(int),
529 more = (more == 3) ? 3 : more - 1) {
530 /* stop if hit our current position */
533 instr = *((uint32_t *)va);
535 switch (i.JType.op) {
537 switch (i.RType.func) {
540 more = 2; /* stop after next instruction */
545 more = 1; /* stop now */
556 more = 2; /* stop after next instruction */
563 switch (i.RType.rs) {
566 more = 2; /* stop after next instruction */
573 * SP is being saved using S8(FP). Most likely it indicates
574 * that SP is modified in the function and we can't get
575 * its value safely without emulating code backward
576 * So just bail out on functions like this
578 if ((i.IType.rs == 30) && (i.IType.rt = 29))
581 /* look for saved registers on the stack */
582 if (i.IType.rs != 29)
584 /* only restore the first one */
585 if (mask & (1 << i.IType.rt))
587 mask |= (1 << i.IType.rt);
588 if (i.IType.rt == 31)
589 ra = *((register_t *)(*sp + (short)i.IType.imm));
596 /* look for stack pointer adjustment */
597 if (i.IType.rs != 29 || i.IType.rt != 29)
599 stksize = -((short)i.IType.imm);
603 if (!MIPS_IS_VALID_KERNELADDR(ra))
616 pmc_next_uframe(register_t *pc, register_t *sp, register_t *ra)
618 int offset, registers_on_stack;
619 uint32_t opcode, mask;
620 register_t function_start;
624 registers_on_stack = 0;
630 while (offset < MAX_FUNCTION_SIZE) {
631 opcode = fuword32((void *)(*pc - offset));
633 /* [d]addiu sp, sp, -X*/
634 if (((opcode & 0xffff8000) == 0x27bd8000)
635 || ((opcode & 0xffff8000) == 0x67bd8000)) {
636 function_start = *pc - offset;
637 registers_on_stack = 1;
642 if ((opcode & 0xffff8000) == 0x3c1c0000) {
644 * Function might start with this instruction
645 * Keep an eye on "jr ra" and sp correction
646 * with positive value further on
648 function_start = *pc - offset;
651 if (function_start) {
653 * Stop looking further. Possible end of
654 * function instruction: it means there is no
655 * stack modifications, sp is unchanged
658 /* [d]addiu sp,sp,X */
659 if (((opcode & 0xffff8000) == 0x27bd0000)
660 || ((opcode & 0xffff8000) == 0x67bd0000))
663 if (opcode == 0x03e00008)
667 offset += sizeof(int);
673 if (registers_on_stack) {
675 while ((offset < MAX_PROLOGUE_SIZE)
676 && ((function_start + offset) < *pc)) {
677 i.word = fuword32((void *)(function_start + offset));
678 switch (i.JType.op) {
680 /* look for saved registers on the stack */
681 if (i.IType.rs != 29)
683 /* only restore the first one */
684 if (mask & (1 << i.IType.rt))
686 mask |= (1 << i.IType.rt);
687 if (i.IType.rt == 31)
688 *ra = fuword32((void *)(*sp + (short)i.IType.imm));
691 #if defined(__mips_n64)
693 /* look for saved registers on the stack */
694 if (i.IType.rs != 29)
696 /* only restore the first one */
697 if (mask & (1 << i.IType.rt))
699 mask |= (1 << i.IType.rt);
701 if (i.IType.rt == 31)
702 *ra = fuword64((void *)(*sp + (short)i.IType.imm));
710 /* look for stack pointer adjustment */
711 if (i.IType.rs != 29 || i.IType.rt != 29)
713 stksize = -((short)i.IType.imm);
716 offset += sizeof(int);
721 * We reached the end of backtrace
732 #endif /* HWPMC_MIPS_BACKTRACE */
737 return pmc_mips_initialize();
741 pmc_md_finalize(struct pmc_mdep *md)
743 return pmc_mips_finalize(md);
747 pmc_save_kernel_callchain(uintptr_t *cc, int nframes,
748 struct trapframe *tf)
750 register_t pc, ra, sp;
759 #ifdef HWPMC_MIPS_BACKTRACE
761 * Unwind, and unwind, and unwind
764 if (frames >= nframes)
767 if (pmc_next_frame(&pc, &sp) < 0)
778 pmc_save_user_callchain(uintptr_t *cc, int nframes,
779 struct trapframe *tf)
781 register_t pc, ra, sp;
790 #ifdef HWPMC_MIPS_BACKTRACE
793 * Unwind, and unwind, and unwind
796 if (frames >= nframes)
799 if (pmc_next_uframe(&pc, &sp, &ra) < 0)