sys/dev/hwpmc/hwpmc_mpc7xxx.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 2011 Justin Hibbits
   5  * Copyright (c) 2005, Joseph Koshy
   6  * All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  27  * SUCH DAMAGE.
  28  *
  29  */
  30
  31 #include <sys/cdefs.h>
  32 __FBSDID("$FreeBSD$");
  33
  34 #include <sys/param.h>
  35 #include <sys/pmc.h>
  36 #include <sys/pmckern.h>
  37 #include <sys/systm.h>
  38
  39 #include <machine/pmc_mdep.h>
  40 #include <machine/spr.h>
  41 #include <machine/cpu.h>
  42
  43 #include "hwpmc_powerpc.h"
  44
  45 #define PPC_SET_PMC1SEL(r, x)   ((r & ~(SPR_MMCR0_74XX_PMC1SEL(0x3f))) | \
  46                                 SPR_MMCR0_74XX_PMC1SEL(x))
  47 #define PPC_SET_PMC2SEL(r, x)   ((r & ~(SPR_MMCR0_74XX_PMC2SEL(0x3f))) | \
  48                                 SPR_MMCR0_74XX_PMC2SEL(x))
  49 #define PPC_SET_PMC3SEL(r, x)   ((r & ~(SPR_MMCR1_PMC3SEL(0x1f))) | SPR_MMCR1_PMC3SEL(x))
  50 #define PPC_SET_PMC4SEL(r, x)   ((r & ~(SPR_MMCR1_PMC4SEL(0x1f))) | SPR_MMCR1_PMC4SEL(x))
  51 #define PPC_SET_PMC5SEL(r, x)   ((r & ~(SPR_MMCR1_PMC5SEL(0x1f))) | SPR_MMCR1_PMC5SEL(x))
  52 #define PPC_SET_PMC6SEL(r, x)   ((r & ~(SPR_MMCR1_74XX_PMC6SEL(0x3f))) | \
  53                                 SPR_MMCR1_74XX_PMC6SEL(x))
  54
  55 /* Change this when we support more than just the 7450. */
  56 #define MPC7XXX_MAX_PMCS        6
  57
  58 /*
  59  * Things to improve on this:
  60  * - It stops (clears to 0) the PMC and resets it at every context switch
  61  *   currently.
  62  */
  63
  64 /*
  65  * This should work for every 32-bit PowerPC implementation I know of (G3 and G4
  66  * specifically).
  67  */
  68
  69 #define PPC_PMC_MASK_ALL        0x3f
  70 #define PMC_POWERPC_EVENT(id, mask, number) \
  71         { .pe_event = PMC_EV_PPC7450_##id, .pe_flags = mask, .pe_code = number }
  72
  73 static struct pmc_ppc_event mpc7xxx_event_codes[] = {
  74         PMC_POWERPC_EVENT(CYCLE,PPC_PMC_MASK_ALL, 1),
  75         PMC_POWERPC_EVENT(INSTR_COMPLETED, 0x0f, 2),
  76         PMC_POWERPC_EVENT(TLB_BIT_TRANSITIONS, 0x0f, 3),
  77         PMC_POWERPC_EVENT(INSTR_DISPATCHED, 0x0f, 4),
  78         PMC_POWERPC_EVENT(PMON_EXCEPT, 0x0f, 5),
  79         PMC_POWERPC_EVENT(PMON_SIG, 0x0f, 7),
  80         PMC_POWERPC_EVENT(VPU_INSTR_COMPLETED, 0x03, 8),
  81         PMC_POWERPC_EVENT(VFPU_INSTR_COMPLETED, 0x03, 9),
  82         PMC_POWERPC_EVENT(VIU1_INSTR_COMPLETED, 0x03, 10),
  83         PMC_POWERPC_EVENT(VIU2_INSTR_COMPLETED, 0x03, 11),
  84         PMC_POWERPC_EVENT(MTVSCR_INSTR_COMPLETED, 0x03, 12),
  85         PMC_POWERPC_EVENT(MTVRSAVE_INSTR_COMPLETED, 0x03, 13),
  86         PMC_POWERPC_EVENT(VPU_INSTR_WAIT_CYCLES, 0x03, 14),
  87         PMC_POWERPC_EVENT(VFPU_INSTR_WAIT_CYCLES, 0x03, 15),
  88         PMC_POWERPC_EVENT(VIU1_INSTR_WAIT_CYCLES, 0x03, 16),
  89         PMC_POWERPC_EVENT(VIU2_INSTR_WAIT_CYCLES, 0x03, 17),
  90         PMC_POWERPC_EVENT(MFVSCR_SYNC_CYCLES, 0x03, 18),
  91         PMC_POWERPC_EVENT(VSCR_SAT_SET, 0x03, 19),
  92         PMC_POWERPC_EVENT(STORE_INSTR_COMPLETED, 0x03, 20),
  93         PMC_POWERPC_EVENT(L1_INSTR_CACHE_MISSES, 0x03, 21),
  94         PMC_POWERPC_EVENT(L1_DATA_SNOOPS, 0x03, 22),
  95         PMC_POWERPC_EVENT(UNRESOLVED_BRANCHES, 0x01, 23),
  96         PMC_POWERPC_EVENT(SPEC_BUFFER_CYCLES, 0x01, 24),
  97         PMC_POWERPC_EVENT(BRANCH_UNIT_STALL_CYCLES, 0x01, 25),
  98         PMC_POWERPC_EVENT(TRUE_BRANCH_TARGET_HITS, 0x01, 26),
  99         PMC_POWERPC_EVENT(BRANCH_LINK_STAC_PREDICTED, 0x01, 27),
 100         PMC_POWERPC_EVENT(GPR_ISSUE_QUEUE_DISPATCHES, 0x01, 28),
 101         PMC_POWERPC_EVENT(CYCLES_THREE_INSTR_DISPATCHED, 0x01, 29),
 102         PMC_POWERPC_EVENT(THRESHOLD_INSTR_QUEUE_ENTRIES_CYCLES, 0x01, 30),
 103         PMC_POWERPC_EVENT(THRESHOLD_VEC_INSTR_QUEUE_ENTRIES_CYCLES, 0x01, 31),
 104         PMC_POWERPC_EVENT(CYCLES_NO_COMPLETED_INSTRS, 0x01, 32),
 105         PMC_POWERPC_EVENT(IU2_INSTR_COMPLETED, 0x01, 33),
 106         PMC_POWERPC_EVENT(BRANCHES_COMPLETED, 0x01, 34),
 107         PMC_POWERPC_EVENT(EIEIO_INSTR_COMPLETED, 0x01, 35),
 108         PMC_POWERPC_EVENT(MTSPR_INSTR_COMPLETED, 0x01, 36),
 109         PMC_POWERPC_EVENT(SC_INSTR_COMPLETED, 0x01, 37),
 110         PMC_POWERPC_EVENT(LS_LM_COMPLETED, 0x01, 38),
 111         PMC_POWERPC_EVENT(ITLB_HW_TABLE_SEARCH_CYCLES, 0x01, 39),
 112         PMC_POWERPC_EVENT(DTLB_HW_SEARCH_CYCLES_OVER_THRESHOLD, 0x01, 40),
 113         PMC_POWERPC_EVENT(L1_INSTR_CACHE_ACCESSES, 0x01, 41),
 114         PMC_POWERPC_EVENT(INSTR_BKPT_MATCHES, 0x01, 42),
 115         PMC_POWERPC_EVENT(L1_DATA_CACHE_LOAD_MISS_CYCLES_OVER_THRESHOLD, 0x01, 43),
 116         PMC_POWERPC_EVENT(L1_DATA_SNOOP_HIT_ON_MODIFIED, 0x01, 44),
 117         PMC_POWERPC_EVENT(LOAD_MISS_ALIAS, 0x01, 45),
 118         PMC_POWERPC_EVENT(LOAD_MISS_ALIAS_ON_TOUCH, 0x01, 46),
 119         PMC_POWERPC_EVENT(TOUCH_ALIAS, 0x01, 47),
 120         PMC_POWERPC_EVENT(L1_DATA_SNOOP_HIT_CASTOUT_QUEUE, 0x01, 48),
 121         PMC_POWERPC_EVENT(L1_DATA_SNOOP_HIT_CASTOUT, 0x01, 49),
 122         PMC_POWERPC_EVENT(L1_DATA_SNOOP_HITS, 0x01, 50),
 123         PMC_POWERPC_EVENT(WRITE_THROUGH_STORES, 0x01, 51),
 124         PMC_POWERPC_EVENT(CACHE_INHIBITED_STORES, 0x01, 52),
 125         PMC_POWERPC_EVENT(L1_DATA_LOAD_HIT, 0x01, 53),
 126         PMC_POWERPC_EVENT(L1_DATA_TOUCH_HIT, 0x01, 54),
 127         PMC_POWERPC_EVENT(L1_DATA_STORE_HIT, 0x01, 55),
 128         PMC_POWERPC_EVENT(L1_DATA_TOTAL_HITS, 0x01, 56),
 129         PMC_POWERPC_EVENT(DST_INSTR_DISPATCHED, 0x01, 57),
 130         PMC_POWERPC_EVENT(REFRESHED_DSTS, 0x01, 58),
 131         PMC_POWERPC_EVENT(SUCCESSFUL_DST_TABLE_SEARCHES, 0x01, 59),
 132         PMC_POWERPC_EVENT(DSS_INSTR_COMPLETED, 0x01, 60),
 133         PMC_POWERPC_EVENT(DST_STREAM_0_CACHE_LINE_FETCHES, 0x01, 61),
 134         PMC_POWERPC_EVENT(VTQ_SUSPENDS_DUE_TO_CTX_CHANGE, 0x01, 62),
 135         PMC_POWERPC_EVENT(VTQ_LINE_FETCH_HIT, 0x01, 63),
 136         PMC_POWERPC_EVENT(VEC_LOAD_INSTR_COMPLETED, 0x01, 64),
 137         PMC_POWERPC_EVENT(FP_STORE_INSTR_COMPLETED_IN_LSU, 0x01, 65),
 138         PMC_POWERPC_EVENT(FPU_RENORMALIZATION, 0x01, 66),
 139         PMC_POWERPC_EVENT(FPU_DENORMALIZATION, 0x01, 67),
 140         PMC_POWERPC_EVENT(FP_STORE_CAUSES_STALL_IN_LSU, 0x01, 68),
 141         PMC_POWERPC_EVENT(LD_ST_TRUE_ALIAS_STALL, 0x01, 70),
 142         PMC_POWERPC_EVENT(LSU_INDEXED_ALIAS_STALL, 0x01, 71),
 143         PMC_POWERPC_EVENT(LSU_ALIAS_VS_FSQ_WB0_WB1, 0x01, 72),
 144         PMC_POWERPC_EVENT(LSU_ALIAS_VS_CSQ, 0x01, 73),
 145         PMC_POWERPC_EVENT(LSU_LOAD_HIT_LINE_ALIAS_VS_CSQ0, 0x01, 74),
 146         PMC_POWERPC_EVENT(LSU_LOAD_MISS_LINE_ALIAS_VS_CSQ0, 0x01, 75),
 147         PMC_POWERPC_EVENT(LSU_TOUCH_LINE_ALIAS_VS_FSQ_WB0_WB1, 0x01, 76),
 148         PMC_POWERPC_EVENT(LSU_TOUCH_ALIAS_VS_CSQ, 0x01, 77),
 149         PMC_POWERPC_EVENT(LSU_LMQ_FULL_STALL, 0x01, 78),
 150         PMC_POWERPC_EVENT(FP_LOAD_INSTR_COMPLETED_IN_LSU, 0x01, 79),
 151         PMC_POWERPC_EVENT(FP_LOAD_SINGLE_INSTR_COMPLETED_IN_LSU, 0x01, 80),
 152         PMC_POWERPC_EVENT(FP_LOAD_DOUBLE_COMPLETED_IN_LSU, 0x01, 81),
 153         PMC_POWERPC_EVENT(LSU_RA_LATCH_STALL, 0x01, 82),
 154         PMC_POWERPC_EVENT(LSU_LOAD_VS_STORE_QUEUE_ALIAS_STALL, 0x01, 83),
 155         PMC_POWERPC_EVENT(LSU_LMQ_INDEX_ALIAS, 0x01, 84),
 156         PMC_POWERPC_EVENT(LSU_STORE_QUEUE_INDEX_ALIAS, 0x01, 85),
 157         PMC_POWERPC_EVENT(LSU_CSQ_FORWARDING, 0x01, 86),
 158         PMC_POWERPC_EVENT(LSU_MISALIGNED_LOAD_FINISH, 0x01, 87),
 159         PMC_POWERPC_EVENT(LSU_MISALIGN_STORE_COMPLETED, 0x01, 88),
 160         PMC_POWERPC_EVENT(LSU_MISALIGN_STALL, 0x01, 89),
 161         PMC_POWERPC_EVENT(FP_ONE_QUARTER_FPSCR_RENAMES_BUSY, 0x01, 90),
 162         PMC_POWERPC_EVENT(FP_ONE_HALF_FPSCR_RENAMES_BUSY, 0x01, 91),
 163         PMC_POWERPC_EVENT(FP_THREE_QUARTERS_FPSCR_RENAMES_BUSY, 0x01, 92),
 164         PMC_POWERPC_EVENT(FP_ALL_FPSCR_RENAMES_BUSY, 0x01, 93),
 165         PMC_POWERPC_EVENT(FP_DENORMALIZED_RESULT, 0x01, 94),
 166         PMC_POWERPC_EVENT(L1_DATA_TOTAL_MISSES, 0x02, 23),
 167         PMC_POWERPC_EVENT(DISPATCHES_TO_FPR_ISSUE_QUEUE, 0x02, 24),
 168         PMC_POWERPC_EVENT(LSU_INSTR_COMPLETED, 0x02, 25),
 169         PMC_POWERPC_EVENT(LOAD_INSTR_COMPLETED, 0x02, 26),
 170         PMC_POWERPC_EVENT(SS_SM_INSTR_COMPLETED, 0x02, 27),
 171         PMC_POWERPC_EVENT(TLBIE_INSTR_COMPLETED, 0x02, 28),
 172         PMC_POWERPC_EVENT(LWARX_INSTR_COMPLETED, 0x02, 29),
 173         PMC_POWERPC_EVENT(MFSPR_INSTR_COMPLETED, 0x02, 30),
 174         PMC_POWERPC_EVENT(REFETCH_SERIALIZATION, 0x02, 31),
 175         PMC_POWERPC_EVENT(COMPLETION_QUEUE_ENTRIES_OVER_THRESHOLD, 0x02, 32),
 176         PMC_POWERPC_EVENT(CYCLES_ONE_INSTR_DISPATCHED, 0x02, 33),
 177         PMC_POWERPC_EVENT(CYCLES_TWO_INSTR_COMPLETED, 0x02, 34),
 178         PMC_POWERPC_EVENT(ITLB_NON_SPECULATIVE_MISSES, 0x02, 35),
 179         PMC_POWERPC_EVENT(CYCLES_WAITING_FROM_L1_INSTR_CACHE_MISS, 0x02, 36),
 180         PMC_POWERPC_EVENT(L1_DATA_LOAD_ACCESS_MISS, 0x02, 37),
 181         PMC_POWERPC_EVENT(L1_DATA_TOUCH_MISS, 0x02, 38),
 182         PMC_POWERPC_EVENT(L1_DATA_STORE_MISS, 0x02, 39),
 183         PMC_POWERPC_EVENT(L1_DATA_TOUCH_MISS_CYCLES, 0x02, 40),
 184         PMC_POWERPC_EVENT(L1_DATA_CYCLES_USED, 0x02, 41),
 185         PMC_POWERPC_EVENT(DST_STREAM_1_CACHE_LINE_FETCHES, 0x02, 42),
 186         PMC_POWERPC_EVENT(VTQ_STREAM_CANCELED_PREMATURELY, 0x02, 43),
 187         PMC_POWERPC_EVENT(VTQ_RESUMES_DUE_TO_CTX_CHANGE, 0x02, 44),
 188         PMC_POWERPC_EVENT(VTQ_LINE_FETCH_MISS, 0x02, 45),
 189         PMC_POWERPC_EVENT(VTQ_LINE_FETCH, 0x02, 46),
 190         PMC_POWERPC_EVENT(TLBIE_SNOOPS, 0x02, 47),
 191         PMC_POWERPC_EVENT(L1_INSTR_CACHE_RELOADS, 0x02, 48),
 192         PMC_POWERPC_EVENT(L1_DATA_CACHE_RELOADS, 0x02, 49),
 193         PMC_POWERPC_EVENT(L1_DATA_CACHE_CASTOUTS_TO_L2, 0x02, 50),
 194         PMC_POWERPC_EVENT(STORE_MERGE_GATHER, 0x02, 51),
 195         PMC_POWERPC_EVENT(CACHEABLE_STORE_MERGE_TO_32_BYTES, 0x02, 52),
 196         PMC_POWERPC_EVENT(DATA_BKPT_MATCHES, 0x02, 53),
 197         PMC_POWERPC_EVENT(FALL_THROUGH_BRANCHES_PROCESSED, 0x02, 54),
 198         PMC_POWERPC_EVENT(FIRST_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLY, 0x02, 55),
 199         PMC_POWERPC_EVENT(SECOND_SPECULATION_BUFFER_ACTIVE, 0x02, 56),
 200         PMC_POWERPC_EVENT(BPU_STALL_ON_LR_DEPENDENCY, 0x02, 57),
 201         PMC_POWERPC_EVENT(BTIC_MISS, 0x02, 58),
 202         PMC_POWERPC_EVENT(BRANCH_LINK_STACK_CORRECTLY_RESOLVED, 0x02, 59),
 203         PMC_POWERPC_EVENT(FPR_ISSUE_STALLED, 0x02, 60),
 204         PMC_POWERPC_EVENT(SWITCHES_BETWEEN_PRIV_USER, 0x02, 61),
 205         PMC_POWERPC_EVENT(LSU_COMPLETES_FP_STORE_SINGLE, 0x02, 62),
 206         PMC_POWERPC_EVENT(CYCLES_TWO_INSTR_COMPLETED, 0x04, 8),
 207         PMC_POWERPC_EVENT(CYCLES_ONE_INSTR_DISPATCHED, 0x04, 9),
 208         PMC_POWERPC_EVENT(VR_ISSUE_QUEUE_DISPATCHES, 0x04, 10),
 209         PMC_POWERPC_EVENT(VR_STALLS, 0x04, 11),
 210         PMC_POWERPC_EVENT(GPR_RENAME_BUFFER_ENTRIES_OVER_THRESHOLD, 0x04, 12),
 211         PMC_POWERPC_EVENT(FPR_ISSUE_QUEUE_ENTRIES, 0x04, 13),
 212         PMC_POWERPC_EVENT(FPU_INSTR_COMPLETED, 0x04, 14),
 213         PMC_POWERPC_EVENT(STWCX_INSTR_COMPLETED, 0x04, 15),
 214         PMC_POWERPC_EVENT(LS_LM_INSTR_PIECES, 0x04, 16),
 215         PMC_POWERPC_EVENT(ITLB_HW_SEARCH_CYCLES_OVER_THRESHOLD, 0x04, 17),
 216         PMC_POWERPC_EVENT(DTLB_MISSES, 0x04, 18),
 217         PMC_POWERPC_EVENT(CANCELLED_L1_INSTR_CACHE_MISSES, 0x04, 19),
 218         PMC_POWERPC_EVENT(L1_DATA_CACHE_OP_HIT, 0x04, 20),
 219         PMC_POWERPC_EVENT(L1_DATA_LOAD_MISS_CYCLES, 0x04, 21),
 220         PMC_POWERPC_EVENT(L1_DATA_PUSHES, 0x04, 22),
 221         PMC_POWERPC_EVENT(L1_DATA_TOTAL_MISS, 0x04, 23),
 222         PMC_POWERPC_EVENT(VT2_FETCHES, 0x04, 24),
 223         PMC_POWERPC_EVENT(TAKEN_BRANCHES_PROCESSED, 0x04, 25),
 224         PMC_POWERPC_EVENT(BRANCH_FLUSHES, 0x04, 26),
 225         PMC_POWERPC_EVENT(SECOND_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLY, 0x04, 27),
 226         PMC_POWERPC_EVENT(THIRD_SPECULATION_BUFFER_ACTIVE, 0x04, 28),
 227         PMC_POWERPC_EVENT(BRANCH_UNIT_STALL_ON_CTR_DEPENDENCY, 0x04, 29),
 228         PMC_POWERPC_EVENT(FAST_BTIC_HIT, 0x04, 30),
 229         PMC_POWERPC_EVENT(BRANCH_LINK_STACK_MISPREDICTED, 0x04, 31),
 230         PMC_POWERPC_EVENT(CYCLES_THREE_INSTR_COMPLETED, 0x08, 14),
 231         PMC_POWERPC_EVENT(CYCLES_NO_INSTR_DISPATCHED, 0x08, 15),
 232         PMC_POWERPC_EVENT(GPR_ISSUE_QUEUE_ENTRIES_OVER_THRESHOLD, 0x08, 16),
 233         PMC_POWERPC_EVENT(GPR_ISSUE_QUEUE_STALLED, 0x08, 17),
 234         PMC_POWERPC_EVENT(IU1_INSTR_COMPLETED, 0x08, 18),
 235         PMC_POWERPC_EVENT(DSSALL_INSTR_COMPLETED, 0x08, 19),
 236         PMC_POWERPC_EVENT(TLBSYNC_INSTR_COMPLETED, 0x08, 20),
 237         PMC_POWERPC_EVENT(SYNC_INSTR_COMPLETED, 0x08, 21),
 238         PMC_POWERPC_EVENT(SS_SM_INSTR_PIECES, 0x08, 22),
 239         PMC_POWERPC_EVENT(DTLB_HW_SEARCH_CYCLES, 0x08, 23),
 240         PMC_POWERPC_EVENT(SNOOP_RETRIES, 0x08, 24),
 241         PMC_POWERPC_EVENT(SUCCESSFUL_STWCX, 0x08, 25),
 242         PMC_POWERPC_EVENT(DST_STREAM_3_CACHE_LINE_FETCHES, 0x08, 26),
 243         PMC_POWERPC_EVENT(THIRD_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLY, 0x08, 27),
 244         PMC_POWERPC_EVENT(MISPREDICTED_BRANCHES, 0x08, 28),
 245         PMC_POWERPC_EVENT(FOLDED_BRANCHES, 0x08, 29),
 246         PMC_POWERPC_EVENT(FP_STORE_DOUBLE_COMPLETES_IN_LSU, 0x08, 30),
 247         PMC_POWERPC_EVENT(L2_CACHE_HITS, 0x30, 2),
 248         PMC_POWERPC_EVENT(L3_CACHE_HITS, 0x30, 3),
 249         PMC_POWERPC_EVENT(L2_INSTR_CACHE_MISSES, 0x30, 4),
 250         PMC_POWERPC_EVENT(L3_INSTR_CACHE_MISSES, 0x30, 5),
 251         PMC_POWERPC_EVENT(L2_DATA_CACHE_MISSES, 0x30, 6),
 252         PMC_POWERPC_EVENT(L3_DATA_CACHE_MISSES, 0x30, 7),
 253         PMC_POWERPC_EVENT(L2_LOAD_HITS, 0x10, 8),
 254         PMC_POWERPC_EVENT(L2_STORE_HITS, 0x10, 9),
 255         PMC_POWERPC_EVENT(L3_LOAD_HITS, 0x10, 10),
 256         PMC_POWERPC_EVENT(L3_STORE_HITS, 0x10, 11),
 257         PMC_POWERPC_EVENT(L2_TOUCH_HITS, 0x30, 13),
 258         PMC_POWERPC_EVENT(L3_TOUCH_HITS, 0x30, 14),
 259         PMC_POWERPC_EVENT(SNOOP_RETRIES, 0x30, 15),
 260         PMC_POWERPC_EVENT(SNOOP_MODIFIED, 0x10, 16),
 261         PMC_POWERPC_EVENT(SNOOP_VALID, 0x10, 17),
 262         PMC_POWERPC_EVENT(INTERVENTION, 0x30, 18),
 263         PMC_POWERPC_EVENT(L2_CACHE_MISSES, 0x10, 19),
 264         PMC_POWERPC_EVENT(L3_CACHE_MISSES, 0x10, 20),
 265         PMC_POWERPC_EVENT(L2_CACHE_CASTOUTS, 0x20, 8),
 266         PMC_POWERPC_EVENT(L3_CACHE_CASTOUTS, 0x20, 9),
 267         PMC_POWERPC_EVENT(L2SQ_FULL_CYCLES, 0x20, 10),
 268         PMC_POWERPC_EVENT(L3SQ_FULL_CYCLES, 0x20, 11),
 269         PMC_POWERPC_EVENT(RAQ_FULL_CYCLES, 0x20, 16),
 270         PMC_POWERPC_EVENT(WAQ_FULL_CYCLES, 0x20, 17),
 271         PMC_POWERPC_EVENT(L1_EXTERNAL_INTERVENTIONS, 0x20, 19),
 272         PMC_POWERPC_EVENT(L2_EXTERNAL_INTERVENTIONS, 0x20, 20),
 273         PMC_POWERPC_EVENT(L3_EXTERNAL_INTERVENTIONS, 0x20, 21),
 274         PMC_POWERPC_EVENT(EXTERNAL_INTERVENTIONS, 0x20, 22),
 275         PMC_POWERPC_EVENT(EXTERNAL_PUSHES, 0x20, 23),
 276         PMC_POWERPC_EVENT(EXTERNAL_SNOOP_RETRY, 0x20, 24),
 277         PMC_POWERPC_EVENT(DTQ_FULL_CYCLES, 0x20, 25),
 278         PMC_POWERPC_EVENT(BUS_RETRY, 0x20, 26),
 279         PMC_POWERPC_EVENT(L2_VALID_REQUEST, 0x20, 27),
 280         PMC_POWERPC_EVENT(BORDQ_FULL, 0x20, 28),
 281         PMC_POWERPC_EVENT(BUS_TAS_FOR_READS, 0x20, 42),
 282         PMC_POWERPC_EVENT(BUS_TAS_FOR_WRITES, 0x20, 43),
 283         PMC_POWERPC_EVENT(BUS_READS_NOT_RETRIED, 0x20, 44),
 284         PMC_POWERPC_EVENT(BUS_WRITES_NOT_RETRIED, 0x20, 45),
 285         PMC_POWERPC_EVENT(BUS_READS_WRITES_NOT_RETRIED, 0x20, 46),
 286         PMC_POWERPC_EVENT(BUS_RETRY_DUE_TO_L1_RETRY, 0x20, 47),
 287         PMC_POWERPC_EVENT(BUS_RETRY_DUE_TO_PREVIOUS_ADJACENT, 0x20, 48),
 288         PMC_POWERPC_EVENT(BUS_RETRY_DUE_TO_COLLISION, 0x20, 49),
 289         PMC_POWERPC_EVENT(BUS_RETRY_DUE_TO_INTERVENTION_ORDERING, 0x20, 50),
 290         PMC_POWERPC_EVENT(SNOOP_REQUESTS, 0x20, 51),
 291         PMC_POWERPC_EVENT(PREFETCH_ENGINE_REQUEST, 0x20, 52),
 292         PMC_POWERPC_EVENT(PREFETCH_ENGINE_COLLISION_VS_LOAD, 0x20, 53),
 293         PMC_POWERPC_EVENT(PREFETCH_ENGINE_COLLISION_VS_STORE, 0x20, 54),
 294         PMC_POWERPC_EVENT(PREFETCH_ENGINE_COLLISION_VS_INSTR_FETCH, 0x20, 55),
 295         PMC_POWERPC_EVENT(PREFETCH_ENGINE_COLLISION_VS_LOAD_STORE_INSTR_FETCH, 0x20, 56),
 296         PMC_POWERPC_EVENT(PREFETCH_ENGINE_FULL, 0x20, 57)
 297 };
 298 static size_t mpc7xxx_event_codes_size = nitems(mpc7xxx_event_codes);
 299
 300 static pmc_value_t
 301 mpc7xxx_pmcn_read(unsigned int pmc)
 302 {
 303         switch (pmc) {
 304         case 0:
 305                 return (mfspr(SPR_PMC1_74XX));
 306         case 1:
 307                 return (mfspr(SPR_PMC2_74XX));
 308         case 2:
 309                 return (mfspr(SPR_PMC3_74XX));
 310         case 3:
 311                 return (mfspr(SPR_PMC4_74XX));
 312         case 4:
 313                 return (mfspr(SPR_PMC5_74XX));
 314         case 5:
 315                 return (mfspr(SPR_PMC6_74XX));
 316         default:
 317                 panic("Invalid PMC number: %d\n", pmc);
 318         }
 319 }
 320
 321 static void
 322 mpc7xxx_pmcn_write(unsigned int pmc, uint32_t val)
 323 {
 324         switch (pmc) {
 325         case 0:
 326                 mtspr(SPR_PMC1_74XX, val);
 327                 break;
 328         case 1:
 329                 mtspr(SPR_PMC2_74XX, val);
 330                 break;
 331         case 2:
 332                 mtspr(SPR_PMC3_74XX, val);
 333                 break;
 334         case 3:
 335                 mtspr(SPR_PMC4_74XX, val);
 336                 break;
 337         case 4:
 338                 mtspr(SPR_PMC5_74XX, val);
 339                 break;
 340         case 5:
 341                 mtspr(SPR_PMC6_74XX, val);
 342                 break;
 343         default:
 344                 panic("Invalid PMC number: %d\n", pmc);
 345         }
 346 }
 347
 348 static void
 349 mpc7xxx_set_pmc(int cpu, int ri, int config)
 350 {
 351         struct pmc *pm;
 352         struct pmc_hw *phw;
 353         register_t pmc_mmcr;
 354         uint32_t config_mask;
 355
 356         phw    = &powerpc_pcpu[cpu]->pc_ppcpmcs[ri];
 357         pm     = phw->phw_pmc;
 358         /* The mask is inverted (enable is 1) compared to the flags in
 359          * MMCR0, which are Freeze flags.
 360          */
 361         config_mask = ~config & POWERPC_PMC_ENABLE;
 362         config &= ~POWERPC_PMC_ENABLE;
 363
 364         /* Enable/disable the PMC. */
 365         switch (ri) {
 366         case 0:
 367                 pmc_mmcr = mfspr(SPR_MMCR0_74XX);
 368                 pmc_mmcr = PPC_SET_PMC1SEL(pmc_mmcr, config);
 369                 mtspr(SPR_MMCR0_74XX, pmc_mmcr);
 370                 break;
 371         case 1:
 372                 pmc_mmcr = mfspr(SPR_MMCR0_74XX);
 373                 pmc_mmcr = PPC_SET_PMC2SEL(pmc_mmcr, config);
 374                 mtspr(SPR_MMCR0_74XX, pmc_mmcr);
 375                 break;
 376         case 2:
 377                 pmc_mmcr = mfspr(SPR_MMCR1_74XX);
 378                 pmc_mmcr = PPC_SET_PMC3SEL(pmc_mmcr, config);
 379                 mtspr(SPR_MMCR1_74XX, pmc_mmcr);
 380                 break;
 381         case 3:
 382                 pmc_mmcr = mfspr(SPR_MMCR0_74XX);
 383                 pmc_mmcr = PPC_SET_PMC4SEL(pmc_mmcr, config);
 384                 mtspr(SPR_MMCR0_74XX, pmc_mmcr);
 385                 break;
 386         case 4:
 387                 pmc_mmcr = mfspr(SPR_MMCR1_74XX);
 388                 pmc_mmcr = PPC_SET_PMC5SEL(pmc_mmcr, config);
 389                 mtspr(SPR_MMCR1_74XX, pmc_mmcr);
 390                 break;
 391         case 5:
 392                 pmc_mmcr = mfspr(SPR_MMCR1_74XX);
 393                 pmc_mmcr = PPC_SET_PMC6SEL(pmc_mmcr, config);
 394                 mtspr(SPR_MMCR1_74XX, pmc_mmcr);
 395                 break;
 396         }
 397
 398         if (config != PMCN_NONE) {
 399                 pmc_mmcr = mfspr(SPR_MMCR0_74XX);
 400                 pmc_mmcr &= ~SPR_MMCR0_FC;
 401                 pmc_mmcr |= config;
 402                 mtspr(SPR_MMCR0_74XX, pmc_mmcr);
 403         }
 404 }
 405
 406 static int
 407 mpc7xxx_pcpu_init(struct pmc_mdep *md, int cpu)
 408 {
 409         powerpc_pcpu_init(md, cpu);
 410
 411         /* Clear the MMCRs, and set FC, to disable all PMCs. */
 412         mtspr(SPR_MMCR0_74XX, SPR_MMCR0_FC | SPR_MMCR0_PMXE |
 413             SPR_MMCR0_FCECE | SPR_MMCR0_PMC1CE | SPR_MMCR0_PMCNCE);
 414         mtspr(SPR_MMCR1_74XX, 0);
 415
 416         return (0);
 417 }
 418
 419 static int
 420 mpc7xxx_pcpu_fini(struct pmc_mdep *md, int cpu)
 421 {
 422         uint32_t mmcr0 = mfspr(SPR_MMCR0_74XX);
 423
 424         mtmsr(mfmsr() & ~PSL_PMM);
 425         mmcr0 |= SPR_MMCR0_FC;
 426         mtspr(SPR_MMCR0_74XX, mmcr0);
 427
 428         return (powerpc_pcpu_fini(md, cpu));
 429 }
 430
 431 static void
 432 mpc7xxx_resume_pmc(bool ie)
 433 {
 434         /* Re-enable PERF exceptions. */
 435         if (ie)
 436                 mtspr(SPR_MMCR0_74XX,
 437                     (mfspr(SPR_MMCR0_74XX) & ~SPR_MMCR0_FC) | SPR_MMCR0_PMXE);
 438 }
 439
 440 int
 441 pmc_mpc7xxx_initialize(struct pmc_mdep *pmc_mdep)
 442 {
 443         struct pmc_classdep *pcd;
 444
 445         pmc_mdep->pmd_cputype = PMC_CPU_PPC_7450;
 446
 447         pcd = &pmc_mdep->pmd_classdep[PMC_MDEP_CLASS_INDEX_POWERPC];
 448         pcd->pcd_caps  = POWERPC_PMC_CAPS;
 449         pcd->pcd_class = PMC_CLASS_PPC7450;
 450         pcd->pcd_num   = MPC7XXX_MAX_PMCS;
 451         pcd->pcd_ri    = pmc_mdep->pmd_npmc;
 452         pcd->pcd_width = 32;    /* All PMCs, even in ppc970, are 32-bit */
 453
 454         pcd->pcd_allocate_pmc   = powerpc_allocate_pmc;
 455         pcd->pcd_config_pmc     = powerpc_config_pmc;
 456         pcd->pcd_pcpu_fini      = mpc7xxx_pcpu_fini;
 457         pcd->pcd_pcpu_init      = mpc7xxx_pcpu_init;
 458         pcd->pcd_describe       = powerpc_describe;
 459         pcd->pcd_get_config     = powerpc_get_config;
 460         pcd->pcd_read_pmc       = powerpc_read_pmc;
 461         pcd->pcd_release_pmc    = powerpc_release_pmc;
 462         pcd->pcd_start_pmc      = powerpc_start_pmc;
 463         pcd->pcd_stop_pmc       = powerpc_stop_pmc;
 464         pcd->pcd_write_pmc      = powerpc_write_pmc;
 465
 466         pmc_mdep->pmd_npmc   += MPC7XXX_MAX_PMCS;
 467         pmc_mdep->pmd_intr   =  powerpc_pmc_intr;
 468
 469         ppc_event_codes = mpc7xxx_event_codes;
 470         ppc_event_codes_size = mpc7xxx_event_codes_size;
 471         ppc_event_first = PMC_EV_PPC7450_FIRST;
 472         ppc_event_last = PMC_EV_PPC7450_LAST;
 473         ppc_max_pmcs = MPC7XXX_MAX_PMCS;
 474         ppc_class = pcd->pcd_class;
 475
 476         powerpc_set_pmc = mpc7xxx_set_pmc;
 477         powerpc_pmcn_read = mpc7xxx_pmcn_read;
 478         powerpc_pmcn_write = mpc7xxx_pmcn_write;
 479         powerpc_resume_pmc = mpc7xxx_resume_pmc;
 480
 481         return (0);
 482 }