sys/dev/hwpmc/hwpmc_octeon.c

   1 /*-
   2  * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  *
  26  */
  27
  28 #include <sys/cdefs.h>
  29 __FBSDID("$FreeBSD$");
  30
  31 #include <sys/param.h>
  32 #include <sys/systm.h>
  33 #include <sys/pmc.h>
  34 #include <sys/pmckern.h>
  35
  36 #include <machine/cpu.h>
  37 #include <machine/cpufunc.h>
  38 #include <machine/pmc_mdep.h>
  39
  40 #include <contrib/octeon-sdk/cvmx.h>
  41 #include <contrib/octeon-sdk/cvmx-core.h>
  42
  43 #define OCTEON_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER |     \
  44                                  PMC_CAP_SYSTEM | PMC_CAP_EDGE |        \
  45                                  PMC_CAP_THRESHOLD | PMC_CAP_READ |     \
  46                                  PMC_CAP_WRITE | PMC_CAP_INVERT |       \
  47                                  PMC_CAP_QUALIFIER)
  48
  49 const struct mips_event_code_map mips_event_codes[] =
  50 {
  51     { PMC_EV_OCTEON_CLK, MIPS_CTR_ALL, CVMX_CORE_PERF_CLK },
  52     { PMC_EV_OCTEON_ISSUE, MIPS_CTR_ALL, CVMX_CORE_PERF_ISSUE },
  53     { PMC_EV_OCTEON_RET, MIPS_CTR_ALL, CVMX_CORE_PERF_RET },
  54     { PMC_EV_OCTEON_NISSUE, MIPS_CTR_ALL, CVMX_CORE_PERF_NISSUE },
  55     { PMC_EV_OCTEON_SISSUE, MIPS_CTR_ALL, CVMX_CORE_PERF_SISSUE },
  56     { PMC_EV_OCTEON_DISSUE, MIPS_CTR_ALL, CVMX_CORE_PERF_DISSUE },
  57     { PMC_EV_OCTEON_IFI, MIPS_CTR_ALL, CVMX_CORE_PERF_IFI },
  58     { PMC_EV_OCTEON_BR, MIPS_CTR_ALL, CVMX_CORE_PERF_BR },
  59     { PMC_EV_OCTEON_BRMIS, MIPS_CTR_ALL, CVMX_CORE_PERF_BRMIS },
  60     { PMC_EV_OCTEON_J, MIPS_CTR_ALL, CVMX_CORE_PERF_J },
  61     { PMC_EV_OCTEON_JMIS, MIPS_CTR_ALL, CVMX_CORE_PERF_JMIS },
  62     { PMC_EV_OCTEON_REPLAY, MIPS_CTR_ALL, CVMX_CORE_PERF_REPLAY },
  63     { PMC_EV_OCTEON_IUNA, MIPS_CTR_ALL, CVMX_CORE_PERF_IUNA },
  64     { PMC_EV_OCTEON_TRAP, MIPS_CTR_ALL, CVMX_CORE_PERF_TRAP },
  65     { PMC_EV_OCTEON_UULOAD, MIPS_CTR_ALL, CVMX_CORE_PERF_UULOAD },
  66     { PMC_EV_OCTEON_UUSTORE, MIPS_CTR_ALL, CVMX_CORE_PERF_UUSTORE },
  67     { PMC_EV_OCTEON_ULOAD, MIPS_CTR_ALL, CVMX_CORE_PERF_ULOAD },
  68     { PMC_EV_OCTEON_USTORE, MIPS_CTR_ALL, CVMX_CORE_PERF_USTORE },
  69     { PMC_EV_OCTEON_EC, MIPS_CTR_ALL, CVMX_CORE_PERF_EC },
  70     { PMC_EV_OCTEON_MC, MIPS_CTR_ALL, CVMX_CORE_PERF_MC },
  71     { PMC_EV_OCTEON_CC, MIPS_CTR_ALL, CVMX_CORE_PERF_CC },
  72     { PMC_EV_OCTEON_CSRC, MIPS_CTR_ALL, CVMX_CORE_PERF_CSRC },
  73     { PMC_EV_OCTEON_CFETCH, MIPS_CTR_ALL, CVMX_CORE_PERF_CFETCH },
  74     { PMC_EV_OCTEON_CPREF, MIPS_CTR_ALL, CVMX_CORE_PERF_CPREF },
  75     { PMC_EV_OCTEON_ICA, MIPS_CTR_ALL, CVMX_CORE_PERF_ICA },
  76     { PMC_EV_OCTEON_II, MIPS_CTR_ALL, CVMX_CORE_PERF_II },
  77     { PMC_EV_OCTEON_IP, MIPS_CTR_ALL, CVMX_CORE_PERF_IP },
  78     { PMC_EV_OCTEON_CIMISS, MIPS_CTR_ALL, CVMX_CORE_PERF_CIMISS },
  79     { PMC_EV_OCTEON_WBUF, MIPS_CTR_ALL, CVMX_CORE_PERF_WBUF },
  80     { PMC_EV_OCTEON_WDAT, MIPS_CTR_ALL, CVMX_CORE_PERF_WDAT },
  81     { PMC_EV_OCTEON_WBUFLD, MIPS_CTR_ALL, CVMX_CORE_PERF_WBUFLD },
  82     { PMC_EV_OCTEON_WBUFFL, MIPS_CTR_ALL, CVMX_CORE_PERF_WBUFFL },
  83     { PMC_EV_OCTEON_WBUFTR, MIPS_CTR_ALL, CVMX_CORE_PERF_WBUFTR },
  84     { PMC_EV_OCTEON_BADD, MIPS_CTR_ALL, CVMX_CORE_PERF_BADD },
  85     { PMC_EV_OCTEON_BADDL2, MIPS_CTR_ALL, CVMX_CORE_PERF_BADDL2 },
  86     { PMC_EV_OCTEON_BFILL, MIPS_CTR_ALL, CVMX_CORE_PERF_BFILL },
  87     { PMC_EV_OCTEON_DDIDS, MIPS_CTR_ALL, CVMX_CORE_PERF_DDIDS },
  88     { PMC_EV_OCTEON_IDIDS, MIPS_CTR_ALL, CVMX_CORE_PERF_IDIDS },
  89     { PMC_EV_OCTEON_DIDNA, MIPS_CTR_ALL, CVMX_CORE_PERF_DIDNA },
  90     { PMC_EV_OCTEON_LDS, MIPS_CTR_ALL, CVMX_CORE_PERF_LDS },
  91     { PMC_EV_OCTEON_LMLDS, MIPS_CTR_ALL, CVMX_CORE_PERF_LMLDS },
  92     { PMC_EV_OCTEON_IOLDS, MIPS_CTR_ALL, CVMX_CORE_PERF_IOLDS },
  93     { PMC_EV_OCTEON_DMLDS, MIPS_CTR_ALL, CVMX_CORE_PERF_DMLDS },
  94     { PMC_EV_OCTEON_STS, MIPS_CTR_ALL, CVMX_CORE_PERF_STS },
  95     { PMC_EV_OCTEON_LMSTS, MIPS_CTR_ALL, CVMX_CORE_PERF_LMSTS },
  96     { PMC_EV_OCTEON_IOSTS, MIPS_CTR_ALL, CVMX_CORE_PERF_IOSTS },
  97     { PMC_EV_OCTEON_IOBDMA, MIPS_CTR_ALL, CVMX_CORE_PERF_IOBDMA },
  98     { PMC_EV_OCTEON_DTLB, MIPS_CTR_ALL, CVMX_CORE_PERF_DTLB },
  99     { PMC_EV_OCTEON_DTLBAD, MIPS_CTR_ALL, CVMX_CORE_PERF_DTLBAD },
 100     { PMC_EV_OCTEON_ITLB, MIPS_CTR_ALL, CVMX_CORE_PERF_ITLB },
 101     { PMC_EV_OCTEON_SYNC, MIPS_CTR_ALL, CVMX_CORE_PERF_SYNC },
 102     { PMC_EV_OCTEON_SYNCIOB, MIPS_CTR_ALL, CVMX_CORE_PERF_SYNCIOB },
 103     { PMC_EV_OCTEON_SYNCW, MIPS_CTR_ALL, CVMX_CORE_PERF_SYNCW },
 104 };
 105
 106 const int mips_event_codes_size = nitems(mips_event_codes);
 107
 108 struct mips_pmc_spec mips_pmc_spec = {
 109         .ps_cpuclass = PMC_CLASS_OCTEON,
 110         .ps_cputype = PMC_CPU_MIPS_OCTEON,
 111         .ps_capabilities = OCTEON_PMC_CAPS,
 112         .ps_counter_width = 64
 113 };
 114
 115 /*
 116  * Performance Count Register N
 117  */
 118 uint64_t
 119 mips_pmcn_read(unsigned int pmc)
 120 {
 121         uint64_t reg = 0;
 122
 123         KASSERT(pmc < mips_npmcs, ("[mips,%d] illegal PMC number %d",
 124                                    __LINE__, pmc));
 125
 126         /* The counter value is the next value after the control register. */
 127         switch (pmc) {
 128         case 0:
 129                 CVMX_MF_COP0(reg, COP0_PERFVALUE0);
 130                 break;
 131         case 1:
 132                 CVMX_MF_COP0(reg, COP0_PERFVALUE1);
 133                 break;
 134         default:
 135                 return 0;
 136         }
 137         return (reg);
 138 }
 139
 140 uint64_t
 141 mips_pmcn_write(unsigned int pmc, uint64_t reg)
 142 {
 143
 144         KASSERT(pmc < mips_npmcs, ("[mips,%d] illegal PMC number %d",
 145                                    __LINE__, pmc));
 146
 147         switch (pmc) {
 148         case 0:
 149                 CVMX_MT_COP0(reg, COP0_PERFVALUE0);
 150                 break;
 151         case 1:
 152                 CVMX_MT_COP0(reg, COP0_PERFVALUE1);
 153                 break;
 154         default:
 155                 return 0;
 156         }
 157         return (reg);
 158 }
 159
 160 uint32_t
 161 mips_get_perfctl(int cpu, int ri, uint32_t event, uint32_t caps)
 162 {
 163         cvmx_core_perf_control_t control;
 164
 165         KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
 166             ("[mips,%d] illegal CPU value %d", __LINE__, cpu));
 167         KASSERT(ri >= 0 && ri < mips_npmcs,
 168             ("[mips,%d] illegal row index %d", __LINE__, ri));
 169
 170         control.s.event = event;
 171
 172         if (caps & PMC_CAP_SYSTEM) {
 173                 control.s.k = 1;
 174                 control.s.s = 1;
 175                 control.s.ex = 1;
 176         }
 177
 178         if (caps & PMC_CAP_USER)
 179                 control.s.u = 1;
 180
 181         if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0) {
 182                 control.s.k = 1;
 183                 control.s.s = 1;
 184                 control.s.u = 1;
 185                 control.s.ex = 1;
 186         }
 187
 188         if (caps & PMC_CAP_INTERRUPT)
 189                 control.s.ie = 1;
 190
 191         PMCDBG2(MDP,ALL,2,"mips-allocate ri=%d -> config=0x%x", ri,
 192             control.u32);
 193
 194         return (control.u32);
 195 }