2 * Copyright (c) 2013 Justin Hibbits
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
33 #include <sys/pmckern.h>
34 #include <sys/systm.h>
36 #include <machine/pmc_mdep.h>
37 #include <machine/spr.h>
38 #include <machine/cpu.h>
40 #include "hwpmc_powerpc.h"
42 #define PPC970_MAX_PMCS 8
44 /* MMCR0, PMC1 is 8 bytes in, PMC2 is 1 byte in. */
45 #define PPC970_SET_MMCR0_PMCSEL(r, x, i) \
46 ((r & ~(0x1f << (7 * (1 - i) + 1))) | (x << (7 * (1 - i) + 1)))
47 /* MMCR1 has 6 PMC*SEL items (PMC3->PMC8), in sequence. */
48 #define PPC970_SET_MMCR1_PMCSEL(r, x, i) \
49 ((r & ~(0x1f << (5 * (7 - i) + 2))) | (x << (5 * (7 - i) + 2)))
51 #define PPC970_PMC_HAS_OVERFLOWED(x) (ppc970_pmcn_read(x) & (0x1 << 31))
53 /* How PMC works on PPC970:
55 * Any PMC can count a direct event. Indirect events are handled specially.
56 * Direct events: As published.
58 * Encoding 00 000 -- Add byte lane bit counters
59 * MMCR1[24:31] -- select bit matching PMC being an adder.
61 * PMCxSEL: 1x -- select from byte lane: 10 == lower lane (0/1), 11 == upper
63 * PMCxSEL[2:4] -- bit in the byte lane selected.
65 * PMC[1,2,5,6] == lane 0/lane 2
66 * PMC[3,4,7,8] == lane 1,3
70 * Lane 0 -- TTM0(FPU,ISU,IFU,VPU)
81 * LSU1 byte 2 or byte 6
85 * LSU1 byte 3 or byte 7
88 * Add byte lane for PMC (above), bit 0+4, 1+5, 2+6, 3+7
91 struct pmc_ppc970_event {
92 enum pmc_event pe_event;
94 #define PMC_PPC970_FLAG_PMCS 0x000000ff
95 #define PMC_PPC970_FLAG_PMC1 0x01
96 #define PMC_PPC970_FLAG_PMC2 0x02
97 #define PMC_PPC970_FLAG_PMC3 0x04
98 #define PMC_PPC970_FLAG_PMC4 0x08
99 #define PMC_PPC970_FLAG_PMC5 0x10
100 #define PMC_PPC970_FLAG_PMC6 0x20
101 #define PMC_PPC970_FLAG_PMC7 0x40
102 #define PMC_PPC970_FLAG_PMC8 0x80
106 static struct pmc_ppc970_event ppc970_event_codes[] = {
107 {PMC_EV_PPC970_INSTR_COMPLETED,
108 .pe_flags = PMC_PPC970_FLAG_PMCS,
111 {PMC_EV_PPC970_MARKED_GROUP_DISPATCH,
112 .pe_flags = PMC_PPC970_FLAG_PMC1,
115 {PMC_EV_PPC970_MARKED_STORE_COMPLETED,
116 .pe_flags = PMC_PPC970_FLAG_PMC1,
119 {PMC_EV_PPC970_GCT_EMPTY,
120 .pe_flags = PMC_PPC970_FLAG_PMC1,
123 {PMC_EV_PPC970_RUN_CYCLES,
124 .pe_flags = PMC_PPC970_FLAG_PMC1,
127 {PMC_EV_PPC970_OVERFLOW,
128 .pe_flags = PMC_PPC970_FLAG_PMCS,
131 {PMC_EV_PPC970_CYCLES,
132 .pe_flags = PMC_PPC970_FLAG_PMCS,
135 {PMC_EV_PPC970_THRESHOLD_TIMEOUT,
136 .pe_flags = PMC_PPC970_FLAG_PMC2,
139 {PMC_EV_PPC970_GROUP_DISPATCH,
140 .pe_flags = PMC_PPC970_FLAG_PMC2,
143 {PMC_EV_PPC970_BR_MARKED_INSTR_FINISH,
144 .pe_flags = PMC_PPC970_FLAG_PMC2,
147 {PMC_EV_PPC970_GCT_EMPTY_BY_SRQ_FULL,
148 .pe_flags = PMC_PPC970_FLAG_PMC2,
151 {PMC_EV_PPC970_STOP_COMPLETION,
152 .pe_flags = PMC_PPC970_FLAG_PMC3,
155 {PMC_EV_PPC970_LSU_EMPTY,
156 .pe_flags = PMC_PPC970_FLAG_PMC3,
159 {PMC_EV_PPC970_MARKED_STORE_WITH_INTR,
160 .pe_flags = PMC_PPC970_FLAG_PMC3,
163 {PMC_EV_PPC970_CYCLES_IN_SUPER,
164 .pe_flags = PMC_PPC970_FLAG_PMC3,
167 {PMC_EV_PPC970_VPU_MARKED_INSTR_COMPLETED,
168 .pe_flags = PMC_PPC970_FLAG_PMC3,
171 {PMC_EV_PPC970_FXU0_IDLE_FXU1_BUSY,
172 .pe_flags = PMC_PPC970_FLAG_PMC4,
175 {PMC_EV_PPC970_SRQ_EMPTY,
176 .pe_flags = PMC_PPC970_FLAG_PMC4,
179 {PMC_EV_PPC970_MARKED_GROUP_COMPLETED,
180 .pe_flags = PMC_PPC970_FLAG_PMC4,
183 {PMC_EV_PPC970_CR_MARKED_INSTR_FINISH,
184 .pe_flags = PMC_PPC970_FLAG_PMC4,
187 {PMC_EV_PPC970_DISPATCH_SUCCESS,
188 .pe_flags = PMC_PPC970_FLAG_PMC5,
191 {PMC_EV_PPC970_FXU0_IDLE_FXU1_IDLE,
192 .pe_flags = PMC_PPC970_FLAG_PMC5,
195 {PMC_EV_PPC970_ONE_PLUS_INSTR_COMPLETED,
196 .pe_flags = PMC_PPC970_FLAG_PMC5,
199 {PMC_EV_PPC970_GROUP_MARKED_IDU,
200 .pe_flags = PMC_PPC970_FLAG_PMC5,
203 {PMC_EV_PPC970_MARKED_GROUP_COMPLETE_TIMEOUT,
204 .pe_flags = PMC_PPC970_FLAG_PMC5,
207 {PMC_EV_PPC970_FXU0_BUSY_FXU1_BUSY,
208 .pe_flags = PMC_PPC970_FLAG_PMC6,
211 {PMC_EV_PPC970_MARKED_STORE_SENT_TO_STS,
212 .pe_flags = PMC_PPC970_FLAG_PMC6,
215 {PMC_EV_PPC970_FXU_MARKED_INSTR_FINISHED,
216 .pe_flags = PMC_PPC970_FLAG_PMC6,
219 {PMC_EV_PPC970_MARKED_GROUP_ISSUED,
220 .pe_flags = PMC_PPC970_FLAG_PMC6,
223 {PMC_EV_PPC970_FXU0_BUSY_FXU1_IDLE,
224 .pe_flags = PMC_PPC970_FLAG_PMC7,
227 {PMC_EV_PPC970_GROUP_COMPLETED,
228 .pe_flags = PMC_PPC970_FLAG_PMC7,
231 {PMC_EV_PPC970_FPU_MARKED_INSTR_COMPLETED,
232 .pe_flags = PMC_PPC970_FLAG_PMC7,
235 {PMC_EV_PPC970_MARKED_INSTR_FINISH_ANY_UNIT,
236 .pe_flags = PMC_PPC970_FLAG_PMC7,
239 {PMC_EV_PPC970_EXTERNAL_INTERRUPT,
240 .pe_flags = PMC_PPC970_FLAG_PMC8,
243 {PMC_EV_PPC970_GROUP_DISPATCH_REJECT,
244 .pe_flags = PMC_PPC970_FLAG_PMC8,
247 {PMC_EV_PPC970_LSU_MARKED_INSTR_FINISH,
248 .pe_flags = PMC_PPC970_FLAG_PMC8,
251 {PMC_EV_PPC970_TIMEBASE_EVENT,
252 .pe_flags = PMC_PPC970_FLAG_PMC8,
256 {PMC_EV_PPC970_LSU_COMPLETION_STALL, },
257 {PMC_EV_PPC970_FXU_COMPLETION_STALL, },
258 {PMC_EV_PPC970_DCACHE_MISS_COMPLETION_STALL, },
259 {PMC_EV_PPC970_FPU_COMPLETION_STALL, },
260 {PMC_EV_PPC970_FXU_LONG_INSTR_COMPLETION_STALL, },
261 {PMC_EV_PPC970_REJECT_COMPLETION_STALL, },
262 {PMC_EV_PPC970_FPU_LONG_INSTR_COMPLETION_STALL, },
263 {PMC_EV_PPC970_GCT_EMPTY_BY_ICACHE_MISS, },
264 {PMC_EV_PPC970_REJECT_COMPLETION_STALL_ERAT_MISS, },
265 {PMC_EV_PPC970_GCT_EMPTY_BY_BRANCH_MISS_PREDICT, },
268 static size_t ppc970_event_codes_size = nitems(ppc970_event_codes);
271 ppc970_pmcn_read(unsigned int pmc)
277 val = mfspr(SPR_970PMC1);
280 val = mfspr(SPR_970PMC2);
283 val = mfspr(SPR_970PMC3);
286 val = mfspr(SPR_970PMC4);
289 val = mfspr(SPR_970PMC5);
292 val = mfspr(SPR_970PMC6);
295 val = mfspr(SPR_970PMC7);
298 val = mfspr(SPR_970PMC8);
301 panic("Invalid PMC number: %d\n", pmc);
308 ppc970_pmcn_write(unsigned int pmc, uint32_t val)
312 mtspr(SPR_970PMC1, val);
315 mtspr(SPR_970PMC2, val);
318 mtspr(SPR_970PMC3, val);
321 mtspr(SPR_970PMC4, val);
324 mtspr(SPR_970PMC5, val);
327 mtspr(SPR_970PMC6, val);
330 mtspr(SPR_970PMC7, val);
333 mtspr(SPR_970PMC8, val);
336 panic("Invalid PMC number: %d\n", pmc);
341 ppc970_config_pmc(int cpu, int ri, struct pmc *pm)
345 PMCDBG3(MDP,CFG,1, "cpu=%d ri=%d pm=%p", cpu, ri, pm);
347 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
348 ("[powerpc,%d] illegal CPU value %d", __LINE__, cpu));
349 KASSERT(ri >= 0 && ri < PPC970_MAX_PMCS,
350 ("[powerpc,%d] illegal row-index %d", __LINE__, ri));
352 phw = &powerpc_pcpu[cpu]->pc_ppcpmcs[ri];
354 KASSERT(pm == NULL || phw->phw_pmc == NULL,
355 ("[powerpc,%d] pm=%p phw->pm=%p hwpmc not unconfigured",
356 __LINE__, pm, phw->phw_pmc));
364 ppc970_set_pmc(int cpu, int ri, int config)
370 phw = &powerpc_pcpu[cpu]->pc_ppcpmcs[ri];
379 pmc_mmcr = mfspr(SPR_970MMCR0);
380 pmc_mmcr = PPC970_SET_MMCR0_PMCSEL(pmc_mmcr, config, ri);
381 mtspr(SPR_970MMCR0, pmc_mmcr);
389 pmc_mmcr = mfspr(SPR_970MMCR1);
390 pmc_mmcr = PPC970_SET_MMCR1_PMCSEL(pmc_mmcr, config, ri);
391 mtspr(SPR_970MMCR1, pmc_mmcr);
398 ppc970_start_pmc(int cpu, int ri)
406 phw = &powerpc_pcpu[cpu]->pc_ppcpmcs[ri];
408 config = pm->pm_md.pm_powerpc.pm_powerpc_evsel & ~POWERPC_PMC_ENABLE;
410 error = ppc970_set_pmc(cpu, ri, config);
412 /* The mask is inverted (enable is 1) compared to the flags in MMCR0, which
415 config = ~pm->pm_md.pm_powerpc.pm_powerpc_evsel & POWERPC_PMC_ENABLE;
417 pmc_mmcr = mfspr(SPR_970MMCR0);
418 pmc_mmcr &= ~SPR_MMCR0_FC;
420 mtspr(SPR_970MMCR0, pmc_mmcr);
426 ppc970_stop_pmc(int cpu, int ri)
428 return ppc970_set_pmc(cpu, ri, PMC970N_NONE);
432 ppc970_read_pmc(int cpu, int ri, pmc_value_t *v)
437 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
438 ("[powerpc,%d] illegal CPU value %d", __LINE__, cpu));
439 KASSERT(ri >= 0 && ri < PPC970_MAX_PMCS,
440 ("[powerpc,%d] illegal row index %d", __LINE__, ri));
442 pm = powerpc_pcpu[cpu]->pc_ppcpmcs[ri].phw_pmc;
444 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu,
447 tmp = ppc970_pmcn_read(ri);
448 PMCDBG2(MDP,REA,2,"ppc-read id=%d -> %jd", ri, tmp);
449 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
450 *v = POWERPC_PERFCTR_VALUE_TO_RELOAD_COUNT(tmp);
458 ppc970_write_pmc(int cpu, int ri, pmc_value_t v)
462 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
463 ("[powerpc,%d] illegal CPU value %d", __LINE__, cpu));
464 KASSERT(ri >= 0 && ri < PPC970_MAX_PMCS,
465 ("[powerpc,%d] illegal row-index %d", __LINE__, ri));
467 pm = powerpc_pcpu[cpu]->pc_ppcpmcs[ri].phw_pmc;
469 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
470 v = POWERPC_RELOAD_COUNT_TO_PERFCTR_VALUE(v);
472 PMCDBG3(MDP,WRI,1,"powerpc-write cpu=%d ri=%d v=%jx", cpu, ri, v);
474 ppc970_pmcn_write(ri, v);
480 ppc970_intr(int cpu, struct trapframe *tf)
483 struct powerpc_cpu *pac;
485 int i, error, retval;
487 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
488 ("[powerpc,%d] out of range CPU %d", __LINE__, cpu));
490 PMCDBG3(MDP,INT,1, "cpu=%d tf=%p um=%d", cpu, (void *) tf,
495 pac = powerpc_pcpu[cpu];
498 * look for all PMCs that have interrupted:
499 * - look for a running, sampling PMC which has overflowed
500 * and which has a valid 'struct pmc' association
502 * If found, we call a helper to process the interrupt.
505 config = mfspr(SPR_970MMCR0) & ~SPR_MMCR0_FC;
506 for (i = 0; i < PPC970_MAX_PMCS; i++) {
507 if ((pm = pac->pc_ppcpmcs[i].phw_pmc) == NULL ||
508 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) {
512 if (!PPC970_PMC_HAS_OVERFLOWED(i))
515 retval = 1; /* Found an interrupting PMC. */
517 if (pm->pm_state != PMC_STATE_RUNNING)
520 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf,
523 ppc970_stop_pmc(cpu, i);
525 /* reload sampling count. */
526 ppc970_write_pmc(cpu, i, pm->pm_sc.pm_reloadcount);
529 atomic_add_int(retval ? &pmc_stats.pm_intr_processed :
530 &pmc_stats.pm_intr_ignored, 1);
532 /* Re-enable PERF exceptions. */
534 mtspr(SPR_970MMCR0, config | SPR_MMCR0_PMXE);
540 ppc970_pcpu_init(struct pmc_mdep *md, int cpu)
543 struct powerpc_cpu *pac;
547 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
548 ("[powerpc,%d] wrong cpu number %d", __LINE__, cpu));
549 PMCDBG1(MDP,INI,1,"powerpc-init cpu=%d", cpu);
551 powerpc_pcpu[cpu] = pac = malloc(sizeof(struct powerpc_cpu), M_PMC,
553 pac->pc_ppcpmcs = malloc(sizeof(struct pmc_hw) * PPC970_MAX_PMCS,
554 M_PMC, M_WAITOK|M_ZERO);
555 pac->pc_class = PMC_CLASS_PPC970;
558 first_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_POWERPC].pcd_ri;
559 KASSERT(pc != NULL, ("[powerpc,%d] NULL per-cpu pointer", __LINE__));
561 for (i = 0, phw = pac->pc_ppcpmcs; i < PPC970_MAX_PMCS; i++, phw++) {
562 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED |
563 PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(i);
565 pc->pc_hwpmcs[i + first_ri] = phw;
568 /* Clear the MMCRs, and set FC, to disable all PMCs. */
569 /* 970 PMC is not counted when set to 0x08 */
570 mtspr(SPR_970MMCR0, SPR_MMCR0_FC | SPR_MMCR0_PMXE |
571 SPR_MMCR0_FCECE | SPR_MMCR0_PMC1CE | SPR_MMCR0_PMCNCE |
572 SPR_970MMCR0_PMC1SEL(0x8) | SPR_970MMCR0_PMC2SEL(0x8));
573 mtspr(SPR_970MMCR1, 0x4218420);
579 ppc970_pcpu_fini(struct pmc_mdep *md, int cpu)
581 register_t mmcr0 = mfspr(SPR_MMCR0);
583 mmcr0 |= SPR_MMCR0_FC;
584 mmcr0 &= ~SPR_MMCR0_PMXE;
585 mtspr(SPR_MMCR0, mmcr0);
587 free(powerpc_pcpu[cpu]->pc_ppcpmcs, M_PMC);
588 free(powerpc_pcpu[cpu], M_PMC);
594 ppc970_allocate_pmc(int cpu, int ri, struct pmc *pm,
595 const struct pmc_op_pmcallocate *a)
598 uint32_t caps, config = 0, counter = 0;
601 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
602 ("[powerpc,%d] illegal CPU value %d", __LINE__, cpu));
603 KASSERT(ri >= 0 && ri < PPC970_MAX_PMCS,
604 ("[powerpc,%d] illegal row index %d", __LINE__, ri));
610 if (pe < PMC_EV_PPC970_FIRST || pe > PMC_EV_PPC970_LAST)
613 for (i = 0; i < ppc970_event_codes_size; i++) {
614 if (ppc970_event_codes[i].pe_event == pe) {
615 config = ppc970_event_codes[i].pe_code;
616 counter = ppc970_event_codes[i].pe_flags;
620 if (i == ppc970_event_codes_size)
623 if ((counter & (1 << ri)) == 0)
626 if (caps & PMC_CAP_SYSTEM)
627 config |= POWERPC_PMC_KERNEL_ENABLE;
628 if (caps & PMC_CAP_USER)
629 config |= POWERPC_PMC_USER_ENABLE;
630 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0)
631 config |= POWERPC_PMC_ENABLE;
633 pm->pm_md.pm_powerpc.pm_powerpc_evsel = config;
635 PMCDBG2(MDP,ALL,2,"powerpc-allocate ri=%d -> config=0x%x", ri, config);
641 ppc970_release_pmc(int cpu, int ri, struct pmc *pmc)
645 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
646 ("[powerpc,%d] illegal CPU value %d", __LINE__, cpu));
647 KASSERT(ri >= 0 && ri < PPC970_MAX_PMCS,
648 ("[powerpc,%d] illegal row-index %d", __LINE__, ri));
650 phw = &powerpc_pcpu[cpu]->pc_ppcpmcs[ri];
651 KASSERT(phw->phw_pmc == NULL,
652 ("[powerpc,%d] PHW pmc %p non-NULL", __LINE__, phw->phw_pmc));
658 pmc_ppc970_initialize(struct pmc_mdep *pmc_mdep)
660 struct pmc_classdep *pcd;
662 pmc_mdep->pmd_cputype = PMC_CPU_PPC_970;
664 pcd = &pmc_mdep->pmd_classdep[PMC_MDEP_CLASS_INDEX_POWERPC];
665 pcd->pcd_caps = POWERPC_PMC_CAPS;
666 pcd->pcd_class = PMC_CLASS_PPC970;
667 pcd->pcd_num = PPC970_MAX_PMCS;
668 pcd->pcd_ri = pmc_mdep->pmd_npmc;
671 pcd->pcd_allocate_pmc = ppc970_allocate_pmc;
672 pcd->pcd_config_pmc = ppc970_config_pmc;
673 pcd->pcd_pcpu_fini = ppc970_pcpu_fini;
674 pcd->pcd_pcpu_init = ppc970_pcpu_init;
675 pcd->pcd_describe = powerpc_describe;
676 pcd->pcd_get_config = powerpc_get_config;
677 pcd->pcd_read_pmc = ppc970_read_pmc;
678 pcd->pcd_release_pmc = ppc970_release_pmc;
679 pcd->pcd_start_pmc = ppc970_start_pmc;
680 pcd->pcd_stop_pmc = ppc970_stop_pmc;
681 pcd->pcd_write_pmc = ppc970_write_pmc;
683 pmc_mdep->pmd_npmc += PPC970_MAX_PMCS;
684 pmc_mdep->pmd_intr = ppc970_intr;