2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2013 Justin Hibbits
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
35 #include <sys/pmckern.h>
36 #include <sys/systm.h>
38 #include <machine/pmc_mdep.h>
39 #include <machine/spr.h>
40 #include <machine/cpu.h>
42 #include "hwpmc_powerpc.h"
44 #define PPC970_MAX_PMCS 8
46 /* MMCR0, PMC1 is 8 bytes in, PMC2 is 1 byte in. */
47 #define PPC970_SET_MMCR0_PMCSEL(r, x, i) \
48 ((r & ~(0x1f << (7 * (1 - i) + 1))) | (x << (7 * (1 - i) + 1)))
49 /* MMCR1 has 6 PMC*SEL items (PMC3->PMC8), in sequence. */
50 #define PPC970_SET_MMCR1_PMCSEL(r, x, i) \
51 ((r & ~(0x1f << (5 * (7 - i) + 2))) | (x << (5 * (7 - i) + 2)))
53 #define PPC970_PMC_HAS_OVERFLOWED(x) (ppc970_pmcn_read(x) & (0x1 << 31))
55 /* How PMC works on PPC970:
57 * Any PMC can count a direct event. Indirect events are handled specially.
58 * Direct events: As published.
60 * Encoding 00 000 -- Add byte lane bit counters
61 * MMCR1[24:31] -- select bit matching PMC being an adder.
63 * PMCxSEL: 1x -- select from byte lane: 10 == lower lane (0/1), 11 == upper
65 * PMCxSEL[2:4] -- bit in the byte lane selected.
67 * PMC[1,2,5,6] == lane 0/lane 2
68 * PMC[3,4,7,8] == lane 1,3
72 * Lane 0 -- TTM0(FPU,ISU,IFU,VPU)
83 * LSU1 byte 2 or byte 6
87 * LSU1 byte 3 or byte 7
90 * Add byte lane for PMC (above), bit 0+4, 1+5, 2+6, 3+7
93 struct pmc_ppc970_event {
94 enum pmc_event pe_event;
96 #define PMC_PPC970_FLAG_PMCS 0x000000ff
97 #define PMC_PPC970_FLAG_PMC1 0x01
98 #define PMC_PPC970_FLAG_PMC2 0x02
99 #define PMC_PPC970_FLAG_PMC3 0x04
100 #define PMC_PPC970_FLAG_PMC4 0x08
101 #define PMC_PPC970_FLAG_PMC5 0x10
102 #define PMC_PPC970_FLAG_PMC6 0x20
103 #define PMC_PPC970_FLAG_PMC7 0x40
104 #define PMC_PPC970_FLAG_PMC8 0x80
108 static struct pmc_ppc970_event ppc970_event_codes[] = {
109 {PMC_EV_PPC970_INSTR_COMPLETED,
110 .pe_flags = PMC_PPC970_FLAG_PMCS,
113 {PMC_EV_PPC970_MARKED_GROUP_DISPATCH,
114 .pe_flags = PMC_PPC970_FLAG_PMC1,
117 {PMC_EV_PPC970_MARKED_STORE_COMPLETED,
118 .pe_flags = PMC_PPC970_FLAG_PMC1,
121 {PMC_EV_PPC970_GCT_EMPTY,
122 .pe_flags = PMC_PPC970_FLAG_PMC1,
125 {PMC_EV_PPC970_RUN_CYCLES,
126 .pe_flags = PMC_PPC970_FLAG_PMC1,
129 {PMC_EV_PPC970_OVERFLOW,
130 .pe_flags = PMC_PPC970_FLAG_PMCS,
133 {PMC_EV_PPC970_CYCLES,
134 .pe_flags = PMC_PPC970_FLAG_PMCS,
137 {PMC_EV_PPC970_THRESHOLD_TIMEOUT,
138 .pe_flags = PMC_PPC970_FLAG_PMC2,
141 {PMC_EV_PPC970_GROUP_DISPATCH,
142 .pe_flags = PMC_PPC970_FLAG_PMC2,
145 {PMC_EV_PPC970_BR_MARKED_INSTR_FINISH,
146 .pe_flags = PMC_PPC970_FLAG_PMC2,
149 {PMC_EV_PPC970_GCT_EMPTY_BY_SRQ_FULL,
150 .pe_flags = PMC_PPC970_FLAG_PMC2,
153 {PMC_EV_PPC970_STOP_COMPLETION,
154 .pe_flags = PMC_PPC970_FLAG_PMC3,
157 {PMC_EV_PPC970_LSU_EMPTY,
158 .pe_flags = PMC_PPC970_FLAG_PMC3,
161 {PMC_EV_PPC970_MARKED_STORE_WITH_INTR,
162 .pe_flags = PMC_PPC970_FLAG_PMC3,
165 {PMC_EV_PPC970_CYCLES_IN_SUPER,
166 .pe_flags = PMC_PPC970_FLAG_PMC3,
169 {PMC_EV_PPC970_VPU_MARKED_INSTR_COMPLETED,
170 .pe_flags = PMC_PPC970_FLAG_PMC3,
173 {PMC_EV_PPC970_FXU0_IDLE_FXU1_BUSY,
174 .pe_flags = PMC_PPC970_FLAG_PMC4,
177 {PMC_EV_PPC970_SRQ_EMPTY,
178 .pe_flags = PMC_PPC970_FLAG_PMC4,
181 {PMC_EV_PPC970_MARKED_GROUP_COMPLETED,
182 .pe_flags = PMC_PPC970_FLAG_PMC4,
185 {PMC_EV_PPC970_CR_MARKED_INSTR_FINISH,
186 .pe_flags = PMC_PPC970_FLAG_PMC4,
189 {PMC_EV_PPC970_DISPATCH_SUCCESS,
190 .pe_flags = PMC_PPC970_FLAG_PMC5,
193 {PMC_EV_PPC970_FXU0_IDLE_FXU1_IDLE,
194 .pe_flags = PMC_PPC970_FLAG_PMC5,
197 {PMC_EV_PPC970_ONE_PLUS_INSTR_COMPLETED,
198 .pe_flags = PMC_PPC970_FLAG_PMC5,
201 {PMC_EV_PPC970_GROUP_MARKED_IDU,
202 .pe_flags = PMC_PPC970_FLAG_PMC5,
205 {PMC_EV_PPC970_MARKED_GROUP_COMPLETE_TIMEOUT,
206 .pe_flags = PMC_PPC970_FLAG_PMC5,
209 {PMC_EV_PPC970_FXU0_BUSY_FXU1_BUSY,
210 .pe_flags = PMC_PPC970_FLAG_PMC6,
213 {PMC_EV_PPC970_MARKED_STORE_SENT_TO_STS,
214 .pe_flags = PMC_PPC970_FLAG_PMC6,
217 {PMC_EV_PPC970_FXU_MARKED_INSTR_FINISHED,
218 .pe_flags = PMC_PPC970_FLAG_PMC6,
221 {PMC_EV_PPC970_MARKED_GROUP_ISSUED,
222 .pe_flags = PMC_PPC970_FLAG_PMC6,
225 {PMC_EV_PPC970_FXU0_BUSY_FXU1_IDLE,
226 .pe_flags = PMC_PPC970_FLAG_PMC7,
229 {PMC_EV_PPC970_GROUP_COMPLETED,
230 .pe_flags = PMC_PPC970_FLAG_PMC7,
233 {PMC_EV_PPC970_FPU_MARKED_INSTR_COMPLETED,
234 .pe_flags = PMC_PPC970_FLAG_PMC7,
237 {PMC_EV_PPC970_MARKED_INSTR_FINISH_ANY_UNIT,
238 .pe_flags = PMC_PPC970_FLAG_PMC7,
241 {PMC_EV_PPC970_EXTERNAL_INTERRUPT,
242 .pe_flags = PMC_PPC970_FLAG_PMC8,
245 {PMC_EV_PPC970_GROUP_DISPATCH_REJECT,
246 .pe_flags = PMC_PPC970_FLAG_PMC8,
249 {PMC_EV_PPC970_LSU_MARKED_INSTR_FINISH,
250 .pe_flags = PMC_PPC970_FLAG_PMC8,
253 {PMC_EV_PPC970_TIMEBASE_EVENT,
254 .pe_flags = PMC_PPC970_FLAG_PMC8,
258 {PMC_EV_PPC970_LSU_COMPLETION_STALL, },
259 {PMC_EV_PPC970_FXU_COMPLETION_STALL, },
260 {PMC_EV_PPC970_DCACHE_MISS_COMPLETION_STALL, },
261 {PMC_EV_PPC970_FPU_COMPLETION_STALL, },
262 {PMC_EV_PPC970_FXU_LONG_INSTR_COMPLETION_STALL, },
263 {PMC_EV_PPC970_REJECT_COMPLETION_STALL, },
264 {PMC_EV_PPC970_FPU_LONG_INSTR_COMPLETION_STALL, },
265 {PMC_EV_PPC970_GCT_EMPTY_BY_ICACHE_MISS, },
266 {PMC_EV_PPC970_REJECT_COMPLETION_STALL_ERAT_MISS, },
267 {PMC_EV_PPC970_GCT_EMPTY_BY_BRANCH_MISS_PREDICT, },
270 static size_t ppc970_event_codes_size = nitems(ppc970_event_codes);
273 ppc970_pmcn_read(unsigned int pmc)
279 val = mfspr(SPR_970PMC1);
282 val = mfspr(SPR_970PMC2);
285 val = mfspr(SPR_970PMC3);
288 val = mfspr(SPR_970PMC4);
291 val = mfspr(SPR_970PMC5);
294 val = mfspr(SPR_970PMC6);
297 val = mfspr(SPR_970PMC7);
300 val = mfspr(SPR_970PMC8);
303 panic("Invalid PMC number: %d\n", pmc);
310 ppc970_pmcn_write(unsigned int pmc, uint32_t val)
314 mtspr(SPR_970PMC1, val);
317 mtspr(SPR_970PMC2, val);
320 mtspr(SPR_970PMC3, val);
323 mtspr(SPR_970PMC4, val);
326 mtspr(SPR_970PMC5, val);
329 mtspr(SPR_970PMC6, val);
332 mtspr(SPR_970PMC7, val);
335 mtspr(SPR_970PMC8, val);
338 panic("Invalid PMC number: %d\n", pmc);
343 ppc970_config_pmc(int cpu, int ri, struct pmc *pm)
347 PMCDBG3(MDP,CFG,1, "cpu=%d ri=%d pm=%p", cpu, ri, pm);
349 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
350 ("[powerpc,%d] illegal CPU value %d", __LINE__, cpu));
351 KASSERT(ri >= 0 && ri < PPC970_MAX_PMCS,
352 ("[powerpc,%d] illegal row-index %d", __LINE__, ri));
354 phw = &powerpc_pcpu[cpu]->pc_ppcpmcs[ri];
356 KASSERT(pm == NULL || phw->phw_pmc == NULL,
357 ("[powerpc,%d] pm=%p phw->pm=%p hwpmc not unconfigured",
358 __LINE__, pm, phw->phw_pmc));
366 ppc970_set_pmc(int cpu, int ri, int config)
372 phw = &powerpc_pcpu[cpu]->pc_ppcpmcs[ri];
381 pmc_mmcr = mfspr(SPR_970MMCR0);
382 pmc_mmcr = PPC970_SET_MMCR0_PMCSEL(pmc_mmcr, config, ri);
383 mtspr(SPR_970MMCR0, pmc_mmcr);
391 pmc_mmcr = mfspr(SPR_970MMCR1);
392 pmc_mmcr = PPC970_SET_MMCR1_PMCSEL(pmc_mmcr, config, ri);
393 mtspr(SPR_970MMCR1, pmc_mmcr);
400 ppc970_start_pmc(int cpu, int ri)
408 phw = &powerpc_pcpu[cpu]->pc_ppcpmcs[ri];
410 config = pm->pm_md.pm_powerpc.pm_powerpc_evsel & ~POWERPC_PMC_ENABLE;
412 error = ppc970_set_pmc(cpu, ri, config);
414 /* The mask is inverted (enable is 1) compared to the flags in MMCR0, which
417 config = ~pm->pm_md.pm_powerpc.pm_powerpc_evsel & POWERPC_PMC_ENABLE;
419 pmc_mmcr = mfspr(SPR_970MMCR0);
420 pmc_mmcr &= ~SPR_MMCR0_FC;
422 mtspr(SPR_970MMCR0, pmc_mmcr);
428 ppc970_stop_pmc(int cpu, int ri)
430 return ppc970_set_pmc(cpu, ri, PMC970N_NONE);
434 ppc970_read_pmc(int cpu, int ri, pmc_value_t *v)
439 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
440 ("[powerpc,%d] illegal CPU value %d", __LINE__, cpu));
441 KASSERT(ri >= 0 && ri < PPC970_MAX_PMCS,
442 ("[powerpc,%d] illegal row index %d", __LINE__, ri));
444 pm = powerpc_pcpu[cpu]->pc_ppcpmcs[ri].phw_pmc;
446 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu,
449 tmp = ppc970_pmcn_read(ri);
450 PMCDBG2(MDP,REA,2,"ppc-read id=%d -> %jd", ri, tmp);
451 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
452 *v = POWERPC_PERFCTR_VALUE_TO_RELOAD_COUNT(tmp);
460 ppc970_write_pmc(int cpu, int ri, pmc_value_t v)
464 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
465 ("[powerpc,%d] illegal CPU value %d", __LINE__, cpu));
466 KASSERT(ri >= 0 && ri < PPC970_MAX_PMCS,
467 ("[powerpc,%d] illegal row-index %d", __LINE__, ri));
469 pm = powerpc_pcpu[cpu]->pc_ppcpmcs[ri].phw_pmc;
471 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
472 v = POWERPC_RELOAD_COUNT_TO_PERFCTR_VALUE(v);
474 PMCDBG3(MDP,WRI,1,"powerpc-write cpu=%d ri=%d v=%jx", cpu, ri, v);
476 ppc970_pmcn_write(ri, v);
482 ppc970_intr(int cpu, struct trapframe *tf)
485 struct powerpc_cpu *pac;
487 int i, error, retval;
489 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
490 ("[powerpc,%d] out of range CPU %d", __LINE__, cpu));
492 PMCDBG3(MDP,INT,1, "cpu=%d tf=%p um=%d", cpu, (void *) tf,
497 pac = powerpc_pcpu[cpu];
500 * look for all PMCs that have interrupted:
501 * - look for a running, sampling PMC which has overflowed
502 * and which has a valid 'struct pmc' association
504 * If found, we call a helper to process the interrupt.
507 config = mfspr(SPR_970MMCR0) & ~SPR_MMCR0_FC;
508 for (i = 0; i < PPC970_MAX_PMCS; i++) {
509 if ((pm = pac->pc_ppcpmcs[i].phw_pmc) == NULL ||
510 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) {
514 if (!PPC970_PMC_HAS_OVERFLOWED(i))
517 retval = 1; /* Found an interrupting PMC. */
519 if (pm->pm_state != PMC_STATE_RUNNING)
522 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf,
525 ppc970_stop_pmc(cpu, i);
527 /* reload sampling count. */
528 ppc970_write_pmc(cpu, i, pm->pm_sc.pm_reloadcount);
531 atomic_add_int(retval ? &pmc_stats.pm_intr_processed :
532 &pmc_stats.pm_intr_ignored, 1);
534 /* Re-enable PERF exceptions. */
536 mtspr(SPR_970MMCR0, config | SPR_MMCR0_PMXE);
542 ppc970_pcpu_init(struct pmc_mdep *md, int cpu)
545 struct powerpc_cpu *pac;
549 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
550 ("[powerpc,%d] wrong cpu number %d", __LINE__, cpu));
551 PMCDBG1(MDP,INI,1,"powerpc-init cpu=%d", cpu);
553 powerpc_pcpu[cpu] = pac = malloc(sizeof(struct powerpc_cpu), M_PMC,
555 pac->pc_ppcpmcs = malloc(sizeof(struct pmc_hw) * PPC970_MAX_PMCS,
556 M_PMC, M_WAITOK|M_ZERO);
557 pac->pc_class = PMC_CLASS_PPC970;
560 first_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_POWERPC].pcd_ri;
561 KASSERT(pc != NULL, ("[powerpc,%d] NULL per-cpu pointer", __LINE__));
563 for (i = 0, phw = pac->pc_ppcpmcs; i < PPC970_MAX_PMCS; i++, phw++) {
564 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED |
565 PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(i);
567 pc->pc_hwpmcs[i + first_ri] = phw;
570 /* Clear the MMCRs, and set FC, to disable all PMCs. */
571 /* 970 PMC is not counted when set to 0x08 */
572 mtspr(SPR_970MMCR0, SPR_MMCR0_FC | SPR_MMCR0_PMXE |
573 SPR_MMCR0_FCECE | SPR_MMCR0_PMC1CE | SPR_MMCR0_PMCNCE |
574 SPR_970MMCR0_PMC1SEL(0x8) | SPR_970MMCR0_PMC2SEL(0x8));
575 mtspr(SPR_970MMCR1, 0x4218420);
581 ppc970_pcpu_fini(struct pmc_mdep *md, int cpu)
583 register_t mmcr0 = mfspr(SPR_MMCR0);
585 mmcr0 |= SPR_MMCR0_FC;
586 mmcr0 &= ~SPR_MMCR0_PMXE;
587 mtspr(SPR_MMCR0, mmcr0);
589 free(powerpc_pcpu[cpu]->pc_ppcpmcs, M_PMC);
590 free(powerpc_pcpu[cpu], M_PMC);
596 ppc970_allocate_pmc(int cpu, int ri, struct pmc *pm,
597 const struct pmc_op_pmcallocate *a)
600 uint32_t caps, config = 0, counter = 0;
603 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
604 ("[powerpc,%d] illegal CPU value %d", __LINE__, cpu));
605 KASSERT(ri >= 0 && ri < PPC970_MAX_PMCS,
606 ("[powerpc,%d] illegal row index %d", __LINE__, ri));
612 if (pe < PMC_EV_PPC970_FIRST || pe > PMC_EV_PPC970_LAST)
615 for (i = 0; i < ppc970_event_codes_size; i++) {
616 if (ppc970_event_codes[i].pe_event == pe) {
617 config = ppc970_event_codes[i].pe_code;
618 counter = ppc970_event_codes[i].pe_flags;
622 if (i == ppc970_event_codes_size)
625 if ((counter & (1 << ri)) == 0)
628 if (caps & PMC_CAP_SYSTEM)
629 config |= POWERPC_PMC_KERNEL_ENABLE;
630 if (caps & PMC_CAP_USER)
631 config |= POWERPC_PMC_USER_ENABLE;
632 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0)
633 config |= POWERPC_PMC_ENABLE;
635 pm->pm_md.pm_powerpc.pm_powerpc_evsel = config;
637 PMCDBG2(MDP,ALL,2,"powerpc-allocate ri=%d -> config=0x%x", ri, config);
643 ppc970_release_pmc(int cpu, int ri, struct pmc *pmc)
647 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
648 ("[powerpc,%d] illegal CPU value %d", __LINE__, cpu));
649 KASSERT(ri >= 0 && ri < PPC970_MAX_PMCS,
650 ("[powerpc,%d] illegal row-index %d", __LINE__, ri));
652 phw = &powerpc_pcpu[cpu]->pc_ppcpmcs[ri];
653 KASSERT(phw->phw_pmc == NULL,
654 ("[powerpc,%d] PHW pmc %p non-NULL", __LINE__, phw->phw_pmc));
660 pmc_ppc970_initialize(struct pmc_mdep *pmc_mdep)
662 struct pmc_classdep *pcd;
664 pmc_mdep->pmd_cputype = PMC_CPU_PPC_970;
666 pcd = &pmc_mdep->pmd_classdep[PMC_MDEP_CLASS_INDEX_POWERPC];
667 pcd->pcd_caps = POWERPC_PMC_CAPS;
668 pcd->pcd_class = PMC_CLASS_PPC970;
669 pcd->pcd_num = PPC970_MAX_PMCS;
670 pcd->pcd_ri = pmc_mdep->pmd_npmc;
673 pcd->pcd_allocate_pmc = ppc970_allocate_pmc;
674 pcd->pcd_config_pmc = ppc970_config_pmc;
675 pcd->pcd_pcpu_fini = ppc970_pcpu_fini;
676 pcd->pcd_pcpu_init = ppc970_pcpu_init;
677 pcd->pcd_describe = powerpc_describe;
678 pcd->pcd_get_config = powerpc_get_config;
679 pcd->pcd_read_pmc = ppc970_read_pmc;
680 pcd->pcd_release_pmc = ppc970_release_pmc;
681 pcd->pcd_start_pmc = ppc970_start_pmc;
682 pcd->pcd_stop_pmc = ppc970_stop_pmc;
683 pcd->pcd_write_pmc = ppc970_write_pmc;
685 pmc_mdep->pmd_npmc += PPC970_MAX_PMCS;
686 pmc_mdep->pmd_intr = ppc970_intr;