2 * Copyright (c) 2010 Fabien Thomas
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
37 #include <sys/pmckern.h>
38 #include <sys/systm.h>
40 #include <machine/intr_machdep.h>
41 #if (__FreeBSD_version >= 1100000)
42 #include <x86/apicvar.h>
44 #include <machine/apicvar.h>
46 #include <machine/cpu.h>
47 #include <machine/cpufunc.h>
48 #include <machine/specialreg.h>
50 #define UCF_PMC_CAPS \
51 (PMC_CAP_READ | PMC_CAP_WRITE)
53 #define UCP_PMC_CAPS \
54 (PMC_CAP_EDGE | PMC_CAP_THRESHOLD | PMC_CAP_READ | PMC_CAP_WRITE | \
55 PMC_CAP_INVERT | PMC_CAP_QUALIFIER | PMC_CAP_PRECISE)
57 #define SELECTSEL(x) \
58 (((x) == PMC_CPU_INTEL_SANDYBRIDGE || (x) == PMC_CPU_INTEL_HASWELL) ? \
59 UCP_CB0_EVSEL0 : UCP_EVSEL0)
61 #define SELECTOFF(x) \
62 (((x) == PMC_CPU_INTEL_SANDYBRIDGE || (x) == PMC_CPU_INTEL_HASWELL) ? \
63 UCF_OFFSET_SB : UCF_OFFSET)
65 static enum pmc_cputype uncore_cputype;
68 volatile uint32_t pc_resync;
69 volatile uint32_t pc_ucfctrl; /* Fixed function control. */
70 volatile uint64_t pc_globalctrl; /* Global control register. */
71 struct pmc_hw pc_uncorepmcs[];
74 static struct uncore_cpu **uncore_pcpu;
76 static uint64_t uncore_pmcmask;
78 static int uncore_ucf_ri; /* relative index of fixed counters */
79 static int uncore_ucf_width;
80 static int uncore_ucf_npmc;
82 static int uncore_ucp_width;
83 static int uncore_ucp_npmc;
86 uncore_pcpu_noop(struct pmc_mdep *md, int cpu)
94 uncore_pcpu_init(struct pmc_mdep *md, int cpu)
97 struct uncore_cpu *cc;
99 int uncore_ri, n, npmc;
101 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
102 ("[ucf,%d] insane cpu number %d", __LINE__, cpu));
104 PMCDBG1(MDP,INI,1,"uncore-init cpu=%d", cpu);
106 uncore_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCP].pcd_ri;
107 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCP].pcd_num;
108 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCF].pcd_num;
110 cc = malloc(sizeof(struct uncore_cpu) + npmc * sizeof(struct pmc_hw),
111 M_PMC, M_WAITOK | M_ZERO);
113 uncore_pcpu[cpu] = cc;
116 KASSERT(pc != NULL && cc != NULL,
117 ("[uncore,%d] NULL per-cpu structures cpu=%d", __LINE__, cpu));
119 for (n = 0, phw = cc->pc_uncorepmcs; n < npmc; n++, phw++) {
120 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED |
121 PMC_PHW_CPU_TO_STATE(cpu) |
122 PMC_PHW_INDEX_TO_STATE(n + uncore_ri);
124 pc->pc_hwpmcs[n + uncore_ri] = phw;
131 uncore_pcpu_fini(struct pmc_mdep *md, int cpu)
133 int uncore_ri, n, npmc;
135 struct uncore_cpu *cc;
137 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
138 ("[uncore,%d] insane cpu number (%d)", __LINE__, cpu));
140 PMCDBG1(MDP,INI,1,"uncore-pcpu-fini cpu=%d", cpu);
142 if ((cc = uncore_pcpu[cpu]) == NULL)
145 uncore_pcpu[cpu] = NULL;
149 KASSERT(pc != NULL, ("[uncore,%d] NULL per-cpu %d state", __LINE__,
152 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCP].pcd_num;
153 uncore_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCP].pcd_ri;
155 for (n = 0; n < npmc; n++)
156 wrmsr(SELECTSEL(uncore_cputype) + n, 0);
159 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCF].pcd_num;
161 for (n = 0; n < npmc; n++)
162 pc->pc_hwpmcs[n + uncore_ri] = NULL;
170 * Fixed function counters.
174 ucf_perfctr_value_to_reload_count(pmc_value_t v)
176 v &= (1ULL << uncore_ucf_width) - 1;
177 return (1ULL << uncore_ucf_width) - v;
181 ucf_reload_count_to_perfctr_value(pmc_value_t rlc)
183 return (1ULL << uncore_ucf_width) - rlc;
187 ucf_allocate_pmc(int cpu, int ri, struct pmc *pm,
188 const struct pmc_op_pmcallocate *a)
191 uint32_t caps, flags;
193 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
194 ("[uncore,%d] illegal CPU %d", __LINE__, cpu));
196 PMCDBG2(MDP,ALL,1, "ucf-allocate ri=%d reqcaps=0x%x", ri, pm->pm_caps);
198 if (ri < 0 || ri > uncore_ucf_npmc)
203 if (a->pm_class != PMC_CLASS_UCF ||
204 (caps & UCF_PMC_CAPS) != caps)
208 if (ev < PMC_EV_UCF_FIRST || ev > PMC_EV_UCF_LAST)
213 pm->pm_md.pm_ucf.pm_ucf_ctrl = (flags << (ri * 4));
215 PMCDBG1(MDP,ALL,2, "ucf-allocate config=0x%jx",
216 (uintmax_t) pm->pm_md.pm_ucf.pm_ucf_ctrl);
222 ucf_config_pmc(int cpu, int ri, struct pmc *pm)
224 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
225 ("[uncore,%d] illegal CPU %d", __LINE__, cpu));
227 KASSERT(ri >= 0 && ri < uncore_ucf_npmc,
228 ("[uncore,%d] illegal row-index %d", __LINE__, ri));
230 PMCDBG3(MDP,CFG,1, "ucf-config cpu=%d ri=%d pm=%p", cpu, ri, pm);
232 KASSERT(uncore_pcpu[cpu] != NULL, ("[uncore,%d] null per-cpu %d", __LINE__,
235 uncore_pcpu[cpu]->pc_uncorepmcs[ri + uncore_ucf_ri].phw_pmc = pm;
241 ucf_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
245 char ucf_name[PMC_NAME_MAX];
247 phw = &uncore_pcpu[cpu]->pc_uncorepmcs[ri + uncore_ucf_ri];
249 (void) snprintf(ucf_name, sizeof(ucf_name), "UCF-%d", ri);
250 if ((error = copystr(ucf_name, pi->pm_name, PMC_NAME_MAX,
254 pi->pm_class = PMC_CLASS_UCF;
256 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
257 pi->pm_enabled = TRUE;
258 *ppmc = phw->phw_pmc;
260 pi->pm_enabled = FALSE;
268 ucf_get_config(int cpu, int ri, struct pmc **ppm)
270 *ppm = uncore_pcpu[cpu]->pc_uncorepmcs[ri + uncore_ucf_ri].phw_pmc;
276 ucf_read_pmc(int cpu, int ri, pmc_value_t *v)
281 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
282 ("[uncore,%d] illegal cpu value %d", __LINE__, cpu));
283 KASSERT(ri >= 0 && ri < uncore_ucf_npmc,
284 ("[uncore,%d] illegal row-index %d", __LINE__, ri));
286 pm = uncore_pcpu[cpu]->pc_uncorepmcs[ri + uncore_ucf_ri].phw_pmc;
289 ("[uncore,%d] cpu %d ri %d(%d) pmc not configured", __LINE__, cpu,
290 ri, ri + uncore_ucf_ri));
292 tmp = rdmsr(UCF_CTR0 + ri);
294 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
295 *v = ucf_perfctr_value_to_reload_count(tmp);
299 PMCDBG3(MDP,REA,1, "ucf-read cpu=%d ri=%d -> v=%jx", cpu, ri, *v);
305 ucf_release_pmc(int cpu, int ri, struct pmc *pmc)
307 PMCDBG3(MDP,REL,1, "ucf-release cpu=%d ri=%d pm=%p", cpu, ri, pmc);
309 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
310 ("[uncore,%d] illegal CPU value %d", __LINE__, cpu));
311 KASSERT(ri >= 0 && ri < uncore_ucf_npmc,
312 ("[uncore,%d] illegal row-index %d", __LINE__, ri));
314 KASSERT(uncore_pcpu[cpu]->pc_uncorepmcs[ri + uncore_ucf_ri].phw_pmc == NULL,
315 ("[uncore,%d] PHW pmc non-NULL", __LINE__));
321 ucf_start_pmc(int cpu, int ri)
324 struct uncore_cpu *ucfc;
326 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
327 ("[uncore,%d] illegal CPU value %d", __LINE__, cpu));
328 KASSERT(ri >= 0 && ri < uncore_ucf_npmc,
329 ("[uncore,%d] illegal row-index %d", __LINE__, ri));
331 PMCDBG2(MDP,STA,1,"ucf-start cpu=%d ri=%d", cpu, ri);
333 ucfc = uncore_pcpu[cpu];
334 pm = ucfc->pc_uncorepmcs[ri + uncore_ucf_ri].phw_pmc;
336 ucfc->pc_ucfctrl |= pm->pm_md.pm_ucf.pm_ucf_ctrl;
338 wrmsr(UCF_CTRL, ucfc->pc_ucfctrl);
342 ucfc->pc_globalctrl |= (1ULL << (ri + SELECTOFF(uncore_cputype)));
343 wrmsr(UC_GLOBAL_CTRL, ucfc->pc_globalctrl);
344 } while (ucfc->pc_resync != 0);
346 PMCDBG4(MDP,STA,1,"ucfctrl=%x(%x) globalctrl=%jx(%jx)",
347 ucfc->pc_ucfctrl, (uint32_t) rdmsr(UCF_CTRL),
348 ucfc->pc_globalctrl, rdmsr(UC_GLOBAL_CTRL));
354 ucf_stop_pmc(int cpu, int ri)
357 struct uncore_cpu *ucfc;
359 PMCDBG2(MDP,STO,1,"ucf-stop cpu=%d ri=%d", cpu, ri);
361 ucfc = uncore_pcpu[cpu];
363 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
364 ("[uncore,%d] illegal CPU value %d", __LINE__, cpu));
365 KASSERT(ri >= 0 && ri < uncore_ucf_npmc,
366 ("[uncore,%d] illegal row-index %d", __LINE__, ri));
368 fc = (UCF_MASK << (ri * 4));
370 ucfc->pc_ucfctrl &= ~fc;
372 PMCDBG1(MDP,STO,1,"ucf-stop ucfctrl=%x", ucfc->pc_ucfctrl);
373 wrmsr(UCF_CTRL, ucfc->pc_ucfctrl);
377 ucfc->pc_globalctrl &= ~(1ULL << (ri + SELECTOFF(uncore_cputype)));
378 wrmsr(UC_GLOBAL_CTRL, ucfc->pc_globalctrl);
379 } while (ucfc->pc_resync != 0);
381 PMCDBG4(MDP,STO,1,"ucfctrl=%x(%x) globalctrl=%jx(%jx)",
382 ucfc->pc_ucfctrl, (uint32_t) rdmsr(UCF_CTRL),
383 ucfc->pc_globalctrl, rdmsr(UC_GLOBAL_CTRL));
389 ucf_write_pmc(int cpu, int ri, pmc_value_t v)
391 struct uncore_cpu *cc;
394 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
395 ("[uncore,%d] illegal cpu value %d", __LINE__, cpu));
396 KASSERT(ri >= 0 && ri < uncore_ucf_npmc,
397 ("[uncore,%d] illegal row-index %d", __LINE__, ri));
399 cc = uncore_pcpu[cpu];
400 pm = cc->pc_uncorepmcs[ri + uncore_ucf_ri].phw_pmc;
403 ("[uncore,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, ri));
405 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
406 v = ucf_reload_count_to_perfctr_value(v);
408 wrmsr(UCF_CTRL, 0); /* Turn off fixed counters */
409 wrmsr(UCF_CTR0 + ri, v);
410 wrmsr(UCF_CTRL, cc->pc_ucfctrl);
412 PMCDBG4(MDP,WRI,1, "ucf-write cpu=%d ri=%d v=%jx ucfctrl=%jx ",
413 cpu, ri, v, (uintmax_t) rdmsr(UCF_CTRL));
420 ucf_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth)
422 struct pmc_classdep *pcd;
424 KASSERT(md != NULL, ("[ucf,%d] md is NULL", __LINE__));
426 PMCDBG0(MDP,INI,1, "ucf-initialize");
428 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCF];
430 pcd->pcd_caps = UCF_PMC_CAPS;
431 pcd->pcd_class = PMC_CLASS_UCF;
433 pcd->pcd_ri = md->pmd_npmc;
434 pcd->pcd_width = pmcwidth;
436 pcd->pcd_allocate_pmc = ucf_allocate_pmc;
437 pcd->pcd_config_pmc = ucf_config_pmc;
438 pcd->pcd_describe = ucf_describe;
439 pcd->pcd_get_config = ucf_get_config;
440 pcd->pcd_get_msr = NULL;
441 pcd->pcd_pcpu_fini = uncore_pcpu_noop;
442 pcd->pcd_pcpu_init = uncore_pcpu_noop;
443 pcd->pcd_read_pmc = ucf_read_pmc;
444 pcd->pcd_release_pmc = ucf_release_pmc;
445 pcd->pcd_start_pmc = ucf_start_pmc;
446 pcd->pcd_stop_pmc = ucf_stop_pmc;
447 pcd->pcd_write_pmc = ucf_write_pmc;
449 md->pmd_npmc += npmc;
453 * Intel programmable PMCs.
457 * Event descriptor tables.
459 * For each event id, we track:
461 * 1. The CPUs that the event is valid for.
463 * 2. If the event uses a fixed UMASK, the value of the umask field.
464 * If the event doesn't use a fixed UMASK, a mask of legal bits
468 struct ucp_event_descr {
469 enum pmc_event ucp_ev;
470 unsigned char ucp_evcode;
471 unsigned char ucp_umask;
472 unsigned char ucp_flags;
475 #define UCP_F_I7 (1 << 0) /* CPU: Core i7 */
476 #define UCP_F_WM (1 << 1) /* CPU: Westmere */
477 #define UCP_F_SB (1 << 2) /* CPU: Sandy Bridge */
478 #define UCP_F_HW (1 << 3) /* CPU: Haswell */
479 #define UCP_F_FM (1 << 4) /* Fixed mask */
481 #define UCP_F_ALLCPUS \
482 (UCP_F_I7 | UCP_F_WM)
484 #define UCP_F_CMASK 0xFF000000
486 static struct ucp_event_descr ucp_events[] = {
488 #define UCPDESCR(N,EV,UM,FLAGS) { \
489 .ucp_ev = PMC_EV_UCP_EVENT_##N, \
490 .ucp_evcode = (EV), \
492 .ucp_flags = (FLAGS) \
495 UCPDESCR(00H_01H, 0x00, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
496 UCPDESCR(00H_02H, 0x00, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
497 UCPDESCR(00H_04H, 0x00, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
499 UCPDESCR(01H_01H, 0x01, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
500 UCPDESCR(01H_02H, 0x01, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
501 UCPDESCR(01H_04H, 0x01, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
503 UCPDESCR(02H_01H, 0x02, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
504 UCPDESCR(03H_01H, 0x03, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
505 UCPDESCR(03H_02H, 0x03, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
506 UCPDESCR(03H_04H, 0x03, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
507 UCPDESCR(03H_08H, 0x03, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
508 UCPDESCR(03H_10H, 0x03, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
509 UCPDESCR(03H_20H, 0x03, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
510 UCPDESCR(03H_40H, 0x03, 0x40, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
512 UCPDESCR(04H_01H, 0x04, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
513 UCPDESCR(04H_02H, 0x04, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
514 UCPDESCR(04H_04H, 0x04, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
515 UCPDESCR(04H_08H, 0x04, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
516 UCPDESCR(04H_10H, 0x04, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
518 UCPDESCR(05H_01H, 0x05, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
519 UCPDESCR(05H_02H, 0x05, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
520 UCPDESCR(05H_04H, 0x05, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
522 UCPDESCR(06H_01H, 0x06, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
523 UCPDESCR(06H_02H, 0x06, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
524 UCPDESCR(06H_04H, 0x06, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
525 UCPDESCR(06H_08H, 0x06, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
526 UCPDESCR(06H_10H, 0x06, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
527 UCPDESCR(06H_20H, 0x06, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
529 UCPDESCR(07H_01H, 0x07, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
530 UCPDESCR(07H_02H, 0x07, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
531 UCPDESCR(07H_04H, 0x07, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
532 UCPDESCR(07H_08H, 0x07, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
533 UCPDESCR(07H_10H, 0x07, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
534 UCPDESCR(07H_20H, 0x07, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
535 UCPDESCR(07H_24H, 0x07, 0x24, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
537 UCPDESCR(08H_01H, 0x08, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
538 UCPDESCR(08H_02H, 0x08, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
539 UCPDESCR(08H_04H, 0x08, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
540 UCPDESCR(08H_03H, 0x08, 0x03, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
542 UCPDESCR(09H_01H, 0x09, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
543 UCPDESCR(09H_02H, 0x09, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
544 UCPDESCR(09H_04H, 0x09, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
545 UCPDESCR(09H_03H, 0x09, 0x03, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
547 UCPDESCR(0AH_01H, 0x0A, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
548 UCPDESCR(0AH_02H, 0x0A, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
549 UCPDESCR(0AH_04H, 0x0A, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
550 UCPDESCR(0AH_08H, 0x0A, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
551 UCPDESCR(0AH_0FH, 0x0A, 0x0F, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
553 UCPDESCR(0BH_01H, 0x0B, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
554 UCPDESCR(0BH_02H, 0x0B, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
555 UCPDESCR(0BH_04H, 0x0B, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
556 UCPDESCR(0BH_08H, 0x0B, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
557 UCPDESCR(0BH_10H, 0x0B, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
558 UCPDESCR(0BH_1FH, 0x0B, 0x1F, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
560 UCPDESCR(0CH_01H, 0x0C, 0x01, UCP_F_FM | UCP_F_WM),
561 UCPDESCR(0CH_02H, 0x0C, 0x02, UCP_F_FM | UCP_F_WM),
562 UCPDESCR(0CH_04H_E, 0x0C, 0x04, UCP_F_FM | UCP_F_WM),
563 UCPDESCR(0CH_04H_F, 0x0C, 0x04, UCP_F_FM | UCP_F_WM),
564 UCPDESCR(0CH_04H_M, 0x0C, 0x04, UCP_F_FM | UCP_F_WM),
565 UCPDESCR(0CH_04H_S, 0x0C, 0x04, UCP_F_FM | UCP_F_WM),
566 UCPDESCR(0CH_08H_E, 0x0C, 0x08, UCP_F_FM | UCP_F_WM),
567 UCPDESCR(0CH_08H_F, 0x0C, 0x08, UCP_F_FM | UCP_F_WM),
568 UCPDESCR(0CH_08H_M, 0x0C, 0x08, UCP_F_FM | UCP_F_WM),
569 UCPDESCR(0CH_08H_S, 0x0C, 0x08, UCP_F_FM | UCP_F_WM),
571 UCPDESCR(20H_01H, 0x20, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
572 UCPDESCR(20H_02H, 0x20, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
573 UCPDESCR(20H_04H, 0x20, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
574 UCPDESCR(20H_08H, 0x20, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
575 UCPDESCR(20H_10H, 0x20, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
576 UCPDESCR(20H_20H, 0x20, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
578 UCPDESCR(21H_01H, 0x21, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
579 UCPDESCR(21H_02H, 0x21, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
580 UCPDESCR(21H_04H, 0x21, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
582 UCPDESCR(22H_01H, 0x22, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM |
583 UCP_F_SB | UCP_F_HW),
584 UCPDESCR(22H_02H, 0x22, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM |
585 UCP_F_SB | UCP_F_HW),
586 UCPDESCR(22H_04H, 0x22, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM |
587 UCP_F_SB | UCP_F_HW),
588 UCPDESCR(22H_08H, 0x22, 0x08, UCP_F_FM | UCP_F_SB | UCP_F_HW),
589 UCPDESCR(22H_10H, 0x22, 0x10, UCP_F_FM | UCP_F_HW),
590 UCPDESCR(22H_20H, 0x22, 0x20, UCP_F_FM | UCP_F_SB | UCP_F_HW),
591 UCPDESCR(22H_40H, 0x22, 0x40, UCP_F_FM | UCP_F_SB | UCP_F_HW),
592 UCPDESCR(22H_80H, 0x22, 0x80, UCP_F_FM | UCP_F_SB | UCP_F_HW),
594 UCPDESCR(23H_01H, 0x23, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
595 UCPDESCR(23H_02H, 0x23, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
596 UCPDESCR(23H_04H, 0x23, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
598 UCPDESCR(24H_02H, 0x24, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
599 UCPDESCR(24H_04H, 0x24, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
601 UCPDESCR(25H_01H, 0x25, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
602 UCPDESCR(25H_02H, 0x25, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
603 UCPDESCR(25H_04H, 0x25, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
605 UCPDESCR(26H_01H, 0x26, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
607 UCPDESCR(27H_01H, 0x27, 0x01, UCP_F_FM | UCP_F_I7),
608 UCPDESCR(27H_02H, 0x27, 0x02, UCP_F_FM | UCP_F_I7),
609 UCPDESCR(27H_04H, 0x27, 0x04, UCP_F_FM | UCP_F_I7),
610 UCPDESCR(27H_08H, 0x27, 0x08, UCP_F_FM | UCP_F_I7),
611 UCPDESCR(27H_10H, 0x27, 0x10, UCP_F_FM | UCP_F_I7),
612 UCPDESCR(27H_20H, 0x27, 0x20, UCP_F_FM | UCP_F_I7),
614 UCPDESCR(28H_01H, 0x28, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
615 UCPDESCR(28H_02H, 0x28, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
616 UCPDESCR(28H_04H, 0x28, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
617 UCPDESCR(28H_08H, 0x28, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
618 UCPDESCR(28H_10H, 0x28, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
619 UCPDESCR(28H_20H, 0x28, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
621 UCPDESCR(29H_01H, 0x29, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
622 UCPDESCR(29H_02H, 0x29, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
623 UCPDESCR(29H_04H, 0x29, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
624 UCPDESCR(29H_08H, 0x29, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
625 UCPDESCR(29H_10H, 0x29, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
626 UCPDESCR(29H_20H, 0x29, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
628 UCPDESCR(2AH_01H, 0x2A, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
629 UCPDESCR(2AH_02H, 0x2A, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
630 UCPDESCR(2AH_04H, 0x2A, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
631 UCPDESCR(2AH_07H, 0x2A, 0x07, UCP_F_FM | UCP_F_WM),
633 UCPDESCR(2BH_01H, 0x2B, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
634 UCPDESCR(2BH_02H, 0x2B, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
635 UCPDESCR(2BH_04H, 0x2B, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
636 UCPDESCR(2BH_07H, 0x2B, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
638 UCPDESCR(2CH_01H, 0x2C, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
639 UCPDESCR(2CH_02H, 0x2C, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
640 UCPDESCR(2CH_04H, 0x2C, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
641 UCPDESCR(2CH_07H, 0x2C, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
643 UCPDESCR(2DH_01H, 0x2D, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
644 UCPDESCR(2DH_02H, 0x2D, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
645 UCPDESCR(2DH_04H, 0x2D, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
646 UCPDESCR(2DH_07H, 0x2D, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
648 UCPDESCR(2EH_01H, 0x2E, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
649 UCPDESCR(2EH_02H, 0x2E, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
650 UCPDESCR(2EH_04H, 0x2E, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
651 UCPDESCR(2EH_07H, 0x2E, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
653 UCPDESCR(2FH_01H, 0x2F, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
654 UCPDESCR(2FH_02H, 0x2F, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
655 UCPDESCR(2FH_04H, 0x2F, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
656 UCPDESCR(2FH_07H, 0x2F, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
657 UCPDESCR(2FH_08H, 0x2F, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
658 UCPDESCR(2FH_10H, 0x2F, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
659 UCPDESCR(2FH_20H, 0x2F, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
660 UCPDESCR(2FH_38H, 0x2F, 0x38, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
662 UCPDESCR(30H_01H, 0x30, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
663 UCPDESCR(30H_02H, 0x30, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
664 UCPDESCR(30H_04H, 0x30, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
665 UCPDESCR(30H_07H, 0x30, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
667 UCPDESCR(31H_01H, 0x31, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
668 UCPDESCR(31H_02H, 0x31, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
669 UCPDESCR(31H_04H, 0x31, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
670 UCPDESCR(31H_07H, 0x31, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
672 UCPDESCR(32H_01H, 0x32, 0x01, UCP_F_FM | UCP_F_WM),
673 UCPDESCR(32H_02H, 0x32, 0x02, UCP_F_FM | UCP_F_WM),
674 UCPDESCR(32H_04H, 0x32, 0x04, UCP_F_FM | UCP_F_WM),
675 UCPDESCR(32H_07H, 0x32, 0x07, UCP_F_FM | UCP_F_WM),
677 UCPDESCR(33H_01H, 0x33, 0x01, UCP_F_FM | UCP_F_WM),
678 UCPDESCR(33H_02H, 0x33, 0x02, UCP_F_FM | UCP_F_WM),
679 UCPDESCR(33H_04H, 0x33, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
680 UCPDESCR(33H_07H, 0x33, 0x07, UCP_F_FM | UCP_F_WM),
682 UCPDESCR(34H_01H, 0x34, 0x01, UCP_F_FM | UCP_F_WM | UCP_F_SB |
684 UCPDESCR(34H_02H, 0x34, 0x02, UCP_F_FM | UCP_F_WM | UCP_F_SB),
685 UCPDESCR(34H_04H, 0x34, 0x04, UCP_F_FM | UCP_F_WM | UCP_F_SB),
686 UCPDESCR(34H_06H, 0x34, 0x06, UCP_F_FM | UCP_F_HW),
687 UCPDESCR(34H_08H, 0x34, 0x08, UCP_F_FM | UCP_F_WM | UCP_F_SB |
689 UCPDESCR(34H_10H, 0x34, 0x10, UCP_F_FM | UCP_F_WM | UCP_F_SB |
691 UCPDESCR(34H_20H, 0x34, 0x20, UCP_F_FM | UCP_F_WM | UCP_F_SB |
693 UCPDESCR(34H_40H, 0x34, 0x40, UCP_F_FM | UCP_F_SB | UCP_F_HW),
694 UCPDESCR(34H_80H, 0x34, 0x80, UCP_F_FM | UCP_F_SB | UCP_F_HW),
696 UCPDESCR(35H_01H, 0x35, 0x01, UCP_F_FM | UCP_F_WM),
697 UCPDESCR(35H_02H, 0x35, 0x02, UCP_F_FM | UCP_F_WM),
698 UCPDESCR(35H_04H, 0x35, 0x04, UCP_F_FM | UCP_F_WM),
700 UCPDESCR(40H_01H, 0x40, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
701 UCPDESCR(40H_02H, 0x40, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
702 UCPDESCR(40H_04H, 0x40, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
703 UCPDESCR(40H_08H, 0x40, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
704 UCPDESCR(40H_10H, 0x40, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
705 UCPDESCR(40H_20H, 0x40, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
706 UCPDESCR(40H_07H, 0x40, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
707 UCPDESCR(40H_38H, 0x40, 0x38, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
709 UCPDESCR(41H_01H, 0x41, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
710 UCPDESCR(41H_02H, 0x41, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
711 UCPDESCR(41H_04H, 0x41, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
712 UCPDESCR(41H_08H, 0x41, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
713 UCPDESCR(41H_10H, 0x41, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
714 UCPDESCR(41H_20H, 0x41, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
715 UCPDESCR(41H_07H, 0x41, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
716 UCPDESCR(41H_38H, 0x41, 0x38, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
718 UCPDESCR(42H_01H, 0x42, 0x01, UCP_F_FM | UCP_F_WM),
719 UCPDESCR(42H_02H, 0x42, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
720 UCPDESCR(42H_04H, 0x42, 0x04, UCP_F_FM | UCP_F_WM),
721 UCPDESCR(42H_08H, 0x42, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
723 UCPDESCR(43H_01H, 0x43, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
724 UCPDESCR(43H_02H, 0x43, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
726 UCPDESCR(60H_01H, 0x60, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
727 UCPDESCR(60H_02H, 0x60, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
728 UCPDESCR(60H_04H, 0x60, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
730 UCPDESCR(61H_01H, 0x61, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
731 UCPDESCR(61H_02H, 0x61, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
732 UCPDESCR(61H_04H, 0x61, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
734 UCPDESCR(62H_01H, 0x62, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
735 UCPDESCR(62H_02H, 0x62, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
736 UCPDESCR(62H_04H, 0x62, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
738 UCPDESCR(63H_01H, 0x63, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
739 UCPDESCR(63H_02H, 0x63, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
740 UCPDESCR(63H_04H, 0x63, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
741 UCPDESCR(63H_08H, 0x63, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
742 UCPDESCR(63H_10H, 0x63, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
743 UCPDESCR(63H_20H, 0x63, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
745 UCPDESCR(64H_01H, 0x64, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
746 UCPDESCR(64H_02H, 0x64, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
747 UCPDESCR(64H_04H, 0x64, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
748 UCPDESCR(64H_08H, 0x64, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
749 UCPDESCR(64H_10H, 0x64, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
750 UCPDESCR(64H_20H, 0x64, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
752 UCPDESCR(65H_01H, 0x65, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
753 UCPDESCR(65H_02H, 0x65, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
754 UCPDESCR(65H_04H, 0x65, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
756 UCPDESCR(66H_01H, 0x66, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
757 UCPDESCR(66H_02H, 0x66, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
758 UCPDESCR(66H_04H, 0x66, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM),
760 UCPDESCR(67H_01H, 0x67, 0x01, UCP_F_FM | UCP_F_WM),
762 UCPDESCR(80H_01H, 0x80, 0x01, UCP_F_FM | UCP_F_WM | UCP_F_SB |
764 UCPDESCR(80H_02H, 0x80, 0x02, UCP_F_FM | UCP_F_WM),
765 UCPDESCR(80H_04H, 0x80, 0x04, UCP_F_FM | UCP_F_WM),
766 UCPDESCR(80H_08H, 0x80, 0x08, UCP_F_FM | UCP_F_WM),
768 UCPDESCR(81H_01H, 0x81, 0x01, UCP_F_FM | UCP_F_WM | UCP_F_SB |
770 UCPDESCR(81H_02H, 0x81, 0x02, UCP_F_FM | UCP_F_WM),
771 UCPDESCR(81H_04H, 0x81, 0x04, UCP_F_FM | UCP_F_WM),
772 UCPDESCR(81H_08H, 0x81, 0x08, UCP_F_FM | UCP_F_WM),
773 UCPDESCR(81H_20H, 0x81, 0x20, UCP_F_FM | UCP_F_SB | UCP_F_HW),
774 UCPDESCR(81H_80H, 0x81, 0x80, UCP_F_FM | UCP_F_SB | UCP_F_HW),
776 UCPDESCR(82H_01H, 0x82, 0x01, UCP_F_FM | UCP_F_WM),
778 UCPDESCR(83H_01H, 0x83, 0x01, UCP_F_FM | UCP_F_WM | UCP_F_SB |
780 UCPDESCR(83H_02H, 0x83, 0x02, UCP_F_FM | UCP_F_WM),
781 UCPDESCR(83H_04H, 0x83, 0x04, UCP_F_FM | UCP_F_WM),
782 UCPDESCR(83H_08H, 0x83, 0x08, UCP_F_FM | UCP_F_WM),
784 UCPDESCR(84H_01H, 0x84, 0x01, UCP_F_FM | UCP_F_WM | UCP_F_SB |
786 UCPDESCR(84H_02H, 0x84, 0x02, UCP_F_FM | UCP_F_WM),
787 UCPDESCR(84H_04H, 0x84, 0x04, UCP_F_FM | UCP_F_WM),
788 UCPDESCR(84H_08H, 0x84, 0x08, UCP_F_FM | UCP_F_WM),
789 UCPDESCR(85H_02H, 0x85, 0x02, UCP_F_FM | UCP_F_WM),
790 UCPDESCR(86H_01H, 0x86, 0x01, UCP_F_FM | UCP_F_WM)
793 static const int nucp_events = sizeof(ucp_events) / sizeof(ucp_events[0]);
796 ucp_perfctr_value_to_reload_count(pmc_value_t v)
798 v &= (1ULL << uncore_ucp_width) - 1;
799 return (1ULL << uncore_ucp_width) - v;
803 ucp_reload_count_to_perfctr_value(pmc_value_t rlc)
805 return (1ULL << uncore_ucp_width) - rlc;
809 * Counter specific event information for Sandybridge and Haswell
812 ucp_event_sb_hw_ok_on_counter(enum pmc_event pe, int ri)
818 * Events valid only on counter 0.
820 case PMC_EV_UCP_EVENT_80H_01H:
821 case PMC_EV_UCP_EVENT_83H_01H:
826 mask = ~0; /* Any row index is ok. */
829 return (mask & (1 << ri));
833 ucp_allocate_pmc(int cpu, int ri, struct pmc *pm,
834 const struct pmc_op_pmcallocate *a)
838 struct ucp_event_descr *ie;
839 uint32_t caps, config, cpuflag, evsel;
841 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
842 ("[uncore,%d] illegal CPU %d", __LINE__, cpu));
843 KASSERT(ri >= 0 && ri < uncore_ucp_npmc,
844 ("[uncore,%d] illegal row-index value %d", __LINE__, ri));
846 /* check requested capabilities */
848 if ((UCP_PMC_CAPS & caps) != caps)
853 switch (uncore_cputype) {
854 case PMC_CPU_INTEL_HASWELL:
855 case PMC_CPU_INTEL_SANDYBRIDGE:
856 if (ucp_event_sb_hw_ok_on_counter(ev, ri) == 0)
865 * Look for an event descriptor with matching CPU and event id
869 switch (uncore_cputype) {
870 case PMC_CPU_INTEL_COREI7:
873 case PMC_CPU_INTEL_HASWELL:
876 case PMC_CPU_INTEL_SANDYBRIDGE:
879 case PMC_CPU_INTEL_WESTMERE:
886 for (n = 0, ie = ucp_events; n < nucp_events; n++, ie++)
887 if (ie->ucp_ev == ev && ie->ucp_flags & cpuflag)
890 if (n == nucp_events)
894 * A matching event descriptor has been found, so start
895 * assembling the contents of the event select register.
897 evsel = ie->ucp_evcode | UCP_EN;
899 config = a->pm_md.pm_ucp.pm_ucp_config & ~UCP_F_CMASK;
902 * If the event uses a fixed umask value, reject any umask
903 * bits set by the user.
905 if (ie->ucp_flags & UCP_F_FM) {
907 if (UCP_UMASK(config) != 0)
910 evsel |= (ie->ucp_umask << 8);
915 if (caps & PMC_CAP_THRESHOLD)
916 evsel |= (a->pm_md.pm_ucp.pm_ucp_config & UCP_F_CMASK);
917 if (caps & PMC_CAP_EDGE)
919 if (caps & PMC_CAP_INVERT)
922 pm->pm_md.pm_ucp.pm_ucp_evsel = evsel;
928 ucp_config_pmc(int cpu, int ri, struct pmc *pm)
930 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
931 ("[uncore,%d] illegal CPU %d", __LINE__, cpu));
933 KASSERT(ri >= 0 && ri < uncore_ucp_npmc,
934 ("[uncore,%d] illegal row-index %d", __LINE__, ri));
936 PMCDBG3(MDP,CFG,1, "ucp-config cpu=%d ri=%d pm=%p", cpu, ri, pm);
938 KASSERT(uncore_pcpu[cpu] != NULL, ("[uncore,%d] null per-cpu %d", __LINE__,
941 uncore_pcpu[cpu]->pc_uncorepmcs[ri].phw_pmc = pm;
947 ucp_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
951 char ucp_name[PMC_NAME_MAX];
953 phw = &uncore_pcpu[cpu]->pc_uncorepmcs[ri];
955 (void) snprintf(ucp_name, sizeof(ucp_name), "UCP-%d", ri);
956 if ((error = copystr(ucp_name, pi->pm_name, PMC_NAME_MAX,
960 pi->pm_class = PMC_CLASS_UCP;
962 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
963 pi->pm_enabled = TRUE;
964 *ppmc = phw->phw_pmc;
966 pi->pm_enabled = FALSE;
974 ucp_get_config(int cpu, int ri, struct pmc **ppm)
976 *ppm = uncore_pcpu[cpu]->pc_uncorepmcs[ri].phw_pmc;
982 ucp_read_pmc(int cpu, int ri, pmc_value_t *v)
987 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
988 ("[uncore,%d] illegal cpu value %d", __LINE__, cpu));
989 KASSERT(ri >= 0 && ri < uncore_ucp_npmc,
990 ("[uncore,%d] illegal row-index %d", __LINE__, ri));
992 pm = uncore_pcpu[cpu]->pc_uncorepmcs[ri].phw_pmc;
995 ("[uncore,%d] cpu %d ri %d pmc not configured", __LINE__, cpu,
998 tmp = rdmsr(UCP_PMC0 + ri);
999 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
1000 *v = ucp_perfctr_value_to_reload_count(tmp);
1004 PMCDBG4(MDP,REA,1, "ucp-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri,
1011 ucp_release_pmc(int cpu, int ri, struct pmc *pm)
1015 PMCDBG3(MDP,REL,1, "ucp-release cpu=%d ri=%d pm=%p", cpu, ri,
1018 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
1019 ("[uncore,%d] illegal CPU value %d", __LINE__, cpu));
1020 KASSERT(ri >= 0 && ri < uncore_ucp_npmc,
1021 ("[uncore,%d] illegal row-index %d", __LINE__, ri));
1023 KASSERT(uncore_pcpu[cpu]->pc_uncorepmcs[ri].phw_pmc
1024 == NULL, ("[uncore,%d] PHW pmc non-NULL", __LINE__));
1030 ucp_start_pmc(int cpu, int ri)
1034 struct uncore_cpu *cc;
1036 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
1037 ("[uncore,%d] illegal CPU value %d", __LINE__, cpu));
1038 KASSERT(ri >= 0 && ri < uncore_ucp_npmc,
1039 ("[uncore,%d] illegal row-index %d", __LINE__, ri));
1041 cc = uncore_pcpu[cpu];
1042 pm = cc->pc_uncorepmcs[ri].phw_pmc;
1045 ("[uncore,%d] starting cpu%d,ri%d with no pmc configured",
1046 __LINE__, cpu, ri));
1048 PMCDBG2(MDP,STA,1, "ucp-start cpu=%d ri=%d", cpu, ri);
1050 evsel = pm->pm_md.pm_ucp.pm_ucp_evsel;
1053 "ucp-start/2 cpu=%d ri=%d evselmsr=0x%x evsel=0x%x",
1054 cpu, ri, SELECTSEL(uncore_cputype) + ri, evsel);
1056 /* Event specific configuration. */
1057 switch (pm->pm_event) {
1058 case PMC_EV_UCP_EVENT_0CH_04H_E:
1059 case PMC_EV_UCP_EVENT_0CH_08H_E:
1060 wrmsr(MSR_GQ_SNOOP_MESF,0x2);
1062 case PMC_EV_UCP_EVENT_0CH_04H_F:
1063 case PMC_EV_UCP_EVENT_0CH_08H_F:
1064 wrmsr(MSR_GQ_SNOOP_MESF,0x8);
1066 case PMC_EV_UCP_EVENT_0CH_04H_M:
1067 case PMC_EV_UCP_EVENT_0CH_08H_M:
1068 wrmsr(MSR_GQ_SNOOP_MESF,0x1);
1070 case PMC_EV_UCP_EVENT_0CH_04H_S:
1071 case PMC_EV_UCP_EVENT_0CH_08H_S:
1072 wrmsr(MSR_GQ_SNOOP_MESF,0x4);
1078 wrmsr(SELECTSEL(uncore_cputype) + ri, evsel);
1082 cc->pc_globalctrl |= (1ULL << ri);
1083 wrmsr(UC_GLOBAL_CTRL, cc->pc_globalctrl);
1084 } while (cc->pc_resync != 0);
1090 ucp_stop_pmc(int cpu, int ri)
1093 struct uncore_cpu *cc;
1095 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
1096 ("[uncore,%d] illegal cpu value %d", __LINE__, cpu));
1097 KASSERT(ri >= 0 && ri < uncore_ucp_npmc,
1098 ("[uncore,%d] illegal row index %d", __LINE__, ri));
1100 cc = uncore_pcpu[cpu];
1101 pm = cc->pc_uncorepmcs[ri].phw_pmc;
1104 ("[uncore,%d] cpu%d ri%d no configured PMC to stop", __LINE__,
1107 PMCDBG2(MDP,STO,1, "ucp-stop cpu=%d ri=%d", cpu, ri);
1110 wrmsr(SELECTSEL(uncore_cputype) + ri, 0);
1114 cc->pc_globalctrl &= ~(1ULL << ri);
1115 wrmsr(UC_GLOBAL_CTRL, cc->pc_globalctrl);
1116 } while (cc->pc_resync != 0);
1122 ucp_write_pmc(int cpu, int ri, pmc_value_t v)
1125 struct uncore_cpu *cc;
1127 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
1128 ("[uncore,%d] illegal cpu value %d", __LINE__, cpu));
1129 KASSERT(ri >= 0 && ri < uncore_ucp_npmc,
1130 ("[uncore,%d] illegal row index %d", __LINE__, ri));
1132 cc = uncore_pcpu[cpu];
1133 pm = cc->pc_uncorepmcs[ri].phw_pmc;
1136 ("[uncore,%d] cpu%d ri%d no configured PMC to stop", __LINE__,
1139 PMCDBG4(MDP,WRI,1, "ucp-write cpu=%d ri=%d msr=0x%x v=%jx", cpu, ri,
1142 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
1143 v = ucp_reload_count_to_perfctr_value(v);
1146 * Write the new value to the counter. The counter will be in
1147 * a stopped state when the pcd_write() entry point is called.
1150 wrmsr(UCP_PMC0 + ri, v);
1157 ucp_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth)
1159 struct pmc_classdep *pcd;
1161 KASSERT(md != NULL, ("[ucp,%d] md is NULL", __LINE__));
1163 PMCDBG0(MDP,INI,1, "ucp-initialize");
1165 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCP];
1167 pcd->pcd_caps = UCP_PMC_CAPS;
1168 pcd->pcd_class = PMC_CLASS_UCP;
1169 pcd->pcd_num = npmc;
1170 pcd->pcd_ri = md->pmd_npmc;
1171 pcd->pcd_width = pmcwidth;
1173 pcd->pcd_allocate_pmc = ucp_allocate_pmc;
1174 pcd->pcd_config_pmc = ucp_config_pmc;
1175 pcd->pcd_describe = ucp_describe;
1176 pcd->pcd_get_config = ucp_get_config;
1177 pcd->pcd_get_msr = NULL;
1178 pcd->pcd_pcpu_fini = uncore_pcpu_fini;
1179 pcd->pcd_pcpu_init = uncore_pcpu_init;
1180 pcd->pcd_read_pmc = ucp_read_pmc;
1181 pcd->pcd_release_pmc = ucp_release_pmc;
1182 pcd->pcd_start_pmc = ucp_start_pmc;
1183 pcd->pcd_stop_pmc = ucp_stop_pmc;
1184 pcd->pcd_write_pmc = ucp_write_pmc;
1186 md->pmd_npmc += npmc;
1190 pmc_uncore_initialize(struct pmc_mdep *md, int maxcpu)
1192 uncore_cputype = md->pmd_cputype;
1196 * Initialize programmable counters.
1199 uncore_ucp_npmc = 8;
1200 uncore_ucp_width = 48;
1202 uncore_pmcmask |= ((1ULL << uncore_ucp_npmc) - 1);
1204 ucp_initialize(md, maxcpu, uncore_ucp_npmc, uncore_ucp_width);
1207 * Initialize fixed function counters, if present.
1209 uncore_ucf_ri = uncore_ucp_npmc;
1210 uncore_ucf_npmc = 1;
1211 uncore_ucf_width = 48;
1213 ucf_initialize(md, maxcpu, uncore_ucf_npmc, uncore_ucf_width);
1214 uncore_pmcmask |= ((1ULL << uncore_ucf_npmc) - 1) << SELECTOFF(uncore_cputype);
1216 PMCDBG2(MDP,INI,1,"uncore-init pmcmask=0x%jx ucfri=%d", uncore_pmcmask,
1219 uncore_pcpu = malloc(sizeof(*uncore_pcpu) * maxcpu, M_PMC,
1226 pmc_uncore_finalize(struct pmc_mdep *md)
1228 PMCDBG0(MDP,INI,1, "uncore-finalize");
1230 free(uncore_pcpu, M_PMC);