2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2009 Rui Paulo <rpaulo@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
36 #include <sys/pmckern.h>
38 #include <machine/pmc_mdep.h>
40 * Support for the Intel XScale network processors
42 * XScale processors have up to now three generations.
44 * The first generation has two PMC; the event selection, interrupt config
45 * and overflow flag setup are done by writing to the PMNC register.
46 * It also has less monitoring events than the latter generations.
48 * The second and third generatiosn have four PMCs, one register for the event
49 * selection, one register for the interrupt config and one register for
52 static int xscale_npmcs;
53 static int xscale_gen; /* XScale Core generation */
55 struct xscale_event_code_map {
60 const struct xscale_event_code_map xscale_event_codes[] = {
61 /* 1st and 2nd Generation XScale cores */
62 { PMC_EV_XSCALE_IC_FETCH, 0x00 },
63 { PMC_EV_XSCALE_IC_MISS, 0x01 },
64 { PMC_EV_XSCALE_DATA_DEPENDENCY_STALLED,0x02 },
65 { PMC_EV_XSCALE_ITLB_MISS, 0x03 },
66 { PMC_EV_XSCALE_DTLB_MISS, 0x04 },
67 { PMC_EV_XSCALE_BRANCH_RETIRED, 0x05 },
68 { PMC_EV_XSCALE_BRANCH_MISPRED, 0x06 },
69 { PMC_EV_XSCALE_INSTR_RETIRED, 0x07 },
70 { PMC_EV_XSCALE_DC_FULL_CYCLE, 0x08 },
71 { PMC_EV_XSCALE_DC_FULL_CONTIG, 0x09 },
72 { PMC_EV_XSCALE_DC_ACCESS, 0x0a },
73 { PMC_EV_XSCALE_DC_MISS, 0x0b },
74 { PMC_EV_XSCALE_DC_WRITEBACK, 0x0c },
75 { PMC_EV_XSCALE_PC_CHANGE, 0x0d },
76 /* 3rd Generation XScale cores */
77 { PMC_EV_XSCALE_BRANCH_RETIRED_ALL, 0x0e },
78 { PMC_EV_XSCALE_INSTR_CYCLE, 0x0f },
79 { PMC_EV_XSCALE_CP_STALL, 0x17 },
80 { PMC_EV_XSCALE_PC_CHANGE_ALL, 0x18 },
81 { PMC_EV_XSCALE_PIPELINE_FLUSH, 0x19 },
82 { PMC_EV_XSCALE_BACKEND_STALL, 0x1a },
83 { PMC_EV_XSCALE_MULTIPLIER_USE, 0x1b },
84 { PMC_EV_XSCALE_MULTIPLIER_STALLED, 0x1c },
85 { PMC_EV_XSCALE_DATA_CACHE_STALLED, 0x1e },
86 { PMC_EV_XSCALE_L2_CACHE_REQ, 0x20 },
87 { PMC_EV_XSCALE_L2_CACHE_MISS, 0x23 },
88 { PMC_EV_XSCALE_ADDRESS_BUS_TRANS, 0x40 },
89 { PMC_EV_XSCALE_SELF_ADDRESS_BUS_TRANS, 0x41 },
90 { PMC_EV_XSCALE_DATA_BUS_TRANS, 0x48 },
94 * Per-processor information.
97 struct pmc_hw *pc_xscalepmcs;
100 static struct xscale_cpu **xscale_pcpu;
103 * Performance Monitor Control Register
105 static __inline uint32_t
106 xscale_pmnc_read(void)
110 __asm __volatile("mrc p14, 0, %0, c0, c1, 0" : "=r" (reg));
116 xscale_pmnc_write(uint32_t reg)
118 __asm __volatile("mcr p14, 0, %0, c0, c1, 0" : : "r" (reg));
122 * Clock Counter Register
124 static __inline uint32_t
125 xscale_ccnt_read(void)
129 __asm __volatile("mrc p14, 0, %0, c1, c1, 0" : "=r" (reg));
135 xscale_ccnt_write(uint32_t reg)
137 __asm __volatile("mcr p14, 0, %0, c1, c1, 0" : : "r" (reg));
141 * Interrupt Enable Register
143 static __inline uint32_t
144 xscale_inten_read(void)
148 __asm __volatile("mrc p14, 0, %0, c4, c1, 0" : "=r" (reg));
154 xscale_inten_write(uint32_t reg)
156 __asm __volatile("mcr p14, 0, %0, c4, c1, 0" : : "r" (reg));
160 * Overflow Flag Register
162 static __inline uint32_t
163 xscale_flag_read(void)
167 __asm __volatile("mrc p14, 0, %0, c5, c1, 0" : "=r" (reg));
173 xscale_flag_write(uint32_t reg)
175 __asm __volatile("mcr p14, 0, %0, c5, c1, 0" : : "r" (reg));
179 * Event Selection Register
181 static __inline uint32_t
182 xscale_evtsel_read(void)
186 __asm __volatile("mrc p14, 0, %0, c8, c1, 0" : "=r" (reg));
192 xscale_evtsel_write(uint32_t reg)
194 __asm __volatile("mcr p14, 0, %0, c8, c1, 0" : : "r" (reg));
198 * Performance Count Register N
201 xscale_pmcn_read(unsigned int pmc)
205 KASSERT(pmc < 4, ("[xscale,%d] illegal PMC number %d", __LINE__, pmc));
209 __asm __volatile("mrc p14, 0, %0, c0, c2, 0" : "=r" (reg));
212 __asm __volatile("mrc p14, 0, %0, c1, c2, 0" : "=r" (reg));
215 __asm __volatile("mrc p14, 0, %0, c2, c2, 0" : "=r" (reg));
218 __asm __volatile("mrc p14, 0, %0, c3, c2, 0" : "=r" (reg));
226 xscale_pmcn_write(unsigned int pmc, uint32_t reg)
229 KASSERT(pmc < 4, ("[xscale,%d] illegal PMC number %d", __LINE__, pmc));
233 __asm __volatile("mcr p14, 0, %0, c0, c2, 0" : : "r" (reg));
236 __asm __volatile("mcr p14, 0, %0, c1, c2, 0" : : "r" (reg));
239 __asm __volatile("mcr p14, 0, %0, c2, c2, 0" : : "r" (reg));
242 __asm __volatile("mcr p14, 0, %0, c3, c2, 0" : : "r" (reg));
250 xscale_allocate_pmc(int cpu, int ri, struct pmc *pm,
251 const struct pmc_op_pmcallocate *a)
254 uint32_t caps, config;
257 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
258 ("[xscale,%d] illegal CPU value %d", __LINE__, cpu));
259 KASSERT(ri >= 0 && ri < xscale_npmcs,
260 ("[xscale,%d] illegal row index %d", __LINE__, ri));
263 if (a->pm_class != PMC_CLASS_XSCALE)
266 for (i = 0; i < nitems(xscale_event_codes); i++) {
267 if (xscale_event_codes[i].pe_ev == pe) {
268 config = xscale_event_codes[i].pe_code;
272 if (i == nitems(xscale_event_codes))
274 /* Generation 1 has fewer events */
275 if (xscale_gen == 1 && i > PMC_EV_XSCALE_PC_CHANGE)
277 pm->pm_md.pm_xscale.pm_xscale_evsel = config;
279 PMCDBG2(MDP,ALL,2,"xscale-allocate ri=%d -> config=0x%x", ri, config);
286 xscale_read_pmc(int cpu, int ri, pmc_value_t *v)
291 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
292 ("[xscale,%d] illegal CPU value %d", __LINE__, cpu));
293 KASSERT(ri >= 0 && ri < xscale_npmcs,
294 ("[xscale,%d] illegal row index %d", __LINE__, ri));
296 pm = xscale_pcpu[cpu]->pc_xscalepmcs[ri].phw_pmc;
297 tmp = xscale_pmcn_read(ri);
298 PMCDBG2(MDP,REA,2,"xscale-read id=%d -> %jd", ri, tmp);
299 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
300 *v = XSCALE_PERFCTR_VALUE_TO_RELOAD_COUNT(tmp);
308 xscale_write_pmc(int cpu, int ri, pmc_value_t v)
312 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
313 ("[xscale,%d] illegal CPU value %d", __LINE__, cpu));
314 KASSERT(ri >= 0 && ri < xscale_npmcs,
315 ("[xscale,%d] illegal row-index %d", __LINE__, ri));
317 pm = xscale_pcpu[cpu]->pc_xscalepmcs[ri].phw_pmc;
319 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
320 v = XSCALE_RELOAD_COUNT_TO_PERFCTR_VALUE(v);
322 PMCDBG3(MDP,WRI,1,"xscale-write cpu=%d ri=%d v=%jx", cpu, ri, v);
324 xscale_pmcn_write(ri, v);
330 xscale_config_pmc(int cpu, int ri, struct pmc *pm)
334 PMCDBG3(MDP,CFG,1, "cpu=%d ri=%d pm=%p", cpu, ri, pm);
336 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
337 ("[xscale,%d] illegal CPU value %d", __LINE__, cpu));
338 KASSERT(ri >= 0 && ri < xscale_npmcs,
339 ("[xscale,%d] illegal row-index %d", __LINE__, ri));
341 phw = &xscale_pcpu[cpu]->pc_xscalepmcs[ri];
343 KASSERT(pm == NULL || phw->phw_pmc == NULL,
344 ("[xscale,%d] pm=%p phw->pm=%p hwpmc not unconfigured",
345 __LINE__, pm, phw->phw_pmc));
353 xscale_start_pmc(int cpu, int ri)
355 uint32_t pmnc, config, evtsel;
359 phw = &xscale_pcpu[cpu]->pc_xscalepmcs[ri];
361 config = pm->pm_md.pm_xscale.pm_xscale_evsel;
364 * Configure the event selection.
366 * On the XScale 2nd Generation there's no EVTSEL register.
368 if (xscale_npmcs == 2) {
369 pmnc = xscale_pmnc_read();
372 pmnc &= ~XSCALE_PMNC_EVT0_MASK;
373 pmnc |= (config << 12) & XSCALE_PMNC_EVT0_MASK;
376 pmnc &= ~XSCALE_PMNC_EVT1_MASK;
377 pmnc |= (config << 20) & XSCALE_PMNC_EVT1_MASK;
383 xscale_pmnc_write(pmnc);
385 evtsel = xscale_evtsel_read();
388 evtsel &= ~XSCALE_EVTSEL_EVT0_MASK;
389 evtsel |= config & XSCALE_EVTSEL_EVT0_MASK;
392 evtsel &= ~XSCALE_EVTSEL_EVT1_MASK;
393 evtsel |= (config << 8) & XSCALE_EVTSEL_EVT1_MASK;
396 evtsel &= ~XSCALE_EVTSEL_EVT2_MASK;
397 evtsel |= (config << 16) & XSCALE_EVTSEL_EVT2_MASK;
400 evtsel &= ~XSCALE_EVTSEL_EVT3_MASK;
401 evtsel |= (config << 24) & XSCALE_EVTSEL_EVT3_MASK;
407 xscale_evtsel_write(evtsel);
412 * Note that XScale provides only one bit to enable/disable _all_
413 * performance monitoring units.
415 pmnc = xscale_pmnc_read();
416 pmnc |= XSCALE_PMNC_ENABLE;
417 xscale_pmnc_write(pmnc);
423 xscale_stop_pmc(int cpu, int ri)
425 uint32_t pmnc, evtsel;
429 phw = &xscale_pcpu[cpu]->pc_xscalepmcs[ri];
435 * Note that XScale provides only one bit to enable/disable _all_
436 * performance monitoring units.
438 pmnc = xscale_pmnc_read();
439 pmnc &= ~XSCALE_PMNC_ENABLE;
440 xscale_pmnc_write(pmnc);
442 * A value of 0xff makes the corresponding PMU go into
445 if (xscale_npmcs == 2) {
446 pmnc = xscale_pmnc_read();
449 pmnc |= XSCALE_PMNC_EVT0_MASK;
452 pmnc |= XSCALE_PMNC_EVT1_MASK;
458 xscale_pmnc_write(pmnc);
460 evtsel = xscale_evtsel_read();
463 evtsel |= XSCALE_EVTSEL_EVT0_MASK;
466 evtsel |= XSCALE_EVTSEL_EVT1_MASK;
469 evtsel |= XSCALE_EVTSEL_EVT2_MASK;
472 evtsel |= XSCALE_EVTSEL_EVT3_MASK;
478 xscale_evtsel_write(evtsel);
485 xscale_release_pmc(int cpu, int ri, struct pmc *pmc)
489 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
490 ("[xscale,%d] illegal CPU value %d", __LINE__, cpu));
491 KASSERT(ri >= 0 && ri < xscale_npmcs,
492 ("[xscale,%d] illegal row-index %d", __LINE__, ri));
494 phw = &xscale_pcpu[cpu]->pc_xscalepmcs[ri];
495 KASSERT(phw->phw_pmc == NULL,
496 ("[xscale,%d] PHW pmc %p non-NULL", __LINE__, phw->phw_pmc));
502 xscale_intr(int cpu, struct trapframe *tf)
509 xscale_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
513 char xscale_name[PMC_NAME_MAX];
515 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
516 ("[xscale,%d], illegal CPU %d", __LINE__, cpu));
517 KASSERT(ri >= 0 && ri < xscale_npmcs,
518 ("[xscale,%d] row-index %d out of range", __LINE__, ri));
520 phw = &xscale_pcpu[cpu]->pc_xscalepmcs[ri];
521 snprintf(xscale_name, sizeof(xscale_name), "XSCALE-%d", ri);
522 if ((error = copystr(xscale_name, pi->pm_name, PMC_NAME_MAX,
525 pi->pm_class = PMC_CLASS_XSCALE;
526 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
527 pi->pm_enabled = TRUE;
528 *ppmc = phw->phw_pmc;
530 pi->pm_enabled = FALSE;
538 xscale_get_config(int cpu, int ri, struct pmc **ppm)
540 *ppm = xscale_pcpu[cpu]->pc_xscalepmcs[ri].phw_pmc;
546 * XXX don't know what we should do here.
549 xscale_switch_in(struct pmc_cpu *pc, struct pmc_process *pp)
555 xscale_switch_out(struct pmc_cpu *pc, struct pmc_process *pp)
561 xscale_pcpu_init(struct pmc_mdep *md, int cpu)
565 struct xscale_cpu *pac;
568 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
569 ("[xscale,%d] wrong cpu number %d", __LINE__, cpu));
570 PMCDBG1(MDP,INI,1,"xscale-init cpu=%d", cpu);
572 xscale_pcpu[cpu] = pac = malloc(sizeof(struct xscale_cpu), M_PMC,
574 pac->pc_xscalepmcs = malloc(sizeof(struct pmc_hw) * xscale_npmcs,
575 M_PMC, M_WAITOK|M_ZERO);
577 first_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_XSCALE].pcd_ri;
578 KASSERT(pc != NULL, ("[xscale,%d] NULL per-cpu pointer", __LINE__));
580 for (i = 0, phw = pac->pc_xscalepmcs; i < xscale_npmcs; i++, phw++) {
581 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED |
582 PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(i);
584 pc->pc_hwpmcs[i + first_ri] = phw;
588 * Disable and put the PMUs into power save mode.
590 if (xscale_npmcs == 2) {
591 xscale_pmnc_write(XSCALE_PMNC_EVT1_MASK |
592 XSCALE_PMNC_EVT0_MASK);
594 xscale_evtsel_write(XSCALE_EVTSEL_EVT3_MASK |
595 XSCALE_EVTSEL_EVT2_MASK | XSCALE_EVTSEL_EVT1_MASK |
596 XSCALE_EVTSEL_EVT0_MASK);
603 xscale_pcpu_fini(struct pmc_mdep *md, int cpu)
609 pmc_xscale_initialize()
611 struct pmc_mdep *pmc_mdep;
612 struct pmc_classdep *pcd;
615 /* Get the Core Generation from CP15 */
616 __asm __volatile("mrc p15, 0, %0, c0, c0, 0" : "=r" (idreg));
617 xscale_gen = (idreg >> 13) & 0x3;
618 switch (xscale_gen) {
627 printf("%s: unknown XScale core generation\n", __func__);
630 PMCDBG1(MDP,INI,1,"xscale-init npmcs=%d", xscale_npmcs);
633 * Allocate space for pointers to PMC HW descriptors and for
634 * the MDEP structure used by MI code.
636 xscale_pcpu = malloc(sizeof(struct xscale_cpu *) * pmc_cpu_max(), M_PMC,
640 pmc_mdep = pmc_mdep_alloc(1);
642 pmc_mdep->pmd_cputype = PMC_CPU_INTEL_XSCALE;
644 pcd = &pmc_mdep->pmd_classdep[PMC_MDEP_CLASS_INDEX_XSCALE];
645 pcd->pcd_caps = XSCALE_PMC_CAPS;
646 pcd->pcd_class = PMC_CLASS_XSCALE;
647 pcd->pcd_num = xscale_npmcs;
648 pcd->pcd_ri = pmc_mdep->pmd_npmc;
651 pcd->pcd_allocate_pmc = xscale_allocate_pmc;
652 pcd->pcd_config_pmc = xscale_config_pmc;
653 pcd->pcd_pcpu_fini = xscale_pcpu_fini;
654 pcd->pcd_pcpu_init = xscale_pcpu_init;
655 pcd->pcd_describe = xscale_describe;
656 pcd->pcd_get_config = xscale_get_config;
657 pcd->pcd_read_pmc = xscale_read_pmc;
658 pcd->pcd_release_pmc = xscale_release_pmc;
659 pcd->pcd_start_pmc = xscale_start_pmc;
660 pcd->pcd_stop_pmc = xscale_stop_pmc;
661 pcd->pcd_write_pmc = xscale_write_pmc;
663 pmc_mdep->pmd_intr = xscale_intr;
664 pmc_mdep->pmd_switch_in = xscale_switch_in;
665 pmc_mdep->pmd_switch_out = xscale_switch_out;
667 pmc_mdep->pmd_npmc += xscale_npmcs;
673 pmc_xscale_finalize(struct pmc_mdep *md)