2 * Copyright (c) 2009 Rui Paulo <rpaulo@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
32 #include <sys/systm.h>
34 #include <sys/pmckern.h>
36 #include <machine/pmc_mdep.h>
38 * Support for the Intel XScale network processors
40 * XScale processors have up to now three generations.
42 * The first generation has two PMC; the event selection, interrupt config
43 * and overflow flag setup are done by writing to the PMNC register.
44 * It also has less monitoring events than the latter generations.
46 * The second and third generatiosn have four PMCs, one register for the event
47 * selection, one register for the interrupt config and one register for
50 static int xscale_npmcs;
51 static int xscale_gen; /* XScale Core generation */
53 struct xscale_event_code_map {
58 const struct xscale_event_code_map xscale_event_codes[] = {
59 /* 1st and 2nd Generation XScale cores */
60 { PMC_EV_XSCALE_IC_FETCH, 0x00 },
61 { PMC_EV_XSCALE_IC_MISS, 0x01 },
62 { PMC_EV_XSCALE_DATA_DEPENDENCY_STALLED,0x02 },
63 { PMC_EV_XSCALE_ITLB_MISS, 0x03 },
64 { PMC_EV_XSCALE_DTLB_MISS, 0x04 },
65 { PMC_EV_XSCALE_BRANCH_RETIRED, 0x05 },
66 { PMC_EV_XSCALE_BRANCH_MISPRED, 0x06 },
67 { PMC_EV_XSCALE_INSTR_RETIRED, 0x07 },
68 { PMC_EV_XSCALE_DC_FULL_CYCLE, 0x08 },
69 { PMC_EV_XSCALE_DC_FULL_CONTIG, 0x09 },
70 { PMC_EV_XSCALE_DC_ACCESS, 0x0a },
71 { PMC_EV_XSCALE_DC_MISS, 0x0b },
72 { PMC_EV_XSCALE_DC_WRITEBACK, 0x0c },
73 { PMC_EV_XSCALE_PC_CHANGE, 0x0d },
74 /* 3rd Generation XScale cores */
75 { PMC_EV_XSCALE_BRANCH_RETIRED_ALL, 0x0e },
76 { PMC_EV_XSCALE_INSTR_CYCLE, 0x0f },
77 { PMC_EV_XSCALE_CP_STALL, 0x17 },
78 { PMC_EV_XSCALE_PC_CHANGE_ALL, 0x18 },
79 { PMC_EV_XSCALE_PIPELINE_FLUSH, 0x19 },
80 { PMC_EV_XSCALE_BACKEND_STALL, 0x1a },
81 { PMC_EV_XSCALE_MULTIPLIER_USE, 0x1b },
82 { PMC_EV_XSCALE_MULTIPLIER_STALLED, 0x1c },
83 { PMC_EV_XSCALE_DATA_CACHE_STALLED, 0x1e },
84 { PMC_EV_XSCALE_L2_CACHE_REQ, 0x20 },
85 { PMC_EV_XSCALE_L2_CACHE_MISS, 0x23 },
86 { PMC_EV_XSCALE_ADDRESS_BUS_TRANS, 0x40 },
87 { PMC_EV_XSCALE_SELF_ADDRESS_BUS_TRANS, 0x41 },
88 { PMC_EV_XSCALE_DATA_BUS_TRANS, 0x48 },
92 * Per-processor information.
95 struct pmc_hw *pc_xscalepmcs;
98 static struct xscale_cpu **xscale_pcpu;
101 * Performance Monitor Control Register
103 static __inline uint32_t
104 xscale_pmnc_read(void)
108 __asm __volatile("mrc p14, 0, %0, c0, c1, 0" : "=r" (reg));
114 xscale_pmnc_write(uint32_t reg)
116 __asm __volatile("mcr p14, 0, %0, c0, c1, 0" : : "r" (reg));
120 * Clock Counter Register
122 static __inline uint32_t
123 xscale_ccnt_read(void)
127 __asm __volatile("mrc p14, 0, %0, c1, c1, 0" : "=r" (reg));
133 xscale_ccnt_write(uint32_t reg)
135 __asm __volatile("mcr p14, 0, %0, c1, c1, 0" : : "r" (reg));
139 * Interrupt Enable Register
141 static __inline uint32_t
142 xscale_inten_read(void)
146 __asm __volatile("mrc p14, 0, %0, c4, c1, 0" : "=r" (reg));
152 xscale_inten_write(uint32_t reg)
154 __asm __volatile("mcr p14, 0, %0, c4, c1, 0" : : "r" (reg));
158 * Overflow Flag Register
160 static __inline uint32_t
161 xscale_flag_read(void)
165 __asm __volatile("mrc p14, 0, %0, c5, c1, 0" : "=r" (reg));
171 xscale_flag_write(uint32_t reg)
173 __asm __volatile("mcr p14, 0, %0, c5, c1, 0" : : "r" (reg));
177 * Event Selection Register
179 static __inline uint32_t
180 xscale_evtsel_read(void)
184 __asm __volatile("mrc p14, 0, %0, c8, c1, 0" : "=r" (reg));
190 xscale_evtsel_write(uint32_t reg)
192 __asm __volatile("mcr p14, 0, %0, c8, c1, 0" : : "r" (reg));
196 * Performance Count Register N
199 xscale_pmcn_read(unsigned int pmc)
203 KASSERT(pmc < 4, ("[xscale,%d] illegal PMC number %d", __LINE__, pmc));
207 __asm __volatile("mrc p14, 0, %0, c0, c2, 0" : "=r" (reg));
210 __asm __volatile("mrc p14, 0, %0, c1, c2, 0" : "=r" (reg));
213 __asm __volatile("mrc p14, 0, %0, c2, c2, 0" : "=r" (reg));
216 __asm __volatile("mrc p14, 0, %0, c3, c2, 0" : "=r" (reg));
224 xscale_pmcn_write(unsigned int pmc, uint32_t reg)
227 KASSERT(pmc < 4, ("[xscale,%d] illegal PMC number %d", __LINE__, pmc));
231 __asm __volatile("mcr p14, 0, %0, c0, c2, 0" : : "r" (reg));
234 __asm __volatile("mcr p14, 0, %0, c1, c2, 0" : : "r" (reg));
237 __asm __volatile("mcr p14, 0, %0, c2, c2, 0" : : "r" (reg));
240 __asm __volatile("mcr p14, 0, %0, c3, c2, 0" : : "r" (reg));
248 xscale_allocate_pmc(int cpu, int ri, struct pmc *pm,
249 const struct pmc_op_pmcallocate *a)
252 uint32_t caps, config;
255 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
256 ("[xscale,%d] illegal CPU value %d", __LINE__, cpu));
257 KASSERT(ri >= 0 && ri < xscale_npmcs,
258 ("[xscale,%d] illegal row index %d", __LINE__, ri));
261 if (a->pm_class != PMC_CLASS_XSCALE)
264 for (i = 0; i < nitems(xscale_event_codes); i++) {
265 if (xscale_event_codes[i].pe_ev == pe) {
266 config = xscale_event_codes[i].pe_code;
270 if (i == nitems(xscale_event_codes))
272 /* Generation 1 has fewer events */
273 if (xscale_gen == 1 && i > PMC_EV_XSCALE_PC_CHANGE)
275 pm->pm_md.pm_xscale.pm_xscale_evsel = config;
277 PMCDBG2(MDP,ALL,2,"xscale-allocate ri=%d -> config=0x%x", ri, config);
284 xscale_read_pmc(int cpu, int ri, pmc_value_t *v)
289 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
290 ("[xscale,%d] illegal CPU value %d", __LINE__, cpu));
291 KASSERT(ri >= 0 && ri < xscale_npmcs,
292 ("[xscale,%d] illegal row index %d", __LINE__, ri));
294 pm = xscale_pcpu[cpu]->pc_xscalepmcs[ri].phw_pmc;
295 tmp = xscale_pmcn_read(ri);
296 PMCDBG2(MDP,REA,2,"xscale-read id=%d -> %jd", ri, tmp);
297 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
298 *v = XSCALE_PERFCTR_VALUE_TO_RELOAD_COUNT(tmp);
306 xscale_write_pmc(int cpu, int ri, pmc_value_t v)
310 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
311 ("[xscale,%d] illegal CPU value %d", __LINE__, cpu));
312 KASSERT(ri >= 0 && ri < xscale_npmcs,
313 ("[xscale,%d] illegal row-index %d", __LINE__, ri));
315 pm = xscale_pcpu[cpu]->pc_xscalepmcs[ri].phw_pmc;
317 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
318 v = XSCALE_RELOAD_COUNT_TO_PERFCTR_VALUE(v);
320 PMCDBG3(MDP,WRI,1,"xscale-write cpu=%d ri=%d v=%jx", cpu, ri, v);
322 xscale_pmcn_write(ri, v);
328 xscale_config_pmc(int cpu, int ri, struct pmc *pm)
332 PMCDBG3(MDP,CFG,1, "cpu=%d ri=%d pm=%p", cpu, ri, pm);
334 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
335 ("[xscale,%d] illegal CPU value %d", __LINE__, cpu));
336 KASSERT(ri >= 0 && ri < xscale_npmcs,
337 ("[xscale,%d] illegal row-index %d", __LINE__, ri));
339 phw = &xscale_pcpu[cpu]->pc_xscalepmcs[ri];
341 KASSERT(pm == NULL || phw->phw_pmc == NULL,
342 ("[xscale,%d] pm=%p phw->pm=%p hwpmc not unconfigured",
343 __LINE__, pm, phw->phw_pmc));
351 xscale_start_pmc(int cpu, int ri)
353 uint32_t pmnc, config, evtsel;
357 phw = &xscale_pcpu[cpu]->pc_xscalepmcs[ri];
359 config = pm->pm_md.pm_xscale.pm_xscale_evsel;
362 * Configure the event selection.
364 * On the XScale 2nd Generation there's no EVTSEL register.
366 if (xscale_npmcs == 2) {
367 pmnc = xscale_pmnc_read();
370 pmnc &= ~XSCALE_PMNC_EVT0_MASK;
371 pmnc |= (config << 12) & XSCALE_PMNC_EVT0_MASK;
374 pmnc &= ~XSCALE_PMNC_EVT1_MASK;
375 pmnc |= (config << 20) & XSCALE_PMNC_EVT1_MASK;
381 xscale_pmnc_write(pmnc);
383 evtsel = xscale_evtsel_read();
386 evtsel &= ~XSCALE_EVTSEL_EVT0_MASK;
387 evtsel |= config & XSCALE_EVTSEL_EVT0_MASK;
390 evtsel &= ~XSCALE_EVTSEL_EVT1_MASK;
391 evtsel |= (config << 8) & XSCALE_EVTSEL_EVT1_MASK;
394 evtsel &= ~XSCALE_EVTSEL_EVT2_MASK;
395 evtsel |= (config << 16) & XSCALE_EVTSEL_EVT2_MASK;
398 evtsel &= ~XSCALE_EVTSEL_EVT3_MASK;
399 evtsel |= (config << 24) & XSCALE_EVTSEL_EVT3_MASK;
405 xscale_evtsel_write(evtsel);
410 * Note that XScale provides only one bit to enable/disable _all_
411 * performance monitoring units.
413 pmnc = xscale_pmnc_read();
414 pmnc |= XSCALE_PMNC_ENABLE;
415 xscale_pmnc_write(pmnc);
421 xscale_stop_pmc(int cpu, int ri)
423 uint32_t pmnc, evtsel;
427 phw = &xscale_pcpu[cpu]->pc_xscalepmcs[ri];
433 * Note that XScale provides only one bit to enable/disable _all_
434 * performance monitoring units.
436 pmnc = xscale_pmnc_read();
437 pmnc &= ~XSCALE_PMNC_ENABLE;
438 xscale_pmnc_write(pmnc);
440 * A value of 0xff makes the corresponding PMU go into
443 if (xscale_npmcs == 2) {
444 pmnc = xscale_pmnc_read();
447 pmnc |= XSCALE_PMNC_EVT0_MASK;
450 pmnc |= XSCALE_PMNC_EVT1_MASK;
456 xscale_pmnc_write(pmnc);
458 evtsel = xscale_evtsel_read();
461 evtsel |= XSCALE_EVTSEL_EVT0_MASK;
464 evtsel |= XSCALE_EVTSEL_EVT1_MASK;
467 evtsel |= XSCALE_EVTSEL_EVT2_MASK;
470 evtsel |= XSCALE_EVTSEL_EVT3_MASK;
476 xscale_evtsel_write(evtsel);
483 xscale_release_pmc(int cpu, int ri, struct pmc *pmc)
487 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
488 ("[xscale,%d] illegal CPU value %d", __LINE__, cpu));
489 KASSERT(ri >= 0 && ri < xscale_npmcs,
490 ("[xscale,%d] illegal row-index %d", __LINE__, ri));
492 phw = &xscale_pcpu[cpu]->pc_xscalepmcs[ri];
493 KASSERT(phw->phw_pmc == NULL,
494 ("[xscale,%d] PHW pmc %p non-NULL", __LINE__, phw->phw_pmc));
500 xscale_intr(int cpu, struct trapframe *tf)
507 xscale_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
511 char xscale_name[PMC_NAME_MAX];
513 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
514 ("[xscale,%d], illegal CPU %d", __LINE__, cpu));
515 KASSERT(ri >= 0 && ri < xscale_npmcs,
516 ("[xscale,%d] row-index %d out of range", __LINE__, ri));
518 phw = &xscale_pcpu[cpu]->pc_xscalepmcs[ri];
519 snprintf(xscale_name, sizeof(xscale_name), "XSCALE-%d", ri);
520 if ((error = copystr(xscale_name, pi->pm_name, PMC_NAME_MAX,
523 pi->pm_class = PMC_CLASS_XSCALE;
524 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
525 pi->pm_enabled = TRUE;
526 *ppmc = phw->phw_pmc;
528 pi->pm_enabled = FALSE;
536 xscale_get_config(int cpu, int ri, struct pmc **ppm)
538 *ppm = xscale_pcpu[cpu]->pc_xscalepmcs[ri].phw_pmc;
544 * XXX don't know what we should do here.
547 xscale_switch_in(struct pmc_cpu *pc, struct pmc_process *pp)
553 xscale_switch_out(struct pmc_cpu *pc, struct pmc_process *pp)
559 xscale_pcpu_init(struct pmc_mdep *md, int cpu)
563 struct xscale_cpu *pac;
566 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
567 ("[xscale,%d] wrong cpu number %d", __LINE__, cpu));
568 PMCDBG1(MDP,INI,1,"xscale-init cpu=%d", cpu);
570 xscale_pcpu[cpu] = pac = malloc(sizeof(struct xscale_cpu), M_PMC,
572 pac->pc_xscalepmcs = malloc(sizeof(struct pmc_hw) * xscale_npmcs,
573 M_PMC, M_WAITOK|M_ZERO);
575 first_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_XSCALE].pcd_ri;
576 KASSERT(pc != NULL, ("[xscale,%d] NULL per-cpu pointer", __LINE__));
578 for (i = 0, phw = pac->pc_xscalepmcs; i < xscale_npmcs; i++, phw++) {
579 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED |
580 PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(i);
582 pc->pc_hwpmcs[i + first_ri] = phw;
586 * Disable and put the PMUs into power save mode.
588 if (xscale_npmcs == 2) {
589 xscale_pmnc_write(XSCALE_PMNC_EVT1_MASK |
590 XSCALE_PMNC_EVT0_MASK);
592 xscale_evtsel_write(XSCALE_EVTSEL_EVT3_MASK |
593 XSCALE_EVTSEL_EVT2_MASK | XSCALE_EVTSEL_EVT1_MASK |
594 XSCALE_EVTSEL_EVT0_MASK);
601 xscale_pcpu_fini(struct pmc_mdep *md, int cpu)
607 pmc_xscale_initialize()
609 struct pmc_mdep *pmc_mdep;
610 struct pmc_classdep *pcd;
613 /* Get the Core Generation from CP15 */
614 __asm __volatile("mrc p15, 0, %0, c0, c0, 0" : "=r" (idreg));
615 xscale_gen = (idreg >> 13) & 0x3;
616 switch (xscale_gen) {
625 printf("%s: unknown XScale core generation\n", __func__);
628 PMCDBG1(MDP,INI,1,"xscale-init npmcs=%d", xscale_npmcs);
631 * Allocate space for pointers to PMC HW descriptors and for
632 * the MDEP structure used by MI code.
634 xscale_pcpu = malloc(sizeof(struct xscale_cpu *) * pmc_cpu_max(), M_PMC,
638 pmc_mdep = pmc_mdep_alloc(1);
640 pmc_mdep->pmd_cputype = PMC_CPU_INTEL_XSCALE;
642 pcd = &pmc_mdep->pmd_classdep[PMC_MDEP_CLASS_INDEX_XSCALE];
643 pcd->pcd_caps = XSCALE_PMC_CAPS;
644 pcd->pcd_class = PMC_CLASS_XSCALE;
645 pcd->pcd_num = xscale_npmcs;
646 pcd->pcd_ri = pmc_mdep->pmd_npmc;
649 pcd->pcd_allocate_pmc = xscale_allocate_pmc;
650 pcd->pcd_config_pmc = xscale_config_pmc;
651 pcd->pcd_pcpu_fini = xscale_pcpu_fini;
652 pcd->pcd_pcpu_init = xscale_pcpu_init;
653 pcd->pcd_describe = xscale_describe;
654 pcd->pcd_get_config = xscale_get_config;
655 pcd->pcd_read_pmc = xscale_read_pmc;
656 pcd->pcd_release_pmc = xscale_release_pmc;
657 pcd->pcd_start_pmc = xscale_start_pmc;
658 pcd->pcd_stop_pmc = xscale_stop_pmc;
659 pcd->pcd_write_pmc = xscale_write_pmc;
661 pmc_mdep->pmd_intr = xscale_intr;
662 pmc_mdep->pmd_switch_in = xscale_switch_in;
663 pmc_mdep->pmd_switch_out = xscale_switch_out;
665 pmc_mdep->pmd_npmc += xscale_npmcs;
671 pmc_xscale_finalize(struct pmc_mdep *md)