2 * Copyright (c) 2009 Rui Paulo <rpaulo@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #ifndef _DEV_HWPMC_XSCALE_H_
30 #define _DEV_HWPMC_XSCALE_H_
32 #define XSCALE_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | \
33 PMC_CAP_SYSTEM | PMC_CAP_EDGE | \
34 PMC_CAP_THRESHOLD | PMC_CAP_READ | \
35 PMC_CAP_WRITE | PMC_CAP_INVERT | \
39 #define XSCALE_PMNC_ENABLE 0x01 /* Enable all Counters */
40 #define XSCALE_PMNC_PMNRESET 0x02 /* Performance Counter Reset */
41 #define XSCALE_PMNC_CCNTRESET 0x04 /* Clock Counter Reset */
42 #define XSCALE_PMNC_CCNTDIV 0x08 /* Clock Counter Divider */
43 /* IXP425 only -- first generation */
44 #define XSCALE_PMNC_EVT0_MASK 0x00ff000
45 #define XSCALE_PMNC_EVT1_MASK 0xff00000
47 #define XSCALE_INTEN_CCNT 0x01 /* Enable Clock Counter Int. */
48 #define XSCALE_INTEN_PMN0 0x02 /* Enable PMN0 Interrupts */
49 #define XSCALE_INTEN_PMN1 0x04 /* Enable PMN1 Interrupts */
50 #define XSCALE_INTEN_PMN2 0x08 /* Enable PMN2 Interrupts */
51 #define XSCALE_INTEN_PMN3 0x10 /* Enable PMN3 Interrupts */
53 #define XSCALE_EVTSEL_EVT0_MASK 0x000000ff
54 #define XSCALE_EVTSEL_EVT1_MASK 0x0000ff00
55 #define XSCALE_EVTSEL_EVT2_MASK 0x00ff0000
56 #define XSCALE_EVTSEL_EVT3_MASK 0xff000000
58 #define XSCALE_FLAG_CCNT_OVERFLOW 0x01
59 #define XSCALE_FLAG_PMN0_OVERFLOW 0x02
60 #define XSCALE_FLAG_PMN1_OVERFLOW 0x04
61 #define XSCALE_FLAG_PMN2_OVERFLOW 0x08
62 #define XSCALE_FLAG_PMN3_OVERFLOW 0x10
64 #define XSCALE_RELOAD_COUNT_TO_PERFCTR_VALUE(R) (-(R))
65 #define XSCALE_PERFCTR_VALUE_TO_RELOAD_COUNT(P) (-(P))
68 /* MD extension for 'struct pmc' */
69 struct pmc_md_xscale_pmc {
70 uint32_t pm_xscale_evsel;
73 #endif /* _DEV_HWPMC_XSCALE_H_ */