2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (c) 1991 The Regents of the University of California.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of the University nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * NS8250... UART registers.
36 /* 8250 registers #[0-6]. */
38 #define com_data 0 /* data register (R/W) */
39 #define REG_DATA com_data
41 #define com_ier 1 /* interrupt enable register (W) */
42 #define REG_IER com_ier
43 #define IER_ERXRDY 0x1
44 #define IER_ETXRDY 0x2
48 * Receive timeout interrupt enable.
49 * Implemented in Intel XScale, Ingenic XBurst.
51 #define IER_RXTMOUT 0x10
53 #define IER_BITS "\20\1ERXRDY\2ETXRDY\3ERLS\4EMSC\5RXTMOUT"
55 #define com_iir 2 /* interrupt identification register (R) */
56 #define REG_IIR com_iir
58 #define IIR_RXTOUT 0xc
63 #define IIR_NOPEND 0x1
65 #define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */
67 #define IIR_BITS "\20\1NOPEND\2TXRDY\3RXRDY"
69 #define com_lcr 3 /* line control register (R/W) */
70 #define com_cfcr com_lcr /* character format control register (R/W) */
71 #define REG_LCR com_lcr
73 #define CFCR_DLAB LCR_DLAB
74 #define LCR_EFR_ENABLE 0xbf /* magic to enable EFR on 16650 up */
75 #define CFCR_EFR_ENABLE LCR_EFR_ENABLE
76 #define LCR_SBREAK 0x40
77 #define CFCR_SBREAK LCR_SBREAK
78 #define LCR_PZERO 0x30
79 #define CFCR_PZERO LCR_PZERO
81 #define CFCR_PONE LCR_PONE
82 #define LCR_PEVEN 0x10
83 #define CFCR_PEVEN LCR_PEVEN
85 #define CFCR_PODD LCR_PODD
86 #define LCR_PENAB 0x08
87 #define CFCR_PENAB LCR_PENAB
88 #define LCR_STOPB 0x04
89 #define CFCR_STOPB LCR_STOPB
90 #define LCR_8BITS 0x03
91 #define CFCR_8BITS LCR_8BITS
92 #define LCR_7BITS 0x02
93 #define CFCR_7BITS LCR_7BITS
94 #define LCR_6BITS 0x01
95 #define CFCR_6BITS LCR_6BITS
96 #define LCR_5BITS 0x00
97 #define CFCR_5BITS LCR_5BITS
99 #define com_mcr 4 /* modem control register (R/W) */
100 #define REG_MCR com_mcr
101 #define MCR_PRESCALE 0x80 /* only available on 16650 up */
102 #define MCR_LOOPBACK 0x10
104 #define MCR_IENABLE MCR_IE
109 #define MCR_BITS "\20\1DTR\2RTS\3DRS\4IE\5LOOPBACK\10PRESCALE"
111 #define com_lsr 5 /* line status register (R/W) */
112 #define REG_LSR com_lsr
113 #define LSR_RCV_FIFO 0x80
114 #define LSR_TEMT 0x40
115 #define LSR_TSRE LSR_TEMT
116 #define LSR_THRE 0x20
117 #define LSR_TXRDY LSR_THRE
122 #define LSR_RXRDY 0x01
123 #define LSR_RCV_MASK 0x1f
125 #define LSR_BITS "\20\1RXRDY\2OE\3PE\4FE\5BI\6THRE\7TEMT\10RCV_FIFO"
127 #define com_msr 6 /* modem status register (R/W) */
128 #define REG_MSR com_msr
133 #define MSR_DDCD 0x08
134 #define MSR_TERI 0x04
135 #define MSR_DDSR 0x02
136 #define MSR_DCTS 0x01
138 #define MSR_BITS "\20\1DCTS\2DDSR\3TERI\4DDCD\5CTS\6DSR\7RI\10DCD"
140 /* 8250 multiplexed registers #[0-1]. Access enabled by LCR[7]. */
141 #define com_dll 0 /* divisor latch low (R/W) */
142 #define com_dlbl com_dll
143 #define com_dlm 1 /* divisor latch high (R/W) */
144 #define com_dlbh com_dlm
145 #define REG_DLL com_dll
146 #define REG_DLH com_dlm
148 /* 16450 register #7. Not multiplexed. */
149 #define com_scr 7 /* scratch register (R/W) */
151 /* 16550 register #2. Not multiplexed. */
152 #define com_fcr 2 /* FIFO control register (W) */
153 #define com_fifo com_fcr
154 #define REG_FCR com_fcr
155 #define FCR_ENABLE 0x01
156 #define FIFO_ENABLE FCR_ENABLE
157 #define FCR_RCV_RST 0x02
158 #define FIFO_RCV_RST FCR_RCV_RST
159 #define FCR_XMT_RST 0x04
160 #define FIFO_XMT_RST FCR_XMT_RST
162 #define FIFO_DMA_MODE FCR_DMA
163 #define FCR_RX_LOW 0x00
164 #define FIFO_RX_LOW FCR_RX_LOW
165 #define FCR_RX_MEDL 0x40
166 #define FIFO_RX_MEDL FCR_RX_MEDL
167 #define FCR_RX_MEDH 0x80
168 #define FIFO_RX_MEDH FCR_RX_MEDH
169 #define FCR_RX_HIGH 0xc0
170 #define FIFO_RX_HIGH FCR_RX_HIGH
172 #define FCR_BITS "\20\1ENABLE\2RCV_RST\3XMT_RST\4DMA"
174 /* 16650 registers #2,[4-7]. Access enabled by LCR_EFR_ENABLE. */
176 #define com_efr 2 /* enhanced features register (R/W) */
177 #define REG_EFR com_efr
179 #define EFR_AUTOCTS EFR_CTS
181 #define EFR_AUTORTS EFR_RTS
182 #define EFR_EFE 0x10 /* enhanced functions enable */
184 #define com_xon1 4 /* XON 1 character (R/W) */
185 #define com_xon2 5 /* XON 2 character (R/W) */
186 #define com_xoff1 6 /* XOFF 1 character (R/W) */
187 #define com_xoff2 7 /* XOFF 2 character (R/W) */
189 #define DW_REG_USR 31 /* DesignWare derived Uart Status Reg */
190 #define com_usr 39 /* Octeon 16750/16550 Uart Status Reg */
191 #define REG_USR com_usr
192 #define USR_BUSY 1 /* Uart Busy. Serial transfer in progress */
193 #define USR_TXFIFO_NOTFULL 2 /* Uart TX FIFO Not full */
195 /* 16950 register #1. Access enabled by ACR[7]. Also requires !LCR[7]. */
196 #define com_asr 1 /* additional status register (R[0-7]/W[0-1]) */
198 /* 16950 register #3. R/W access enabled by ACR[7]. */
199 #define com_rfl 3 /* receiver fifo level (R) */
202 * 16950 register #4. Access enabled by ACR[7]. Also requires
205 #define com_tfl 4 /* transmitter fifo level (R) */
208 * 16950 register #5. Accessible if !LCR_EFR_ENABLE. Read access also
211 #define com_icr 5 /* index control register (R/W) */
212 #define REG_ICR com_icr
215 * 16950 register #7. It is the same as com_scr except it has a different
216 * abbreviation in the manufacturer's data sheet and it also serves as an
217 * index into the Indexed Control register set.
219 #define com_spr com_scr /* scratch pad (and index) register (R/W) */
220 #define REG_SPR com_scr
223 * 16950 indexed control registers #[0-0x13]. Access is via index in SPR,
224 * data in ICR (if ICR is accessible).
227 #define com_acr 0 /* additional control register (R/W) */
228 #define REG_ACR com_acr
229 #define ACR_ASE 0x80 /* ASR/RFL/TFL enable */
230 #define ACR_ICRE 0x40 /* ICR enable */
231 #define ACR_TLE 0x20 /* TTL/RTL enable */
233 #define com_cpr 1 /* clock prescaler register (R/W) */
234 #define com_tcr 2 /* times clock register (R/W) */
235 #define com_ttl 4 /* transmitter trigger level (R/W) */
236 #define com_rtl 5 /* receiver trigger level (R/W) */
239 /* Hardware extension mode register for RSB-2000/3000. */
240 #define com_emr com_msr
241 #define EMR_EXBUFF 0x04
242 #define EMR_CTSFLW 0x08
243 #define EMR_DSRFLW 0x10
244 #define EMR_RTSFLW 0x20
245 #define EMR_DTRFLW 0x40
246 #define EMR_EFMODE 0x80