2 * Copyright (c) 2006 Juniper Networks
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 #ifndef _DEV_IC_QUICC_H_
30 #define _DEV_IC_QUICC_H_
33 * Device parameter RAM
35 #define QUICC_PRAM_BASE 0x8000
37 #define QUICC_PRAM_REV_NUM (QUICC_PRAM_BASE + 0xaf0)
39 /* SCC parameter RAM. */
40 #define QUICC_PRAM_SIZE_SCC 256
41 #define QUICC_PRAM_BASE_SCC(u) (QUICC_PRAM_BASE + QUICC_PRAM_SIZE_SCC * (u))
43 /* SCC parameters that are common for all modes. */
44 #define QUICC_PRAM_SCC_RBASE(u) (QUICC_PRAM_BASE_SCC(u) + 0x00)
45 #define QUICC_PRAM_SCC_TBASE(u) (QUICC_PRAM_BASE_SCC(u) + 0x02)
46 #define QUICC_PRAM_SCC_RFCR(u) (QUICC_PRAM_BASE_SCC(u) + 0x04)
47 #define QUICC_PRAM_SCC_TFCR(u) (QUICC_PRAM_BASE_SCC(u) + 0x05)
48 #define QUICC_PRAM_SCC_MRBLR(u) (QUICC_PRAM_BASE_SCC(u) + 0x06)
49 #define QUICC_PRAM_SCC_RBPTR(u) (QUICC_PRAM_BASE_SCC(u) + 0x10)
50 #define QUICC_PRAM_SCC_TBPTR(u) (QUICC_PRAM_BASE_SCC(u) + 0x20)
53 * SCC parameters that are specific to UART/ASYNC mode.
55 #define QUICC_PRAM_SIZE_SCC_UART 0x68 /* Rounded up. */
57 #define QUICC_PRAM_SCC_UART_MAX_IDL(u) (QUICC_PRAM_BASE_SCC(u) + 0x38)
58 #define QUICC_PRAM_SCC_UART_IDLC(u) (QUICC_PRAM_BASE_SCC(u) + 0x3a)
59 #define QUICC_PRAM_SCC_UART_BRKCR(u) (QUICC_PRAM_BASE_SCC(u) + 0x3c)
60 #define QUICC_PRAM_SCC_UART_PAREC(u) (QUICC_PRAM_BASE_SCC(u) + 0x3e)
61 #define QUICC_PRAM_SCC_UART_FRMEC(u) (QUICC_PRAM_BASE_SCC(u) + 0x40)
62 #define QUICC_PRAM_SCC_UART_NOSEC(u) (QUICC_PRAM_BASE_SCC(u) + 0x42)
63 #define QUICC_PRAM_SCC_UART_BRKEC(u) (QUICC_PRAM_BASE_SCC(u) + 0x44)
64 #define QUICC_PRAM_SCC_UART_BRKLN(u) (QUICC_PRAM_BASE_SCC(u) + 0x46)
65 #define QUICC_PRAM_SCC_UART_UADDR1(u) (QUICC_PRAM_BASE_SCC(u) + 0x48)
66 #define QUICC_PRAM_SCC_UART_UADDR2(u) (QUICC_PRAM_BASE_SCC(u) + 0x4a)
67 #define QUICC_PRAM_SCC_UART_TOSEQ(u) (QUICC_PRAM_BASE_SCC(u) + 0x4e)
68 #define QUICC_PRAM_SCC_UART_CC(u,n) (QUICC_PRAM_BASE_SCC(u) + 0x50 + (n)*2)
69 #define QUICC_PRAM_SCC_UART_RCCM(u) (QUICC_PRAM_BASE_SCC(u) + 0x60)
70 #define QUICC_PRAM_SCC_UART_RCCR(u) (QUICC_PRAM_BASE_SCC(u) + 0x62)
71 #define QUICC_PRAM_SCC_UART_RLBC(u) (QUICC_PRAM_BASE_SCC(u) + 0x64)
74 * Interrupt controller.
76 #define QUICC_REG_SICR 0x10c00
77 #define QUICC_REG_SIVEC 0x10c04
78 #define QUICC_REG_SIPNR_H 0x10c08
79 #define QUICC_REG_SIPNR_L 0x10c0c
80 #define QUICC_REG_SCPRR_H 0x10c14
81 #define QUICC_REG_SCPRR_L 0x10c18
82 #define QUICC_REG_SIMR_H 0x10c1c
83 #define QUICC_REG_SIMR_L 0x10c20
84 #define QUICC_REG_SIEXR 0x10c24
87 * System clock control register.
89 #define QUICC_REG_SCCR 0x10c80
92 * Baudrate generator registers.
94 #define QUICC_REG_BRG(u) (0x119f0 + ((u) & 3) * 4 - ((u) & 4) * 0x100)
99 #define QUICC_REG_SIZE_SCC 0x20
100 #define QUICC_REG_BASE_SCC(u) (0x11a00 + QUICC_REG_SIZE_SCC * (u))
102 #define QUICC_REG_SCC_GSMR_L(u) (QUICC_REG_BASE_SCC(u) + 0x00)
103 #define QUICC_REG_SCC_GSMR_H(u) (QUICC_REG_BASE_SCC(u) + 0x04)
104 #define QUICC_REG_SCC_PSMR(u) (QUICC_REG_BASE_SCC(u) + 0x08)
105 #define QUICC_REG_SCC_TODR(u) (QUICC_REG_BASE_SCC(u) + 0x0c)
106 #define QUICC_REG_SCC_DSR(u) (QUICC_REG_BASE_SCC(u) + 0x0e)
107 #define QUICC_REG_SCC_SCCE(u) (QUICC_REG_BASE_SCC(u) + 0x10)
108 #define QUICC_REG_SCC_SCCM(u) (QUICC_REG_BASE_SCC(u) + 0x14)
109 #define QUICC_REG_SCC_SCCS(u) (QUICC_REG_BASE_SCC(u) + 0x17)
111 #endif /* _DEV_IC_QUICC_H_ */