2 * Copyright 2004 by Peter Grehan. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #ifndef _VIA6522REG_H_
31 #define _VIA6522REG_H_
34 #define REG_OIRB 0 /* Input/output register B */
35 #define REG_OIRA 1 /* Input/output register A */
36 #define REG_DDRB 2 /* Data direction register B */
37 #define REG_DDRA 3 /* Data direction register A */
38 #define REG_T1CL 4 /* T1 low-order latch/low-order counter */
39 #define REG_T1CH 5 /* T1 high-order counter */
40 #define REG_T1LL 6 /* T1 low-order latches */
41 #define REG_T1LH 7 /* T1 high-order latches */
42 #define REG_T2CL 8 /* T2 low-order latch/low-order counter */
43 #define REG_T2CH 9 /* T2 high-order counter */
44 #define REG_SR 10 /* Shift register */
45 #define REG_ACR 11 /* Auxiliary control register */
46 #define REG_PCR 12 /* Peripheral control register */
47 #define REG_IFR 13 /* Interrupt flag register */
48 #define REG_IER 14 /* Interrupt-enable register */
49 #define REG_OIRA_NH 15 /* Input/output register A: no handshake */
52 /* Auxiliary control register (11) */
53 #define ACR_SR_NONE 0x0 /* Disabled */
54 #define ACR_SR_DIR 0x4 /* Bit for shift-register direction 1=out */
55 #define ACR_SRI_T2 0x1 /* Shift in under control of T2 */
56 #define ACR_SRI_PHI2 0x2 /* " " " " " PHI2 */
57 #define ACR_SRI_EXTCLK 0x3 /* " " " " " external clk */
58 #define ACR_SRO 0x4 /* Shift out free running at T2 rate */
59 #define ACR_SRO_T2 0x5 /* Shift out under control of T2 */
60 #define ACR_SRO_PHI2 0x6 /* " " " " " PHI2 */
61 #define ACR_SRO_EXTCLK 0x7 /* " " " " " external clk */
63 #define ACR_T1_SHIFT 5 /* bits 7-5 */
64 #define ACR_SR_SHIFT 2 /* bits 4-2 */
67 /* Peripheral control register (12) */
68 #define PCR_INTCNTL 0x01 /* interrupt active edge: +ve=1, -ve=0 */
70 #define PCR_CNTL_MASK 0x3 /* 3 bits */
71 #define PCR_CNTL_NEDGE 0x0 /* Input - negative active edge */
72 #define PCR_CNTL_INEDGE 0x1 /* Interrupt - negative active edge */
73 #define PCR_CNTL_PEDGE 0x2 /* Input - positive active edge */
74 #define PCR_CNTL_IPEDGE 0x3 /* Interrupt - positive active edge */
75 #define PCR_CNTL_HSHAKE 0x4 /* Handshake output */
76 #define PCR_CNTL_PULSE 0x5 /* Pulse output */
77 #define PCR_CNTL_LOW 0x6 /* Low output */
78 #define PCR_CNTL_HIGH 0x7 /* High output */
80 #define PCR_CB2_SHIFT 5 /* bits 7-5 */
81 #define PCR_CB1_SHIFT 4 /* bit 4 */
82 #define PCR_CA2_SHIFT 1 /* bits 3-1 */
83 #define PCR_CA1_SHIFT 0 /* bit 0 */
85 /* Interrupt flag register (13) */
93 #define IFR_IRQB 0x80 /* status of IRQB output pin */
95 /* Interrupt enable register (14) */
96 #define IER_CA2 IFR_CA2
97 #define IER_CA1 IFR_CA1
99 #define IER_CB2 IFR_CB2
100 #define IER_CB1 IFR_CB1
101 #define IER_T2 IFR_T2
102 #define IER_T1 IFR_T1
103 #define IER_IRQB IFR_IRQB
105 #endif /* _VIA6522REG_H_ */