1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright (c) 2020, Intel Corporation
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of the Intel Corporation nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
33 #ifndef _ICE_CONTROLQ_H_
34 #define _ICE_CONTROLQ_H_
36 #include "ice_adminq_cmd.h"
38 /* Maximum buffer lengths for all control queue types */
39 #define ICE_AQ_MAX_BUF_LEN 4096
40 #define ICE_MBXQ_MAX_BUF_LEN 4096
42 #define ICE_CTL_Q_DESC(R, i) \
43 (&(((struct ice_aq_desc *)((R).desc_buf.va))[i]))
45 #define ICE_CTL_Q_DESC_UNUSED(R) \
46 (u16)((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
47 (R)->next_to_clean - (R)->next_to_use - 1)
49 /* Defines that help manage the driver vs FW API checks.
50 * Take a look at ice_aq_ver_check in ice_controlq.c for actual usage.
52 #define EXP_FW_API_VER_BRANCH 0x00
53 #define EXP_FW_API_VER_MAJOR 0x01
54 #define EXP_FW_API_VER_MINOR 0x05
56 /* Different control queue types: These are mainly for SW consumption. */
58 ICE_CTL_Q_UNKNOWN = 0,
63 /* Control Queue timeout settings - max delay 250ms */
64 #define ICE_CTL_Q_SQ_CMD_TIMEOUT 2500 /* Count 2500 times */
65 #define ICE_CTL_Q_SQ_CMD_USEC 100 /* Check every 100usec */
67 struct ice_ctl_q_ring {
68 void *dma_head; /* Virtual address to DMA head */
69 struct ice_dma_mem desc_buf; /* descriptor ring memory */
70 void *cmd_buf; /* command buffer memory */
73 struct ice_dma_mem *sq_bi;
74 struct ice_dma_mem *rq_bi;
77 u16 count; /* Number of descriptors */
79 /* used for interrupt processing */
83 /* used for queue tracking */
94 /* sq transaction details */
96 struct ice_aq_desc *wb_desc;
99 #define ICE_CTL_Q_DETAILS(R, i) (&(((struct ice_sq_cd *)((R).cmd_buf))[i]))
101 /* rq event information */
102 struct ice_rq_event_info {
103 struct ice_aq_desc desc;
109 /* Control Queue information */
110 struct ice_ctl_q_info {
111 enum ice_ctl_q qtype;
112 enum ice_aq_err rq_last_status; /* last status on receive queue */
113 struct ice_ctl_q_ring rq; /* receive queue */
114 struct ice_ctl_q_ring sq; /* send queue */
115 u32 sq_cmd_timeout; /* send queue cmd write back timeout */
116 u16 num_rq_entries; /* receive queue depth */
117 u16 num_sq_entries; /* send queue depth */
118 u16 rq_buf_size; /* receive queue buffer size */
119 u16 sq_buf_size; /* send queue buffer size */
120 enum ice_aq_err sq_last_status; /* last status on send queue */
121 struct ice_lock sq_lock; /* Send queue lock */
122 struct ice_lock rq_lock; /* Receive queue lock */
125 #endif /* _ICE_CONTROLQ_H_ */