1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright (c) 2020, Intel Corporation
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of the Intel Corporation nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
36 #define ICE_NVM_CMD_READ 0x0000000B
37 #define ICE_NVM_CMD_WRITE 0x0000000C
39 /* NVM Access config bits */
40 #define ICE_NVM_CFG_MODULE_M MAKEMASK(0xFF, 0)
41 #define ICE_NVM_CFG_MODULE_S 0
42 #define ICE_NVM_CFG_FLAGS_M MAKEMASK(0xF, 8)
43 #define ICE_NVM_CFG_FLAGS_S 8
44 #define ICE_NVM_CFG_EXT_FLAGS_M MAKEMASK(0xF, 12)
45 #define ICE_NVM_CFG_EXT_FLAGS_S 12
46 #define ICE_NVM_CFG_ADAPTER_INFO_M MAKEMASK(0xFFFF, 16)
47 #define ICE_NVM_CFG_ADAPTER_INFO_S 16
49 /* NVM Read Get Driver Features */
50 #define ICE_NVM_GET_FEATURES_MODULE 0xE
51 #define ICE_NVM_GET_FEATURES_FLAGS 0xF
53 /* NVM Read/Write Mapped Space */
54 #define ICE_NVM_REG_RW_MODULE 0x0
55 #define ICE_NVM_REG_RW_FLAGS 0x1
57 #define ICE_NVM_ACCESS_MAJOR_VER 0
58 #define ICE_NVM_ACCESS_MINOR_VER 5
60 /* NVM Access feature flags. Other bits in the features field are reserved and
61 * should be set to zero when reporting the ice_nvm_features structure.
63 #define ICE_NVM_FEATURES_0_REG_ACCESS BIT(1)
65 /* NVM Access Features */
66 struct ice_nvm_features {
67 u8 major; /* Major version (informational only) */
68 u8 minor; /* Minor version (informational only) */
69 u16 size; /* size of ice_nvm_features structure */
70 u8 features[12]; /* Array of feature bits */
73 /* NVM Access command */
74 struct ice_nvm_access_cmd {
75 u32 command; /* NVM command: READ or WRITE */
76 u32 config; /* NVM command configuration */
77 u32 offset; /* offset to read/write, in bytes */
78 u32 data_size; /* size of data field, in bytes */
82 union ice_nvm_access_data {
83 u32 regval; /* Storage for register value */
84 struct ice_nvm_features drv_features; /* NVM features */
87 /* NVM Access registers */
88 #define GL_HIDA(_i) (0x00082000 + ((_i) * 4))
89 #define GL_HIBA(_i) (0x00081000 + ((_i) * 4))
90 #define GL_HICR 0x00082040
91 #define GL_HICR_EN 0x00082044
92 #define GLGEN_CSR_DEBUG_C 0x00075750
93 #define GLPCI_LBARCTRL 0x0009DE74
94 #define GLNVM_GENS 0x000B6100
95 #define GLNVM_FLA 0x000B6108
97 #define ICE_NVM_ACCESS_GL_HIDA_MAX 15
98 #define ICE_NVM_ACCESS_GL_HIBA_MAX 1023
100 u32 ice_nvm_access_get_module(struct ice_nvm_access_cmd *cmd);
101 u32 ice_nvm_access_get_flags(struct ice_nvm_access_cmd *cmd);
102 u32 ice_nvm_access_get_adapter(struct ice_nvm_access_cmd *cmd);
104 ice_nvm_access_read(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
105 union ice_nvm_access_data *data);
107 ice_nvm_access_write(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
108 union ice_nvm_access_data *data);
110 ice_nvm_access_get_features(struct ice_nvm_access_cmd *cmd,
111 union ice_nvm_access_data *data);
113 ice_handle_nvm_access(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
114 union ice_nvm_access_data *data);
116 ice_acquire_nvm(struct ice_hw *hw, enum ice_aq_res_access_type access);
117 void ice_release_nvm(struct ice_hw *hw);
119 ice_aq_read_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset, u16 length,
120 void *data, bool last_command, bool read_shadow_ram,
121 struct ice_sq_cd *cd);
123 ice_read_flat_nvm(struct ice_hw *hw, u32 offset, u32 *length, u8 *data,
124 bool read_shadow_ram);
126 ice_get_pfa_module_tlv(struct ice_hw *hw, u16 *module_tlv, u16 *module_tlv_len,
129 ice_read_pba_string(struct ice_hw *hw, u8 *pba_num, u32 pba_num_size);
130 enum ice_status ice_init_nvm(struct ice_hw *hw);
131 enum ice_status ice_read_sr_word(struct ice_hw *hw, u16 offset, u16 *data);
132 enum ice_status ice_read_sr_word_aq(struct ice_hw *hw, u16 offset, u16 *data);
134 ice_read_sr_buf(struct ice_hw *hw, u16 offset, u16 *words, u16 *data);
136 ice_aq_erase_nvm(struct ice_hw *hw, u16 module_typeid, struct ice_sq_cd *cd);
138 ice_aq_update_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset,
139 u16 length, void *data, bool last_command, u8 command_flags,
140 struct ice_sq_cd *cd);
142 ice_aq_read_nvm_cfg(struct ice_hw *hw, u8 cmd_flags, u16 field_id, void *data,
143 u16 buf_size, u16 *elem_count, struct ice_sq_cd *cd);
145 ice_aq_write_nvm_cfg(struct ice_hw *hw, u8 cmd_flags, void *data, u16 buf_size,
146 u16 elem_count, struct ice_sq_cd *cd);
147 enum ice_status ice_update_sr_checksum(struct ice_hw *hw);
148 enum ice_status ice_validate_sr_checksum(struct ice_hw *hw, u16 *checksum);
149 enum ice_status ice_nvm_validate_checksum(struct ice_hw *hw);
150 #endif /* _ICE_NVM_H_ */