1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright (c) 2020, Intel Corporation
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35 * @brief Functions used to implement OS compatibility layer
37 * Contains functions used by ice_osdep.h to implement the OS compatibility
38 * layer used by some of the hardware files. Specifically, it is for the bits
39 * of OS compatibility which don't make sense as macros or inline functions.
42 #include "ice_common.h"
43 #include "ice_iflib.h"
44 #include <machine/stdarg.h>
49 * @brief OS compatibility layer allocation type
51 * malloc(9) allocation type used by the OS compatibility layer for
52 * distinguishing allocations by this layer from those of the rest of the
55 MALLOC_DEFINE(M_ICE_OSDEP, "ice-osdep", "Intel(R) 100Gb Network Driver osdep allocations");
59 * @brief Global count of # of ice_lock mutexes initialized
61 * A global count of the total number of times that ice_init_lock has been
62 * called. This is used to generate unique lock names for each ice_lock, to
63 * aid in witness lock checking.
65 u16 ice_lock_count = 0;
67 static void ice_dmamap_cb(void *arg, bus_dma_segment_t * segs, int __unused nseg, int error);
70 * ice_hw_to_dev - Given a hw private struct, find the associated device_t
71 * @hw: the hardware private structure
73 * Given a hw structure pointer, lookup the softc and extract the device
74 * pointer. Assumes that hw is embedded within the ice_softc, instead of being
75 * allocated separately, so that __containerof math will work.
77 * This can't be defined in ice_osdep.h as it depends on the complete
78 * definition of struct ice_softc. That can't be easily included in
79 * ice_osdep.h without creating circular header dependencies.
82 ice_hw_to_dev(struct ice_hw *hw) {
83 struct ice_softc *sc = __containerof(hw, struct ice_softc, hw);
89 * ice_debug - Log a debug message if the type is enabled
90 * @hw: device private hardware structure
91 * @mask: the debug message type
92 * @fmt: printf format specifier
94 * Check if hw->debug_mask has enabled the given message type. If so, log the
95 * message to the console using vprintf. Mimic the output of device_printf by
96 * using device_print_prettyname().
99 ice_debug(struct ice_hw *hw, uint64_t mask, char *fmt, ...)
101 device_t dev = ice_hw_to_dev(hw);
104 if (!(mask & hw->debug_mask))
107 device_print_prettyname(dev);
114 * ice_debug_array - Format and print an array of values to the console
115 * @hw: private hardware structure
116 * @mask: the debug message type
117 * @rowsize: preferred number of rows to use
118 * @groupsize: preferred size in bytes to print each chunk
119 * @buf: the array buffer to print
120 * @len: size of the array buffer
122 * Format the given array as a series of uint8_t values with hexadecimal
123 * notation and log the contents to the console log.
125 * TODO: Currently only supports a group size of 1, due to the way hexdump is
129 ice_debug_array(struct ice_hw *hw, uint64_t mask, uint32_t rowsize,
130 uint32_t __unused groupsize, uint8_t *buf, size_t len)
132 device_t dev = ice_hw_to_dev(hw);
135 if (!(mask & hw->debug_mask))
138 /* Format the device header to a string */
139 snprintf(prettyname, sizeof(prettyname), "%s: ", device_get_nameunit(dev));
141 /* Make sure the row-size isn't too large */
145 hexdump(buf, len, prettyname, HD_OMIT_CHARS | rowsize);
149 * rd32 - Read a 32bit hardware register value
150 * @hw: the private hardware structure
151 * @reg: register address to read
153 * Read the specified 32bit register value from BAR0 and return its contents.
156 rd32(struct ice_hw *hw, uint32_t reg)
158 struct ice_softc *sc = __containerof(hw, struct ice_softc, hw);
160 return bus_space_read_4(sc->bar0.tag, sc->bar0.handle, reg);
164 * rd64 - Read a 64bit hardware register value
165 * @hw: the private hardware structure
166 * @reg: register address to read
168 * Read the specified 64bit register value from BAR0 and return its contents.
170 * @pre For 32-bit builds, assumes that the 64bit register read can be
171 * safely broken up into two 32-bit register reads.
174 rd64(struct ice_hw *hw, uint32_t reg)
176 struct ice_softc *sc = __containerof(hw, struct ice_softc, hw);
180 data = bus_space_read_8(sc->bar0.tag, sc->bar0.handle, reg);
183 * bus_space_read_8 isn't supported on 32bit platforms, so we fall
184 * back to using two bus_space_read_4 calls.
186 data = bus_space_read_4(sc->bar0.tag, sc->bar0.handle, reg);
187 data |= ((uint64_t)bus_space_read_4(sc->bar0.tag, sc->bar0.handle, reg + 4)) << 32;
194 * wr32 - Write a 32bit hardware register
195 * @hw: the private hardware structure
196 * @reg: the register address to write to
197 * @val: the 32bit value to write
199 * Write the specified 32bit value to a register address in BAR0.
202 wr32(struct ice_hw *hw, uint32_t reg, uint32_t val)
204 struct ice_softc *sc = __containerof(hw, struct ice_softc, hw);
206 bus_space_write_4(sc->bar0.tag, sc->bar0.handle, reg, val);
210 * wr64 - Write a 64bit hardware register
211 * @hw: the private hardware structure
212 * @reg: the register address to write to
213 * @val: the 64bit value to write
215 * Write the specified 64bit value to a register address in BAR0.
217 * @pre For 32-bit builds, assumes that the 64bit register write can be safely
218 * broken up into two 32-bit register writes.
221 wr64(struct ice_hw *hw, uint32_t reg, uint64_t val)
223 struct ice_softc *sc = __containerof(hw, struct ice_softc, hw);
226 bus_space_write_8(sc->bar0.tag, sc->bar0.handle, reg, val);
228 uint32_t lo_val, hi_val;
231 * bus_space_write_8 isn't supported on 32bit platforms, so we fall
232 * back to using two bus_space_write_4 calls.
234 lo_val = (uint32_t)val;
235 hi_val = (uint32_t)(val >> 32);
236 bus_space_write_4(sc->bar0.tag, sc->bar0.handle, reg, lo_val);
237 bus_space_write_4(sc->bar0.tag, sc->bar0.handle, reg + 4, hi_val);
242 * ice_usec_delay - Delay for the specified number of microseconds
243 * @time: microseconds to delay
244 * @sleep: if true, sleep where possible
246 * If sleep is true, and if the current thread is allowed to sleep, pause so
247 * that another thread can execute. Otherwise, use DELAY to spin the thread
251 ice_usec_delay(uint32_t time, bool sleep)
253 if (sleep && THREAD_CAN_SLEEP())
254 pause("ice_usec_delay", USEC_2_TICKS(time));
260 * ice_msec_delay - Delay for the specified number of milliseconds
261 * @time: milliseconds to delay
262 * @sleep: if true, sleep where possible
264 * If sleep is true, and if the current thread is allowed to sleep, pause so
265 * that another thread can execute. Otherwise, use DELAY to spin the thread
269 ice_msec_delay(uint32_t time, bool sleep)
271 if (sleep && THREAD_CAN_SLEEP())
272 pause("ice_msec_delay", MSEC_2_TICKS(time));
278 * ice_msec_pause - pause (sleep) the thread for a time in milliseconds
279 * @time: milliseconds to sleep
281 * Wrapper for ice_msec_delay with sleep set to true.
284 ice_msec_pause(uint32_t time)
286 ice_msec_delay(time, true);
290 * ice_msec_spin - Spin the thread for a time in milliseconds
291 * @time: milliseconds to delay
293 * Wrapper for ice_msec_delay with sleep sent to false.
296 ice_msec_spin(uint32_t time)
298 ice_msec_delay(time, false);
301 /********************************************************************
302 * Manage DMA'able memory.
303 *******************************************************************/
306 * ice_dmamap_cb - Callback function DMA maps
307 * @arg: pointer to return the segment address
308 * @segs: the segments array
309 * @nseg: number of segments in the array
312 * Callback used by the bus DMA code to obtain the segment address.
315 ice_dmamap_cb(void *arg, bus_dma_segment_t * segs, int __unused nseg, int error)
319 *(bus_addr_t *) arg = segs->ds_addr;
324 * ice_alloc_dma_mem - Request OS to allocate DMA memory
325 * @hw: private hardware structure
326 * @mem: structure defining the DMA memory request
327 * @size: the allocation size
329 * Allocates some memory for DMA use. Use the FreeBSD bus DMA interface to
330 * track this memory using a bus DMA tag and map.
332 * Returns a pointer to the DMA memory address.
335 ice_alloc_dma_mem(struct ice_hw *hw, struct ice_dma_mem *mem, u64 size)
337 device_t dev = ice_hw_to_dev(hw);
340 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
341 1, 0, /* alignment, boundary */
342 BUS_SPACE_MAXADDR, /* lowaddr */
343 BUS_SPACE_MAXADDR, /* highaddr */
344 NULL, NULL, /* filtfunc, filtfuncarg */
348 BUS_DMA_ALLOCNOW, /* flags */
350 NULL, /* lockfuncarg */
354 "ice_alloc_dma: bus_dma_tag_create failed, "
355 "error %s\n", ice_err_str(err));
358 err = bus_dmamem_alloc(mem->tag, (void **)&mem->va,
359 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &mem->map);
362 "ice_alloc_dma: bus_dmamem_alloc failed, "
363 "error %s\n", ice_err_str(err));
366 err = bus_dmamap_load(mem->tag, mem->map, mem->va,
373 "ice_alloc_dma: bus_dmamap_load failed, "
374 "error %s\n", ice_err_str(err));
378 bus_dmamap_sync(mem->tag, mem->map,
379 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
382 bus_dmamem_free(mem->tag, mem->va, mem->map);
384 bus_dma_tag_destroy(mem->tag);
392 * ice_free_dma_mem - Free DMA memory allocated by ice_alloc_dma_mem
393 * @hw: the hardware private structure
394 * @mem: DMA memory to free
396 * Release the bus DMA tag and map, and free the DMA memory associated with
400 ice_free_dma_mem(struct ice_hw __unused *hw, struct ice_dma_mem *mem)
402 bus_dmamap_sync(mem->tag, mem->map,
403 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
404 bus_dmamap_unload(mem->tag, mem->map);
405 bus_dmamem_free(mem->tag, mem->va, mem->map);
406 bus_dma_tag_destroy(mem->tag);