1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright (c) 2020, Intel Corporation
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of the Intel Corporation nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
38 #define ETH_HEADER_LEN 14
40 #define BIT(a) (1UL << (a))
42 #define BIT_ULL(a) (1ULL << (a))
45 #define BITS_PER_BYTE 8
49 #define ICE_BYTES_PER_WORD 2
50 #define ICE_BYTES_PER_DWORD 4
51 #define ICE_MAX_TRAFFIC_CLASS 8
54 #define MIN_T(_t, _a, _b) min((_t)(_a), (_t)(_b))
57 #define IS_ASCII(_ch) ((_ch) < 0x80)
59 #define STRUCT_HACK_VAR_LEN
61 * ice_struct_size - size of struct with C99 flexible array member
62 * @ptr: pointer to structure
63 * @field: flexible array member (last member of the structure)
64 * @num: number of elements of that flexible array member
66 #define ice_struct_size(ptr, field, num) \
67 (sizeof(*(ptr)) + sizeof(*(ptr)->field) * (num))
69 #include "ice_status.h"
70 #include "ice_hw_autogen.h"
71 #include "ice_devids.h"
72 #include "ice_osdep.h"
73 #include "ice_bitops.h" /* Must come before ice_controlq.h */
74 #include "ice_controlq.h"
75 #include "ice_lan_tx_rx.h"
76 #include "ice_flex_type.h"
77 #include "ice_protocol_type.h"
79 static inline bool ice_is_tc_ena(ice_bitmap_t bitmap, u8 tc)
81 return !!(bitmap & BIT(tc));
84 #define DIV_64BIT(n, d) ((n) / (d))
86 static inline u64 round_up_64bit(u64 a, u32 b)
88 return DIV_64BIT(((a) + (b) / 2), (b));
91 static inline u32 ice_round_to_num(u32 N, u32 R)
93 return ((((N) % (R)) < ((R) / 2)) ? (((N) / (R)) * (R)) :
94 ((((N) + (R) - 1) / (R)) * (R)));
97 /* Driver always calls main vsi_handle first */
98 #define ICE_MAIN_VSI_HANDLE 0
100 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
101 #define ICE_MS_TO_GTIME(time) ((time) * 1000)
103 /* Data type manipulation macros. */
104 #define ICE_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
105 #define ICE_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF))
106 #define ICE_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF))
107 #define ICE_LO_WORD(x) ((u16)((x) & 0xFFFF))
109 /* debug masks - set these bits in hw->debug_mask to control output */
110 #define ICE_DBG_TRACE BIT_ULL(0) /* for function-trace only */
111 #define ICE_DBG_INIT BIT_ULL(1)
112 #define ICE_DBG_RELEASE BIT_ULL(2)
113 #define ICE_DBG_FW_LOG BIT_ULL(3)
114 #define ICE_DBG_LINK BIT_ULL(4)
115 #define ICE_DBG_PHY BIT_ULL(5)
116 #define ICE_DBG_QCTX BIT_ULL(6)
117 #define ICE_DBG_NVM BIT_ULL(7)
118 #define ICE_DBG_LAN BIT_ULL(8)
119 #define ICE_DBG_FLOW BIT_ULL(9)
120 #define ICE_DBG_DCB BIT_ULL(10)
121 #define ICE_DBG_DIAG BIT_ULL(11)
122 #define ICE_DBG_FD BIT_ULL(12)
123 #define ICE_DBG_SW BIT_ULL(13)
124 #define ICE_DBG_SCHED BIT_ULL(14)
126 #define ICE_DBG_PKG BIT_ULL(16)
127 #define ICE_DBG_RES BIT_ULL(17)
128 #define ICE_DBG_AQ_MSG BIT_ULL(24)
129 #define ICE_DBG_AQ_DESC BIT_ULL(25)
130 #define ICE_DBG_AQ_DESC_BUF BIT_ULL(26)
131 #define ICE_DBG_AQ_CMD BIT_ULL(27)
132 #define ICE_DBG_AQ (ICE_DBG_AQ_MSG | \
134 ICE_DBG_AQ_DESC_BUF | \
137 #define ICE_DBG_USER BIT_ULL(31)
138 #define ICE_DBG_ALL 0xFFFFFFFFFFFFFFFFULL
140 #define IS_UNICAST_ETHER_ADDR(addr) \
141 ((bool)((((u8 *)(addr))[0] % ((u8)0x2)) == 0))
143 #define IS_MULTICAST_ETHER_ADDR(addr) \
144 ((bool)((((u8 *)(addr))[0] % ((u8)0x2)) == 1))
146 /* Check whether an address is broadcast. */
147 #define IS_BROADCAST_ETHER_ADDR(addr) \
148 ((bool)((((u16 *)(addr))[0] == ((u16)0xffff))))
150 #define IS_ZERO_ETHER_ADDR(addr) \
151 (((bool)((((u16 *)(addr))[0] == ((u16)0x0)))) && \
152 ((bool)((((u16 *)(addr))[1] == ((u16)0x0)))) && \
153 ((bool)((((u16 *)(addr))[2] == ((u16)0x0)))))
155 #ifndef IS_ETHER_ADDR_EQUAL
156 #define IS_ETHER_ADDR_EQUAL(addr1, addr2) \
157 (((bool)((((u16 *)(addr1))[0] == ((u16 *)(addr2))[0]))) && \
158 ((bool)((((u16 *)(addr1))[1] == ((u16 *)(addr2))[1]))) && \
159 ((bool)((((u16 *)(addr1))[2] == ((u16 *)(addr2))[2]))))
162 enum ice_aq_res_ids {
165 ICE_CHANGE_LOCK_RES_ID,
166 ICE_GLOBAL_CFG_LOCK_RES_ID
169 /* FW update timeout definitions are in milliseconds */
170 #define ICE_NVM_TIMEOUT 180000
171 #define ICE_CHANGE_LOCK_TIMEOUT 1000
172 #define ICE_GLOBAL_CFG_LOCK_TIMEOUT 3000
174 enum ice_aq_res_access_type {
179 struct ice_driver_ver {
184 u8 driver_string[32];
197 enum ice_phy_cache_mode {
210 struct ice_phy_cache_mode_data {
212 enum ice_fec_mode curr_user_fec_req;
213 enum ice_fc_mode curr_user_fc_req;
214 u16 curr_user_speed_req;
218 enum ice_set_fc_aq_failures {
219 ICE_SET_FC_AQ_FAIL_NONE = 0,
220 ICE_SET_FC_AQ_FAIL_GET,
221 ICE_SET_FC_AQ_FAIL_SET,
222 ICE_SET_FC_AQ_FAIL_UPDATE
225 /* These are structs for managing the hardware information and the operations */
235 enum ice_media_type {
236 ICE_MEDIA_UNKNOWN = 0,
244 /* Software VSI types. */
251 struct ice_link_status {
252 /* Refer to ice_aq_phy_type for bits definition */
255 u8 topo_media_conflict;
259 u8 lse_ena; /* Link Status Event notification */
265 /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of
266 * ice_aqc_get_phy_caps structure
268 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
271 /* Different data queue types: These are mainly for SW consumption. */
280 /* Different reset sources for which a disable queue AQ call has to be made in
281 * order to clean the Tx scheduler as a part of the reset
283 enum ice_disq_rst_src {
289 /* PHY info such as phy_type, etc... */
290 struct ice_phy_info {
291 struct ice_link_status link_info;
292 struct ice_link_status link_info_old;
295 enum ice_media_type media_type;
297 /* Please refer to struct ice_aqc_get_link_status_data to get
298 * detail of enable bit in curr_user_speed_req
300 u16 curr_user_speed_req;
301 enum ice_fec_mode curr_user_fec_req;
302 enum ice_fc_mode curr_user_fc_req;
303 struct ice_aqc_set_phy_cfg_data curr_user_phy_cfg;
306 #define ICE_MAX_NUM_MIRROR_RULES 64
308 /* Common HW capabilities for SW use */
309 struct ice_hw_common_caps {
310 /* Write CSR protection */
313 /* switching mode supported - EVB switching (including cloud) */
314 #define ICE_NVM_IMAGE_TYPE_EVB 0x0
316 /* Manageablity mode & supported protocols over MCTP */
318 #define ICE_MGMT_MODE_PASS_THRU_MODE_M 0xF
319 #define ICE_MGMT_MODE_CTL_INTERFACE_M 0xF0
320 #define ICE_MGMT_MODE_REDIR_SB_INTERFACE_M 0xF00
322 u32 mgmt_protocols_mctp;
323 #define ICE_MGMT_MODE_PROTO_RSVD BIT(0)
324 #define ICE_MGMT_MODE_PROTO_PLDM BIT(1)
325 #define ICE_MGMT_MODE_PROTO_OEM BIT(2)
326 #define ICE_MGMT_MODE_PROTO_NC_SI BIT(3)
330 /* DCB capabilities */
331 u32 active_tc_bitmap;
334 /* RSS related capabilities */
335 u32 rss_table_size; /* 512 for PFs and 64 for VFs */
336 u32 rss_table_entry_width; /* RSS Entry width in bits */
339 u32 num_rxq; /* Number/Total Rx queues */
340 u32 rxq_first_id; /* First queue ID for Rx queues */
341 u32 num_txq; /* Number/Total Tx queues */
342 u32 txq_first_id; /* First queue ID for Tx queues */
345 u32 num_msix_vectors;
346 u32 msix_vector_first_id;
348 /* Max MTU for function or device */
352 u32 num_wol_proxy_fltr;
353 u32 wol_proxy_vsi_seid;
355 /* LED/SDP pin count */
359 /* LED/SDP - Supports up to 12 LED pins and 8 SDP signals */
360 #define ICE_MAX_SUPPORTED_GPIO_LED 12
361 #define ICE_MAX_SUPPORTED_GPIO_SDP 8
362 u8 led[ICE_MAX_SUPPORTED_GPIO_LED];
363 u8 sdp[ICE_MAX_SUPPORTED_GPIO_SDP];
365 /* SR-IOV virtualization */
366 u8 sr_iov_1_1; /* SR-IOV enabled */
368 /* EVB capabilities */
369 u8 evb_802_1_qbg; /* Edge Virtual Bridging */
370 u8 evb_802_1_qbh; /* Bridge Port Extension */
376 /* WoL and APM support */
377 #define ICE_WOL_SUPPORT_M BIT(0)
378 #define ICE_ACPI_PROG_MTHD_M BIT(1)
379 #define ICE_PROXY_SUPPORT_M BIT(2)
383 bool nvm_unified_update;
384 #define ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT BIT(3)
387 /* Function specific capabilities */
388 struct ice_hw_func_caps {
389 struct ice_hw_common_caps common_cap;
390 u32 num_allocd_vfs; /* Number of allocated VFs */
391 u32 vf_base_id; /* Logical ID of the first VF */
395 /* Device wide capabilities */
396 struct ice_hw_dev_caps {
397 struct ice_hw_common_caps common_cap;
398 u32 num_vfs_exposed; /* Total number of VFs exposed */
399 u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */
403 /* Information about MAC such as address, etc... */
404 struct ice_mac_info {
405 u8 lan_addr[ETH_ALEN];
406 u8 perm_addr[ETH_ALEN];
407 u8 port_addr[ETH_ALEN];
408 u8 wol_addr[ETH_ALEN];
415 ice_bus_embedded, /* Is device Embedded versus card */
420 enum ice_pcie_bus_speed {
421 ice_pcie_speed_unknown = 0xff,
422 ice_pcie_speed_2_5GT = 0x14,
423 ice_pcie_speed_5_0GT = 0x15,
424 ice_pcie_speed_8_0GT = 0x16,
425 ice_pcie_speed_16_0GT = 0x17
429 enum ice_pcie_link_width {
430 ice_pcie_lnk_width_resrv = 0x00,
431 ice_pcie_lnk_x1 = 0x01,
432 ice_pcie_lnk_x2 = 0x02,
433 ice_pcie_lnk_x4 = 0x04,
434 ice_pcie_lnk_x8 = 0x08,
435 ice_pcie_lnk_x12 = 0x0C,
436 ice_pcie_lnk_x16 = 0x10,
437 ice_pcie_lnk_x32 = 0x20,
438 ice_pcie_lnk_width_unknown = 0xff,
441 /* Reset types used to determine which kind of reset was requested. These
442 * defines match what the RESET_TYPE field of the GLGEN_RSTAT register.
443 * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register
444 * because its reset source is different than the other types listed.
456 struct ice_bus_info {
457 enum ice_pcie_bus_speed speed;
458 enum ice_pcie_link_width width;
459 enum ice_bus_type type;
466 /* Flow control (FC) parameters */
468 enum ice_fc_mode current_mode; /* FC mode in effect */
469 enum ice_fc_mode req_mode; /* FC mode requested by caller */
472 /* Option ROM version information */
473 struct ice_orom_info {
474 u8 major; /* Major version of OROM */
475 u8 patch; /* Patch version of OROM */
476 u16 build; /* Build version of OROM */
479 /* NVM Information */
480 struct ice_nvm_info {
481 struct ice_orom_info orom; /* Option ROM version info */
482 u32 eetrack; /* NVM data version */
483 u16 sr_words; /* Shadow RAM size in words */
484 u32 flash_size; /* Size of available flash in bytes */
485 u8 major_ver; /* major version of dev starter */
486 u8 minor_ver; /* minor version of dev starter */
487 u8 blank_nvm_mode; /* is NVM empty (no FW present) */
490 struct ice_link_default_override_tlv {
492 #define ICE_LINK_OVERRIDE_OPT_M 0x3F
493 #define ICE_LINK_OVERRIDE_STRICT_MODE BIT(0)
494 #define ICE_LINK_OVERRIDE_EPCT_DIS BIT(1)
495 #define ICE_LINK_OVERRIDE_PORT_DIS BIT(2)
496 #define ICE_LINK_OVERRIDE_EN BIT(3)
497 #define ICE_LINK_OVERRIDE_AUTO_LINK_DIS BIT(4)
498 #define ICE_LINK_OVERRIDE_EEE_EN BIT(5)
500 #define ICE_LINK_OVERRIDE_PHY_CFG_S 8
501 #define ICE_LINK_OVERRIDE_PHY_CFG_M (0xC3 << ICE_LINK_OVERRIDE_PHY_CFG_S)
502 #define ICE_LINK_OVERRIDE_PAUSE_M 0x3
503 #define ICE_LINK_OVERRIDE_LESM_EN BIT(6)
504 #define ICE_LINK_OVERRIDE_AUTO_FEC_EN BIT(7)
506 #define ICE_LINK_OVERRIDE_FEC_OPT_M 0xFF
512 #define ICE_NVM_VER_LEN 32
514 /* netlist version information */
515 struct ice_netlist_ver_info {
516 u32 major; /* major high/low */
517 u32 minor; /* minor high/low */
518 u32 type; /* type high/low */
519 u32 rev; /* revision high/low */
520 u32 hash; /* SHA-1 hash word */
521 u16 cust_ver; /* customer version */
524 /* Max number of port to queue branches w.r.t topology */
525 #define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS
527 #define ice_for_each_traffic_class(_i) \
528 for ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++)
530 /* ICE_DFLT_AGG_ID means that all new VM(s)/VSI node connects
531 * to driver defined policy for default aggregator
533 #define ICE_INVAL_TEID 0xFFFFFFFF
534 #define ICE_DFLT_AGG_ID 0
536 struct ice_sched_node {
537 struct ice_sched_node *parent;
538 struct ice_sched_node *sibling; /* next sibling in the same layer */
539 struct ice_sched_node **children;
540 struct ice_aqc_txsched_elem_data info;
541 u32 agg_id; /* aggregator group ID */
543 u8 in_use; /* suspended or in use */
544 u8 tx_sched_layer; /* Logical Layer (1-9) */
548 #define ICE_SCHED_NODE_OWNER_LAN 0
549 #define ICE_SCHED_NODE_OWNER_AE 1
550 #define ICE_SCHED_NODE_OWNER_RDMA 2
553 /* Access Macros for Tx Sched Elements data */
554 #define ICE_TXSCHED_GET_NODE_TEID(x) LE32_TO_CPU((x)->info.node_teid)
555 #define ICE_TXSCHED_GET_PARENT_TEID(x) LE32_TO_CPU((x)->info.parent_teid)
556 #define ICE_TXSCHED_GET_CIR_RL_ID(x) \
557 LE16_TO_CPU((x)->info.cir_bw.bw_profile_idx)
558 #define ICE_TXSCHED_GET_EIR_RL_ID(x) \
559 LE16_TO_CPU((x)->info.eir_bw.bw_profile_idx)
560 #define ICE_TXSCHED_GET_SRL_ID(x) LE16_TO_CPU((x)->info.srl_id)
561 #define ICE_TXSCHED_GET_CIR_BWALLOC(x) \
562 LE16_TO_CPU((x)->info.cir_bw.bw_alloc)
563 #define ICE_TXSCHED_GET_EIR_BWALLOC(x) \
564 LE16_TO_CPU((x)->info.eir_bw.bw_alloc)
566 struct ice_sched_rl_profile {
567 u32 rate; /* In Kbps */
568 struct ice_aqc_rl_profile_elem info;
571 /* The aggregator type determines if identifier is for a VSI group,
572 * aggregator group, aggregator of queues, or queue group.
575 ICE_AGG_TYPE_UNKNOWN = 0,
577 ICE_AGG_TYPE_AGG, /* aggregator */
583 /* Rate limit types */
586 ICE_MIN_BW, /* for CIR profile */
587 ICE_MAX_BW, /* for EIR profile */
588 ICE_SHARED_BW /* for shared profile */
591 #define ICE_SCHED_MIN_BW 500 /* in Kbps */
592 #define ICE_SCHED_MAX_BW 100000000 /* in Kbps */
593 #define ICE_SCHED_DFLT_BW 0xFFFFFFFF /* unlimited */
594 #define ICE_SCHED_NO_PRIORITY 0
595 #define ICE_SCHED_NO_BW_WT 0
596 #define ICE_SCHED_DFLT_RL_PROF_ID 0
597 #define ICE_SCHED_NO_SHARED_RL_PROF_ID 0xFFFF
598 #define ICE_SCHED_DFLT_BW_WT 4
599 #define ICE_SCHED_INVAL_PROF_ID 0xFFFF
600 #define ICE_SCHED_DFLT_BURST_SIZE (15 * 1024) /* in bytes (15k) */
602 /* Access Macros for Tx Sched RL Profile data */
603 #define ICE_TXSCHED_GET_RL_PROF_ID(p) LE16_TO_CPU((p)->info.profile_id)
604 #define ICE_TXSCHED_GET_RL_MBS(p) LE16_TO_CPU((p)->info.max_burst_size)
605 #define ICE_TXSCHED_GET_RL_MULTIPLIER(p) LE16_TO_CPU((p)->info.rl_multiply)
606 #define ICE_TXSCHED_GET_RL_WAKEUP_MV(p) LE16_TO_CPU((p)->info.wake_up_calc)
607 #define ICE_TXSCHED_GET_RL_ENCODE(p) LE16_TO_CPU((p)->info.rl_encode)
609 /* The following tree example shows the naming conventions followed under
610 * ice_port_info struct for default scheduler tree topology.
614 * (TC0)/ / / / \ \ \ \(TC7) ---> num_branches (range:1- 8)
618 * / |-> num_elements (range:1 - 9)
619 * * | implies num_of_layers
623 * (a) is the last_node_teid(not of type Leaf). A leaf node is created under
624 * (a) as child node where queues get added, add Tx/Rx queue admin commands;
625 * need TEID of (a) to add queues.
628 * -> has 8 branches (one for each TC)
629 * -> First branch (TC0) has 4 elements
631 * -> (a) is the topmost layer node created by firmware on branch 0
633 * Note: Above asterisk tree covers only basic terminology and scenario.
634 * Refer to the documentation for more info.
637 /* Data structure for saving BW information */
645 ICE_BW_TYPE_CNT /* This must be last */
653 struct ice_bw_type_info {
654 ice_declare_bitmap(bw_t_bitmap, ICE_BW_TYPE_CNT);
656 struct ice_bw cir_bw;
657 struct ice_bw eir_bw;
661 /* VSI queue context structure for given TC */
665 /* bw_t_info saves queue BW information */
666 struct ice_bw_type_info bw_t_info;
669 /* VSI type list entry to locate corresponding VSI/aggregator nodes */
670 struct ice_sched_vsi_info {
671 struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS];
672 struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS];
673 u16 max_lanq[ICE_MAX_TRAFFIC_CLASS];
674 /* bw_t_info saves VSI BW information */
675 struct ice_bw_type_info bw_t_info[ICE_MAX_TRAFFIC_CLASS];
678 /* CEE or IEEE 802.1Qaz ETS Configuration data */
679 struct ice_dcb_ets_cfg {
683 u8 prio_table[ICE_MAX_TRAFFIC_CLASS];
684 u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS];
685 u8 tsatable[ICE_MAX_TRAFFIC_CLASS];
688 /* CEE or IEEE 802.1Qaz PFC Configuration data */
689 struct ice_dcb_pfc_cfg {
696 /* CEE or IEEE 802.1Qaz Application Priority data */
697 struct ice_dcb_app_priority_table {
703 #define ICE_MAX_USER_PRIORITY 8
704 #define ICE_DCBX_MAX_APPS 32
705 #define ICE_LLDPDU_SIZE 1500
706 #define ICE_TLV_STATUS_OPER 0x1
707 #define ICE_TLV_STATUS_SYNC 0x2
708 #define ICE_TLV_STATUS_ERR 0x4
709 #define ICE_APP_PROT_ID_FCOE 0x8906
710 #define ICE_APP_PROT_ID_ISCSI 0x0cbc
711 #define ICE_APP_PROT_ID_FIP 0x8914
712 #define ICE_APP_SEL_ETHTYPE 0x1
713 #define ICE_APP_SEL_TCPIP 0x2
714 #define ICE_CEE_APP_SEL_ETHTYPE 0x0
715 #define ICE_CEE_APP_SEL_TCPIP 0x1
717 struct ice_dcbx_cfg {
719 u32 tlv_status; /* CEE mode TLV status */
720 struct ice_dcb_ets_cfg etscfg;
721 struct ice_dcb_ets_cfg etsrec;
722 struct ice_dcb_pfc_cfg pfc;
723 struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS];
725 #define ICE_DCBX_MODE_CEE 0x1
726 #define ICE_DCBX_MODE_IEEE 0x2
728 #define ICE_DCBX_APPS_NON_WILLING 0x1
732 struct ice_dcbx_cfg local_dcbx_cfg; /* Oper/Local Cfg */
733 struct ice_dcbx_cfg desired_dcbx_cfg; /* CEE Desired Cfg */
734 struct ice_dcbx_cfg remote_dcbx_cfg; /* Peer Cfg */
735 u8 dcbx_status : 3; /* see ICE_DCBX_STATUS_DIS */
739 struct ice_port_info {
740 struct ice_sched_node *root; /* Root Node per Port */
741 struct ice_hw *hw; /* back pointer to HW instance */
742 u32 last_node_teid; /* scheduler last node info */
743 u16 sw_id; /* Initial switch ID belongs to port */
746 #define ICE_SCHED_PORT_STATE_INIT 0x0
747 #define ICE_SCHED_PORT_STATE_READY 0x1
749 #define ICE_LPORT_MASK 0xff
750 u16 dflt_tx_vsi_rule_id;
752 u16 dflt_rx_vsi_rule_id;
754 struct ice_fc_info fc;
755 struct ice_mac_info mac;
756 struct ice_phy_info phy;
757 struct ice_lock sched_lock; /* protect access to TXSched tree */
758 struct ice_sched_node *
759 sib_head[ICE_MAX_TRAFFIC_CLASS][ICE_AQC_TOPO_MAX_LEVEL_NUM];
760 /* List contain profile ID(s) and other params per layer */
761 struct LIST_HEAD_TYPE rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM];
762 struct ice_bw_type_info root_node_bw_t_info;
763 struct ice_bw_type_info tc_node_bw_t_info[ICE_MAX_TRAFFIC_CLASS];
764 struct ice_qos_cfg qos_cfg;
768 struct ice_switch_info {
769 struct LIST_HEAD_TYPE vsi_list_map_head;
770 struct ice_sw_recipe *recp_list;
771 u16 prof_res_bm_init;
772 u16 max_used_prof_index;
774 ice_declare_bitmap(prof_res_bm[ICE_MAX_NUM_PROFILES], ICE_MAX_FV_WORDS);
777 /* Port hardware description */
781 struct ice_aqc_layer_props *layer_info;
782 struct ice_port_info *port_info;
783 /* 2D Array for each Tx Sched RL Profile type */
784 struct ice_sched_rl_profile **cir_profiles;
785 struct ice_sched_rl_profile **eir_profiles;
786 struct ice_sched_rl_profile **srl_profiles;
787 /* PSM clock frequency for calculating RL profile params */
789 u64 debug_mask; /* BITMAP for debug mask */
790 enum ice_mac_type mac_type;
795 u16 subsystem_device_id;
796 u16 subsystem_vendor_id;
799 u8 pf_id; /* device profile info */
801 u16 max_burst_size; /* driver sets this value */
803 /* Tx Scheduler values */
804 u8 num_tx_sched_layers;
805 u8 num_tx_sched_phys_layers;
808 u8 sw_entry_point_layer;
809 u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM];
810 struct LIST_HEAD_TYPE agg_list; /* lists all aggregator */
811 struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI];
812 u8 evb_veb; /* true for VEB, false for VEPA */
813 u8 reset_ongoing; /* true if HW is in reset, false otherwise */
814 struct ice_bus_info bus;
815 struct ice_nvm_info nvm;
816 struct ice_hw_dev_caps dev_caps; /* device capabilities */
817 struct ice_hw_func_caps func_caps; /* function capabilities */
818 struct ice_netlist_ver_info netlist_ver; /* netlist version info */
820 struct ice_switch_info *switch_info; /* switch filter lists */
822 /* Control Queue info */
823 struct ice_ctl_q_info adminq;
824 struct ice_ctl_q_info mailboxq;
826 u8 api_branch; /* API branch version */
827 u8 api_maj_ver; /* API major version */
828 u8 api_min_ver; /* API minor version */
829 u8 api_patch; /* API patch version */
830 u8 fw_branch; /* firmware branch version */
831 u8 fw_maj_ver; /* firmware major version */
832 u8 fw_min_ver; /* firmware minor version */
833 u8 fw_patch; /* firmware patch version */
834 u32 fw_build; /* firmware build number */
836 /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL
837 * register. Used for determining the ITR/INTRL granularity during
840 #define ICE_MAX_AGG_BW_200G 0x0
841 #define ICE_MAX_AGG_BW_100G 0X1
842 #define ICE_MAX_AGG_BW_50G 0x2
843 #define ICE_MAX_AGG_BW_25G 0x3
844 /* ITR granularity for different speeds */
845 #define ICE_ITR_GRAN_ABOVE_25 2
846 #define ICE_ITR_GRAN_MAX_25 4
847 /* ITR granularity in 1 us */
849 /* INTRL granularity for different speeds */
850 #define ICE_INTRL_GRAN_ABOVE_25 4
851 #define ICE_INTRL_GRAN_MAX_25 8
852 /* INTRL granularity in 1 us */
855 u8 ucast_shared; /* true if VSIs can share unicast addr */
857 #define ICE_PHY_PER_NAC 1
858 #define ICE_MAX_QUAD 2
859 #define ICE_NUM_QUAD_TYPE 2
860 #define ICE_PORTS_PER_QUAD 4
861 #define ICE_PHY_0_LAST_QUAD 1
862 #define ICE_PORTS_PER_PHY 8
863 #define ICE_NUM_EXTERNAL_PORTS ICE_PORTS_PER_PHY
865 /* Active package version (currently active) */
866 struct ice_pkg_ver active_pkg_ver;
868 u8 active_pkg_name[ICE_PKG_NAME_SIZE];
869 u8 active_pkg_in_nvm;
871 enum ice_aq_err pkg_dwnld_status;
873 /* Driver's package ver - (from the Metadata seg) */
874 struct ice_pkg_ver pkg_ver;
875 u8 pkg_name[ICE_PKG_NAME_SIZE];
877 /* Driver's Ice package version (from the Ice seg) */
878 struct ice_pkg_ver ice_pkg_ver;
879 u8 ice_pkg_name[ICE_PKG_NAME_SIZE];
881 /* Pointer to the ice segment */
884 /* Pointer to allocated copy of pkg memory */
889 struct ice_lock tnl_lock;
890 struct ice_tunnel_table tnl;
892 /* HW block tables */
893 struct ice_blk_info blk[ICE_BLK_COUNT];
894 struct ice_lock fl_profs_locks[ICE_BLK_COUNT]; /* lock fltr profiles */
895 struct LIST_HEAD_TYPE fl_profs[ICE_BLK_COUNT];
896 struct ice_lock rss_locks; /* protect RSS configuration */
897 struct LIST_HEAD_TYPE rss_list_head;
900 /* Statistics collected by each port, VSI, VEB, and S-channel */
901 struct ice_eth_stats {
902 u64 rx_bytes; /* gorc */
903 u64 rx_unicast; /* uprc */
904 u64 rx_multicast; /* mprc */
905 u64 rx_broadcast; /* bprc */
906 u64 rx_discards; /* rdpc */
907 u64 rx_unknown_protocol; /* rupp */
908 u64 tx_bytes; /* gotc */
909 u64 tx_unicast; /* uptc */
910 u64 tx_multicast; /* mptc */
911 u64 tx_broadcast; /* bptc */
912 u64 tx_discards; /* tdpc */
913 u64 tx_errors; /* tepc */
914 u64 rx_no_desc; /* repc */
915 u64 rx_errors; /* repc */
920 /* Statistics collected per VEB per User Priority (UP) for up to 8 UPs */
921 struct ice_veb_up_stats {
922 u64 up_rx_pkts[ICE_MAX_UP];
923 u64 up_rx_bytes[ICE_MAX_UP];
924 u64 up_tx_pkts[ICE_MAX_UP];
925 u64 up_tx_bytes[ICE_MAX_UP];
928 /* Statistics collected by the MAC */
929 struct ice_hw_port_stats {
930 /* eth stats collected by the port */
931 struct ice_eth_stats eth;
932 /* additional port specific stats */
933 u64 tx_dropped_link_down; /* tdold */
934 u64 crc_errors; /* crcerrs */
935 u64 illegal_bytes; /* illerrc */
936 u64 error_bytes; /* errbc */
937 u64 mac_local_faults; /* mlfc */
938 u64 mac_remote_faults; /* mrfc */
939 u64 rx_len_errors; /* rlec */
940 u64 link_xon_rx; /* lxonrxc */
941 u64 link_xoff_rx; /* lxoffrxc */
942 u64 link_xon_tx; /* lxontxc */
943 u64 link_xoff_tx; /* lxofftxc */
944 u64 priority_xon_rx[8]; /* pxonrxc[8] */
945 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
946 u64 priority_xon_tx[8]; /* pxontxc[8] */
947 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
948 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
949 u64 rx_size_64; /* prc64 */
950 u64 rx_size_127; /* prc127 */
951 u64 rx_size_255; /* prc255 */
952 u64 rx_size_511; /* prc511 */
953 u64 rx_size_1023; /* prc1023 */
954 u64 rx_size_1522; /* prc1522 */
955 u64 rx_size_big; /* prc9522 */
956 u64 rx_undersize; /* ruc */
957 u64 rx_fragments; /* rfc */
958 u64 rx_oversize; /* roc */
959 u64 rx_jabber; /* rjc */
960 u64 tx_size_64; /* ptc64 */
961 u64 tx_size_127; /* ptc127 */
962 u64 tx_size_255; /* ptc255 */
963 u64 tx_size_511; /* ptc511 */
964 u64 tx_size_1023; /* ptc1023 */
965 u64 tx_size_1522; /* ptc1522 */
966 u64 tx_size_big; /* ptc9522 */
967 u64 mac_short_pkt_dropped; /* mspdc */
971 u64 tx_lpi_count; /* etlpic */
972 u64 rx_lpi_count; /* erlpic */
975 enum ice_sw_fwd_act_type {
977 ICE_FWD_TO_VSI_LIST, /* Do not use this when adding filter */
984 /* Checksum and Shadow RAM pointers */
985 #define ICE_SR_NVM_CTRL_WORD 0x00
986 #define ICE_SR_PHY_ANALOG_PTR 0x04
987 #define ICE_SR_OPTION_ROM_PTR 0x05
988 #define ICE_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06
989 #define ICE_SR_AUTO_GENERATED_POINTERS_PTR 0x07
990 #define ICE_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08
991 #define ICE_SR_EMP_GLOBAL_MODULE_PTR 0x09
992 #define ICE_SR_EMP_IMAGE_PTR 0x0B
993 #define ICE_SR_PE_IMAGE_PTR 0x0C
994 #define ICE_SR_CSR_PROTECTED_LIST_PTR 0x0D
995 #define ICE_SR_MNG_CFG_PTR 0x0E
996 #define ICE_SR_EMP_MODULE_PTR 0x0F
997 #define ICE_SR_PBA_BLOCK_PTR 0x16
998 #define ICE_SR_BOOT_CFG_PTR 0x132
999 #define ICE_SR_NVM_WOL_CFG 0x19
1000 #define ICE_NVM_OROM_VER_OFF 0x02
1001 #define ICE_SR_NVM_DEV_STARTER_VER 0x18
1002 #define ICE_SR_ALTERNATE_SAN_MAC_ADDR_PTR 0x27
1003 #define ICE_SR_PERMANENT_SAN_MAC_ADDR_PTR 0x28
1004 #define ICE_SR_NVM_MAP_VER 0x29
1005 #define ICE_SR_NVM_IMAGE_VER 0x2A
1006 #define ICE_SR_NVM_STRUCTURE_VER 0x2B
1007 #define ICE_SR_NVM_EETRACK_LO 0x2D
1008 #define ICE_SR_NVM_EETRACK_HI 0x2E
1009 #define ICE_NVM_VER_LO_SHIFT 0
1010 #define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT)
1011 #define ICE_NVM_VER_HI_SHIFT 12
1012 #define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT)
1013 #define ICE_OEM_EETRACK_ID 0xffffffff
1014 #define ICE_OROM_VER_PATCH_SHIFT 0
1015 #define ICE_OROM_VER_PATCH_MASK (0xff << ICE_OROM_VER_PATCH_SHIFT)
1016 #define ICE_OROM_VER_BUILD_SHIFT 8
1017 #define ICE_OROM_VER_BUILD_MASK (0xffff << ICE_OROM_VER_BUILD_SHIFT)
1018 #define ICE_OROM_VER_SHIFT 24
1019 #define ICE_OROM_VER_MASK (0xff << ICE_OROM_VER_SHIFT)
1020 #define ICE_SR_VPD_PTR 0x2F
1021 #define ICE_SR_PXE_SETUP_PTR 0x30
1022 #define ICE_SR_PXE_CFG_CUST_OPTIONS_PTR 0x31
1023 #define ICE_SR_NVM_ORIGINAL_EETRACK_LO 0x34
1024 #define ICE_SR_NVM_ORIGINAL_EETRACK_HI 0x35
1025 #define ICE_SR_VLAN_CFG_PTR 0x37
1026 #define ICE_SR_POR_REGS_AUTO_LOAD_PTR 0x38
1027 #define ICE_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A
1028 #define ICE_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B
1029 #define ICE_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C
1030 #define ICE_SR_PHY_CFG_SCRIPT_PTR 0x3D
1031 #define ICE_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1032 #define ICE_SR_SW_CHECKSUM_WORD 0x3F
1033 #define ICE_SR_PFA_PTR 0x40
1034 #define ICE_SR_1ST_SCRATCH_PAD_PTR 0x41
1035 #define ICE_SR_1ST_NVM_BANK_PTR 0x42
1036 #define ICE_SR_NVM_BANK_SIZE 0x43
1037 #define ICE_SR_1ST_OROM_BANK_PTR 0x44
1038 #define ICE_SR_OROM_BANK_SIZE 0x45
1039 #define ICE_SR_NETLIST_BANK_PTR 0x46
1040 #define ICE_SR_NETLIST_BANK_SIZE 0x47
1041 #define ICE_SR_EMP_SR_SETTINGS_PTR 0x48
1042 #define ICE_SR_CONFIGURATION_METADATA_PTR 0x4D
1043 #define ICE_SR_IMMEDIATE_VALUES_PTR 0x4E
1044 #define ICE_SR_LINK_DEFAULT_OVERRIDE_PTR 0x134
1045 #define ICE_SR_POR_REGISTERS_AUTOLOAD_PTR 0x118
1047 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1048 #define ICE_SR_VPD_SIZE_WORDS 512
1049 #define ICE_SR_PCIE_ALT_SIZE_WORDS 512
1050 #define ICE_SR_CTRL_WORD_1_S 0x06
1051 #define ICE_SR_CTRL_WORD_1_M (0x03 << ICE_SR_CTRL_WORD_1_S)
1053 /* Shadow RAM related */
1054 #define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800
1055 #define ICE_SR_BUF_ALIGNMENT 4096
1056 #define ICE_SR_WORDS_IN_1KB 512
1057 /* Checksum should be calculated such that after adding all the words,
1058 * including the checksum word itself, the sum should be 0xBABA.
1060 #define ICE_SR_SW_CHECKSUM_BASE 0xBABA
1062 /* Link override related */
1063 #define ICE_SR_PFA_LINK_OVERRIDE_WORDS 10
1064 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS 4
1065 #define ICE_SR_PFA_LINK_OVERRIDE_OFFSET 2
1066 #define ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET 1
1067 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET 2
1068 #define ICE_FW_API_LINK_OVERRIDE_MAJ 1
1069 #define ICE_FW_API_LINK_OVERRIDE_MIN 5
1070 #define ICE_FW_API_LINK_OVERRIDE_PATCH 2
1072 #define ICE_PBA_FLAG_DFLT 0xFAFA
1073 /* Hash redirection LUT for VSI - maximum array size */
1074 #define ICE_VSIQF_HLUT_ARRAY_SIZE ((VSIQF_HLUT_MAX_INDEX + 1) * 4)
1077 * Defines for values in the VF_PE_DB_SIZE bits in the GLPCI_LBARCTRL register.
1078 * This is needed to determine the BAR0 space for the VFs
1080 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_0KB 0x0
1081 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_8KB 0x1
1082 #define GLPCI_LBARCTRL_VF_PE_DB_SIZE_64KB 0x2
1084 /* AQ API version for LLDP_FILTER_CONTROL */
1085 #define ICE_FW_API_LLDP_FLTR_MAJ 1
1086 #define ICE_FW_API_LLDP_FLTR_MIN 7
1087 #define ICE_FW_API_LLDP_FLTR_PATCH 1
1088 #endif /* _ICE_TYPE_H_ */