sys/dev/ichiic/ig4_iic.c

   1 /*
   2  * Copyright (c) 2014 The DragonFly Project.  All rights reserved.
   3  *
   4  * This code is derived from software contributed to The DragonFly Project
   5  * by Matthew Dillon <dillon@backplane.com> and was subsequently ported
   6  * to FreeBSD by Michael Gmelin <freebsd@grem.de>
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  *
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in
  16  *    the documentation and/or other materials provided with the
  17  *    distribution.
  18  * 3. Neither the name of The DragonFly Project nor the names of its
  19  *    contributors may be used to endorse or promote products derived
  20  *    from this software without specific, prior written permission.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  23  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  24  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  25  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
  26  * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  27  * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
  28  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  30  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  31  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  32  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  33  * SUCH DAMAGE.
  34  */
  35
  36 #include <sys/cdefs.h>
  37 __FBSDID("$FreeBSD$");
  38
  39 /*
  40  * Intel fourth generation mobile cpus integrated I2C device.
  41  *
  42  * See ig4_reg.h for datasheet reference and notes.
  43  * See ig4_var.h for locking semantics.
  44  */
  45
  46 #include "opt_acpi.h"
  47
  48 #include <sys/param.h>
  49 #include <sys/systm.h>
  50 #include <sys/kernel.h>
  51 #include <sys/module.h>
  52 #include <sys/errno.h>
  53 #include <sys/kdb.h>
  54 #include <sys/lock.h>
  55 #include <sys/mutex.h>
  56 #include <sys/proc.h>
  57 #include <sys/sx.h>
  58 #include <sys/syslog.h>
  59 #include <sys/bus.h>
  60 #include <sys/sysctl.h>
  61
  62 #include <machine/bus.h>
  63 #include <sys/rman.h>
  64
  65 #ifdef DEV_ACPI
  66 #include <contrib/dev/acpica/include/acpi.h>
  67 #include <contrib/dev/acpica/include/accommon.h>
  68 #include <dev/acpica/acpivar.h>
  69 #endif
  70
  71 #include <dev/iicbus/iicbus.h>
  72 #include <dev/iicbus/iiconf.h>
  73
  74 #include <dev/ichiic/ig4_reg.h>
  75 #include <dev/ichiic/ig4_var.h>
  76
  77 #define DO_POLL(sc)     (cold || kdb_active || SCHEDULER_STOPPED() || sc->poll)
  78
  79 /*
  80  * tLOW, tHIGH periods of the SCL clock and maximal falling time of both
  81  * lines are taken from I2C specifications.
  82  */
  83 #define IG4_SPEED_STD_THIGH     4000    /* nsec */
  84 #define IG4_SPEED_STD_TLOW      4700    /* nsec */
  85 #define IG4_SPEED_STD_TF_MAX    300     /* nsec */
  86 #define IG4_SPEED_FAST_THIGH    600     /* nsec */
  87 #define IG4_SPEED_FAST_TLOW     1300    /* nsec */
  88 #define IG4_SPEED_FAST_TF_MAX   300     /* nsec */
  89
  90 /*
  91  * Ig4 hardware parameters except Haswell are taken from intel_lpss driver
  92  */
  93 static const struct ig4_hw ig4iic_hw[] = {
  94         [IG4_HASWELL] = {
  95                 .ic_clock_rate = 100,   /* MHz */
  96                 .sda_hold_time = 90,    /* nsec */
  97                 .txfifo_depth = 32,
  98                 .rxfifo_depth = 32,
  99         },
 100         [IG4_ATOM] = {
 101                 .ic_clock_rate = 100,
 102                 .sda_fall_time = 280,
 103                 .scl_fall_time = 240,
 104                 .sda_hold_time = 60,
 105                 .txfifo_depth = 32,
 106                 .rxfifo_depth = 32,
 107         },
 108         [IG4_SKYLAKE] = {
 109                 .ic_clock_rate = 120,
 110                 .sda_hold_time = 230,
 111         },
 112         [IG4_APL] = {
 113                 .ic_clock_rate = 133,
 114                 .sda_fall_time = 171,
 115                 .scl_fall_time = 208,
 116                 .sda_hold_time = 207,
 117         },
 118         [IG4_CANNONLAKE] = {
 119                 .ic_clock_rate = 216,
 120                 .sda_hold_time = 230,
 121         },
 122         [IG4_TIGERLAKE] = {
 123                 .ic_clock_rate = 133,
 124                 .sda_fall_time = 171,
 125                 .scl_fall_time = 208,
 126                 .sda_hold_time = 42,
 127         },
 128 };
 129
 130 static int ig4iic_set_config(ig4iic_softc_t *sc, bool reset);
 131 static driver_filter_t ig4iic_intr;
 132 static void ig4iic_dump(ig4iic_softc_t *sc);
 133
 134 static int ig4_dump;
 135 SYSCTL_INT(_debug, OID_AUTO, ig4_dump, CTLFLAG_RW,
 136            &ig4_dump, 0, "Dump controller registers");
 137
 138 /*
 139  * Clock registers initialization control
 140  * 0 - Try read clock registers from ACPI and fallback to p.1.
 141  * 1 - Calculate values based on controller type (IC clock rate).
 142  * 2 - Use values inherited from DragonflyBSD driver (old behavior).
 143  * 3 - Keep clock registers intact.
 144  */
 145 static int ig4_timings;
 146 SYSCTL_INT(_debug, OID_AUTO, ig4_timings, CTLFLAG_RDTUN, &ig4_timings, 0,
 147     "Controller timings 0=ACPI, 1=predefined, 2=legacy, 3=do not change");
 148
 149 /*
 150  * Low-level inline support functions
 151  */
 152 static __inline void
 153 reg_write(ig4iic_softc_t *sc, uint32_t reg, uint32_t value)
 154 {
 155         bus_write_4(sc->regs_res, reg, value);
 156         bus_barrier(sc->regs_res, reg, 4, BUS_SPACE_BARRIER_WRITE);
 157 }
 158
 159 static __inline uint32_t
 160 reg_read(ig4iic_softc_t *sc, uint32_t reg)
 161 {
 162         uint32_t value;
 163
 164         bus_barrier(sc->regs_res, reg, 4, BUS_SPACE_BARRIER_READ);
 165         value = bus_read_4(sc->regs_res, reg);
 166         return (value);
 167 }
 168
 169 static void
 170 ig4iic_set_intr_mask(ig4iic_softc_t *sc, uint32_t val)
 171 {
 172         if (sc->intr_mask != val) {
 173                 reg_write(sc, IG4_REG_INTR_MASK, val);
 174                 sc->intr_mask = val;
 175         }
 176 }
 177
 178 static int
 179 intrstat2iic(ig4iic_softc_t *sc, uint32_t val)
 180 {
 181         uint32_t src;
 182
 183         if (val & IG4_INTR_RX_UNDER)
 184                 reg_read(sc, IG4_REG_CLR_RX_UNDER);
 185         if (val & IG4_INTR_RX_OVER)
 186                 reg_read(sc, IG4_REG_CLR_RX_OVER);
 187         if (val & IG4_INTR_TX_OVER)
 188                 reg_read(sc, IG4_REG_CLR_TX_OVER);
 189
 190         if (val & IG4_INTR_TX_ABRT) {
 191                 src = reg_read(sc, IG4_REG_TX_ABRT_SOURCE);
 192                 reg_read(sc, IG4_REG_CLR_TX_ABORT);
 193                 /* User-requested abort. Not really a error */
 194                 if (src & IG4_ABRTSRC_TRANSFER)
 195                         return (IIC_ESTATUS);
 196                 /* Master has lost arbitration */
 197                 if (src & IG4_ABRTSRC_ARBLOST)
 198                         return (IIC_EBUSBSY);
 199                 /* Did not receive an acknowledge from the remote slave */
 200                 if (src & (IG4_ABRTSRC_TXNOACK_ADDR7 |
 201                            IG4_ABRTSRC_TXNOACK_ADDR10_1 |
 202                            IG4_ABRTSRC_TXNOACK_ADDR10_2 |
 203                            IG4_ABRTSRC_TXNOACK_DATA |
 204                            IG4_ABRTSRC_GENCALL_NOACK))
 205                         return (IIC_ENOACK);
 206                 /* Programming errors */
 207                 if (src & (IG4_ABRTSRC_GENCALL_READ |
 208                            IG4_ABRTSRC_NORESTART_START |
 209                            IG4_ABRTSRC_NORESTART_10))
 210                         return (IIC_ENOTSUPP);
 211                 /* Other errors */
 212                 if (src & IG4_ABRTSRC_ACKED_START)
 213                         return (IIC_EBUSERR);
 214         }
 215         /*
 216          * TX_OVER, RX_OVER and RX_UNDER are caused by wrong RX/TX FIFO depth
 217          * detection or driver's read/write pipelining errors.
 218          */
 219         if (val & (IG4_INTR_TX_OVER | IG4_INTR_RX_OVER))
 220                 return (IIC_EOVERFLOW);
 221         if (val & IG4_INTR_RX_UNDER)
 222                 return (IIC_EUNDERFLOW);
 223
 224         return (IIC_NOERR);
 225 }
 226
 227 /*
 228  * Enable or disable the controller and wait for the controller to acknowledge
 229  * the state change.
 230  */
 231 static int
 232 set_controller(ig4iic_softc_t *sc, uint32_t ctl)
 233 {
 234         int retry;
 235         int error;
 236         uint32_t v;
 237
 238         /*
 239          * When the controller is enabled, interrupt on STOP detect
 240          * or receive character ready and clear pending interrupts.
 241          */
 242         ig4iic_set_intr_mask(sc, 0);
 243         if (ctl & IG4_I2C_ENABLE)
 244                 reg_read(sc, IG4_REG_CLR_INTR);
 245
 246         reg_write(sc, IG4_REG_I2C_EN, ctl);
 247         error = IIC_ETIMEOUT;
 248
 249         for (retry = 100; retry > 0; --retry) {
 250                 v = reg_read(sc, IG4_REG_ENABLE_STATUS);
 251                 if (((v ^ ctl) & IG4_I2C_ENABLE) == 0) {
 252                         error = 0;
 253                         break;
 254                 }
 255                 pause("i2cslv", 1);
 256         }
 257         return (error);
 258 }
 259
 260 /*
 261  * Wait up to 25ms for the requested interrupt using a 25uS polling loop.
 262  */
 263 static int
 264 wait_intr(ig4iic_softc_t *sc, uint32_t intr)
 265 {
 266         uint32_t v;
 267         int error;
 268         int txlvl = -1;
 269         u_int count_us = 0;
 270         u_int limit_us = 25000; /* 25ms */
 271
 272         for (;;) {
 273                 /*
 274                  * Check requested status
 275                  */
 276                 v = reg_read(sc, IG4_REG_RAW_INTR_STAT);
 277                 error = intrstat2iic(sc, v & IG4_INTR_ERR_MASK);
 278                 if (error || (v & intr))
 279                         break;
 280
 281                 /*
 282                  * When waiting for the transmit FIFO to become empty,
 283                  * reset the timeout if we see a change in the transmit
 284                  * FIFO level as progress is being made.
 285                  */
 286                 if (intr & (IG4_INTR_TX_EMPTY | IG4_INTR_STOP_DET)) {
 287                         v = reg_read(sc, IG4_REG_TXFLR) & IG4_FIFOLVL_MASK;
 288                         if (txlvl != v) {
 289                                 txlvl = v;
 290                                 count_us = 0;
 291                         }
 292                 }
 293
 294                 /*
 295                  * Stop if we've run out of time.
 296                  */
 297                 if (count_us >= limit_us) {
 298                         error = IIC_ETIMEOUT;
 299                         break;
 300                 }
 301
 302                 /*
 303                  * When polling is not requested let the interrupt do its work.
 304                  */
 305                 if (!DO_POLL(sc)) {
 306                         mtx_lock_spin(&sc->io_lock);
 307                         ig4iic_set_intr_mask(sc, intr | IG4_INTR_ERR_MASK);
 308                         msleep_spin(sc, &sc->io_lock, "i2cwait",
 309                                   (hz + 99) / 100); /* sleep up to 10ms */
 310                         ig4iic_set_intr_mask(sc, 0);
 311                         mtx_unlock_spin(&sc->io_lock);
 312                         count_us += 10000;
 313                 } else {
 314                         DELAY(25);
 315                         count_us += 25;
 316                 }
 317         }
 318
 319         return (error);
 320 }
 321
 322 /*
 323  * Set the slave address.  The controller must be disabled when
 324  * changing the address.
 325  *
 326  * This operation does not issue anything to the I2C bus but sets
 327  * the target address for when the controller later issues a START.
 328  */
 329 static void
 330 set_slave_addr(ig4iic_softc_t *sc, uint8_t slave)
 331 {
 332         uint32_t tar;
 333         uint32_t ctl;
 334         int use_10bit;
 335
 336         use_10bit = 0;
 337         if (sc->slave_valid && sc->last_slave == slave &&
 338             sc->use_10bit == use_10bit) {
 339                 return;
 340         }
 341         sc->use_10bit = use_10bit;
 342
 343         /*
 344          * Wait for TXFIFO to drain before disabling the controller.
 345          */
 346         wait_intr(sc, IG4_INTR_TX_EMPTY);
 347
 348         set_controller(sc, 0);
 349         ctl = reg_read(sc, IG4_REG_CTL);
 350         ctl &= ~IG4_CTL_10BIT;
 351         ctl |= IG4_CTL_RESTARTEN;
 352
 353         tar = slave;
 354         if (sc->use_10bit) {
 355                 tar |= IG4_TAR_10BIT;
 356                 ctl |= IG4_CTL_10BIT;
 357         }
 358         reg_write(sc, IG4_REG_CTL, ctl);
 359         reg_write(sc, IG4_REG_TAR_ADD, tar);
 360         set_controller(sc, IG4_I2C_ENABLE);
 361         sc->slave_valid = 1;
 362         sc->last_slave = slave;
 363 }
 364
 365 /*
 366  *                              IICBUS API FUNCTIONS
 367  */
 368 static int
 369 ig4iic_xfer_start(ig4iic_softc_t *sc, uint16_t slave, bool repeated_start)
 370 {
 371         set_slave_addr(sc, slave >> 1);
 372
 373         if (!repeated_start) {
 374                 /*
 375                  * Clear any previous TX/RX FIFOs overflow/underflow bits
 376                  * and I2C bus STOP condition.
 377                  */
 378                 reg_read(sc, IG4_REG_CLR_INTR);
 379         }
 380
 381         return (0);
 382 }
 383
 384 static bool
 385 ig4iic_xfer_is_started(ig4iic_softc_t *sc)
 386 {
 387         /*
 388          * It requires that no IG4_REG_CLR_INTR or IG4_REG_CLR_START/STOP_DET
 389          * register reads is issued after START condition.
 390          */
 391         return ((reg_read(sc, IG4_REG_RAW_INTR_STAT) &
 392             (IG4_INTR_START_DET | IG4_INTR_STOP_DET)) == IG4_INTR_START_DET);
 393 }
 394
 395 static int
 396 ig4iic_xfer_abort(ig4iic_softc_t *sc)
 397 {
 398         int error;
 399
 400         /* Request send of STOP condition and flush of TX FIFO */
 401         set_controller(sc, IG4_I2C_ABORT | IG4_I2C_ENABLE);
 402         /*
 403          * Wait for the TX_ABRT interrupt with ABRTSRC_TRANSFER
 404          * bit set in TX_ABRT_SOURCE register.
 405          */
 406         error = wait_intr(sc, IG4_INTR_STOP_DET);
 407         set_controller(sc, IG4_I2C_ENABLE);
 408
 409         return (error == IIC_ESTATUS ? 0 : error);
 410 }
 411
 412 /*
 413  * Amount of unread data before next burst to get better I2C bus utilization.
 414  * 2 bytes is enough in FAST mode. 8 bytes is better in FAST+ and HIGH modes.
 415  * Intel-recommended value is 16 for DMA transfers with 64-byte depth FIFOs.
 416  */
 417 #define IG4_FIFO_LOWAT  2
 418
 419 static int
 420 ig4iic_read(ig4iic_softc_t *sc, uint8_t *buf, uint16_t len,
 421     bool repeated_start, bool stop)
 422 {
 423         uint32_t cmd;
 424         int requested = 0;
 425         int received = 0;
 426         int burst, target, lowat = 0;
 427         int error;
 428
 429         if (len == 0)
 430                 return (0);
 431
 432         while (received < len) {
 433                 burst = sc->cfg.txfifo_depth -
 434                     (reg_read(sc, IG4_REG_TXFLR) & IG4_FIFOLVL_MASK);
 435                 if (burst <= 0) {
 436                         error = wait_intr(sc, IG4_INTR_TX_EMPTY);
 437                         if (error)
 438                                 break;
 439                         burst = sc->cfg.txfifo_depth;
 440                 }
 441                 /* Ensure we have enough free space in RXFIFO */
 442                 burst = MIN(burst, sc->cfg.rxfifo_depth - lowat);
 443                 target = MIN(requested + burst, (int)len);
 444                 while (requested < target) {
 445                         cmd = IG4_DATA_COMMAND_RD;
 446                         if (repeated_start && requested == 0)
 447                                 cmd |= IG4_DATA_RESTART;
 448                         if (stop && requested == len - 1)
 449                                 cmd |= IG4_DATA_STOP;
 450                         reg_write(sc, IG4_REG_DATA_CMD, cmd);
 451                         requested++;
 452                 }
 453                 /* Leave some data queued to maintain the hardware pipeline */
 454                 lowat = 0;
 455                 if (requested != len && requested - received > IG4_FIFO_LOWAT)
 456                         lowat = IG4_FIFO_LOWAT;
 457                 /* After TXFLR fills up, clear it by reading available data */
 458                 while (received < requested - lowat) {
 459                         burst = MIN((int)len - received,
 460                             reg_read(sc, IG4_REG_RXFLR) & IG4_FIFOLVL_MASK);
 461                         if (burst > 0) {
 462                                 while (burst--)
 463                                         buf[received++] = 0xFF &
 464                                             reg_read(sc, IG4_REG_DATA_CMD);
 465                         } else {
 466                                 error = wait_intr(sc, IG4_INTR_RX_FULL);
 467                                 if (error)
 468                                         goto out;
 469                         }
 470                 }
 471         }
 472 out:
 473         return (error);
 474 }
 475
 476 static int
 477 ig4iic_write(ig4iic_softc_t *sc, uint8_t *buf, uint16_t len,
 478     bool repeated_start, bool stop)
 479 {
 480         uint32_t cmd;
 481         int sent = 0;
 482         int burst, target;
 483         int error;
 484         bool lowat_set = false;
 485
 486         if (len == 0)
 487                 return (0);
 488
 489         while (sent < len) {
 490                 burst = sc->cfg.txfifo_depth -
 491                     (reg_read(sc, IG4_REG_TXFLR) & IG4_FIFOLVL_MASK);
 492                 target = MIN(sent + burst, (int)len);
 493                 /* Leave some data queued to maintain the hardware pipeline */
 494                 if (!lowat_set && target != len) {
 495                         lowat_set = true;
 496                         reg_write(sc, IG4_REG_TX_TL, IG4_FIFO_LOWAT);
 497                 }
 498                 while(sent < target) {
 499                         cmd = buf[sent];
 500                         if (repeated_start && sent == 0)
 501                                 cmd |= IG4_DATA_RESTART;
 502                         if (stop && sent == len - 1)
 503                                 cmd |= IG4_DATA_STOP;
 504                         reg_write(sc, IG4_REG_DATA_CMD, cmd);
 505                         sent++;
 506                 }
 507                 if (sent < len) {
 508                         error = wait_intr(sc, IG4_INTR_TX_EMPTY);
 509                         if (error)
 510                                 break;
 511                 }
 512         }
 513         if (lowat_set)
 514                 reg_write(sc, IG4_REG_TX_TL, 0);
 515
 516         return (error);
 517 }
 518
 519 int
 520 ig4iic_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
 521 {
 522         ig4iic_softc_t *sc = device_get_softc(dev);
 523         const char *reason = NULL;
 524         uint32_t i;
 525         int error;
 526         int unit;
 527         bool rpstart;
 528         bool stop;
 529         bool allocated;
 530
 531         /*
 532          * The hardware interface imposes limits on allowed I2C messages.
 533          * It is not possible to explicitly send a start or stop.
 534          * They are automatically sent (or not sent, depending on the
 535          * configuration) when a data byte is transferred.
 536          * For this reason it's impossible to send a message with no data
 537          * at all (like an SMBus quick message).
 538          * The start condition is automatically generated after the stop
 539          * condition, so it's impossible to not have a start after a stop.
 540          * The repeated start condition is automatically sent if a change
 541          * of the transfer direction happens, so it's impossible to have
 542          * a change of direction without a (repeated) start.
 543          * The repeated start can be forced even without the change of
 544          * direction.
 545          * Changing the target slave address requires resetting the hardware
 546          * state, so it's impossible to do that without the stop followed
 547          * by the start.
 548          */
 549         for (i = 0; i < nmsgs; i++) {
 550 #if 0
 551                 if (i == 0 && (msgs[i].flags & IIC_M_NOSTART) != 0) {
 552                         reason = "first message without start";
 553                         break;
 554                 }
 555                 if (i == nmsgs - 1 && (msgs[i].flags & IIC_M_NOSTOP) != 0) {
 556                         reason = "last message without stop";
 557                         break;
 558                 }
 559 #endif
 560                 if (msgs[i].len == 0) {
 561                         reason = "message with no data";
 562                         break;
 563                 }
 564                 if (i > 0) {
 565                         if ((msgs[i].flags & IIC_M_NOSTART) != 0 &&
 566                             (msgs[i - 1].flags & IIC_M_NOSTOP) == 0) {
 567                                 reason = "stop not followed by start";
 568                                 break;
 569                         }
 570                         if ((msgs[i - 1].flags & IIC_M_NOSTOP) != 0 &&
 571                             msgs[i].slave != msgs[i - 1].slave) {
 572                                 reason = "change of slave without stop";
 573                                 break;
 574                         }
 575                         if ((msgs[i].flags & IIC_M_NOSTART) != 0 &&
 576                             (msgs[i].flags & IIC_M_RD) !=
 577                             (msgs[i - 1].flags & IIC_M_RD)) {
 578                                 reason = "change of direction without repeated"
 579                                     " start";
 580                                 break;
 581                         }
 582                 }
 583         }
 584         if (reason != NULL) {
 585                 if (bootverbose)
 586                         device_printf(dev, "%s\n", reason);
 587                 return (IIC_ENOTSUPP);
 588         }
 589
 590         /* Check if device is already allocated with iicbus_request_bus() */
 591         allocated = sx_xlocked(&sc->call_lock) != 0;
 592         if (!allocated)
 593                 sx_xlock(&sc->call_lock);
 594
 595         /* Debugging - dump registers. */
 596         if (ig4_dump) {
 597                 unit = device_get_unit(dev);
 598                 if (ig4_dump & (1 << unit)) {
 599                         ig4_dump &= ~(1 << unit);
 600                         ig4iic_dump(sc);
 601                 }
 602         }
 603
 604         /*
 605          * Clear any previous abort condition that may have been holding
 606          * the txfifo in reset.
 607          */
 608         reg_read(sc, IG4_REG_CLR_TX_ABORT);
 609
 610         rpstart = false;
 611         error = 0;
 612         for (i = 0; i < nmsgs; i++) {
 613                 if ((msgs[i].flags & IIC_M_NOSTART) == 0) {
 614                         error = ig4iic_xfer_start(sc, msgs[i].slave, rpstart);
 615                 } else {
 616                         if (!sc->slave_valid ||
 617                             (msgs[i].slave >> 1) != sc->last_slave) {
 618                                 device_printf(dev, "start condition suppressed"
 619                                     "but slave address is not set up");
 620                                 error = EINVAL;
 621                                 break;
 622                         }
 623                         rpstart = false;
 624                 }
 625                 if (error != 0)
 626                         break;
 627
 628                 stop = (msgs[i].flags & IIC_M_NOSTOP) == 0;
 629                 if (msgs[i].flags & IIC_M_RD)
 630                         error = ig4iic_read(sc, msgs[i].buf, msgs[i].len,
 631                             rpstart, stop);
 632                 else
 633                         error = ig4iic_write(sc, msgs[i].buf, msgs[i].len,
 634                             rpstart, stop);
 635
 636                 /* Wait for error or stop condition occurred on the I2C bus */
 637                 if (stop && error == 0) {
 638                         error = wait_intr(sc, IG4_INTR_STOP_DET);
 639                         if (error == 0)
 640                                 reg_read(sc, IG4_REG_CLR_INTR);
 641                 }
 642
 643                 if (error != 0) {
 644                         /*
 645                          * Send STOP condition if it's not done yet and flush
 646                          * both FIFOs. Do a controller soft reset if transfer
 647                          * abort is failed.
 648                          */
 649                         if (ig4iic_xfer_is_started(sc) &&
 650                             ig4iic_xfer_abort(sc) != 0) {
 651                                 device_printf(sc->dev, "Failed to abort "
 652                                     "transfer. Do the controller reset.\n");
 653                                 ig4iic_set_config(sc, true);
 654                         } else {
 655                                 while (reg_read(sc, IG4_REG_I2C_STA) &
 656                                     IG4_STATUS_RX_NOTEMPTY)
 657                                         reg_read(sc, IG4_REG_DATA_CMD);
 658                                 reg_read(sc, IG4_REG_TX_ABRT_SOURCE);
 659                                 reg_read(sc, IG4_REG_CLR_INTR);
 660                         }
 661                         break;
 662                 }
 663
 664                 rpstart = !stop;
 665         }
 666
 667         if (!allocated)
 668                 sx_unlock(&sc->call_lock);
 669         return (error);
 670 }
 671
 672 int
 673 ig4iic_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
 674 {
 675         ig4iic_softc_t *sc = device_get_softc(dev);
 676         bool allocated;
 677
 678         allocated = sx_xlocked(&sc->call_lock) != 0;
 679         if (!allocated)
 680                 sx_xlock(&sc->call_lock);
 681
 682         /* TODO handle speed configuration? */
 683         if (oldaddr != NULL)
 684                 *oldaddr = sc->last_slave << 1;
 685         set_slave_addr(sc, addr >> 1);
 686         if (addr == IIC_UNKNOWN)
 687                 sc->slave_valid = false;
 688
 689         if (!allocated)
 690                 sx_unlock(&sc->call_lock);
 691         return (0);
 692 }
 693
 694 int
 695 ig4iic_callback(device_t dev, int index, caddr_t data)
 696 {
 697         ig4iic_softc_t *sc = device_get_softc(dev);
 698         int error = 0;
 699         int how;
 700
 701         switch (index) {
 702         case IIC_REQUEST_BUS:
 703                 /* force polling if ig4iic is requested with IIC_DONTWAIT */
 704                 how = *(int *)data;
 705                 if ((how & IIC_WAIT) == 0) {
 706                         if (sx_try_xlock(&sc->call_lock) == 0)
 707                                 error = IIC_EBUSBSY;
 708                         else
 709                                 sc->poll = true;
 710                 } else
 711                         sx_xlock(&sc->call_lock);
 712                 break;
 713
 714         case IIC_RELEASE_BUS:
 715                 sc->poll = false;
 716                 sx_unlock(&sc->call_lock);
 717                 break;
 718
 719         default:
 720                 error = errno2iic(EINVAL);
 721         }
 722
 723         return (error);
 724 }
 725
 726 /*
 727  * Clock register values can be calculated with following rough equations:
 728  * SCL_HCNT = ceil(IC clock rate * tHIGH)
 729  * SCL_LCNT = ceil(IC clock rate * tLOW)
 730  * SDA_HOLD = ceil(IC clock rate * SDA hold time)
 731  * Precise equations take signal's falling, rising and spike suppression
 732  * times in to account. They can be found in Synopsys or Intel documentation.
 733  *
 734  * Here we snarf formulas and defaults from Linux driver to be able to use
 735  * timing values provided by Intel LPSS driver "as is".
 736  */
 737 static int
 738 ig4iic_clk_params(const struct ig4_hw *hw, int speed,
 739     uint16_t *scl_hcnt, uint16_t *scl_lcnt, uint16_t *sda_hold)
 740 {
 741         uint32_t thigh, tlow, tf_max;   /* nsec */
 742         uint32_t sda_fall_time;         /* nsec */
 743         uint32_t scl_fall_time;         /* nsec */
 744
 745         switch (speed) {
 746         case IG4_CTL_SPEED_STD:
 747                 thigh = IG4_SPEED_STD_THIGH;
 748                 tlow = IG4_SPEED_STD_TLOW;
 749                 tf_max = IG4_SPEED_STD_TF_MAX;
 750                 break;
 751
 752         case IG4_CTL_SPEED_FAST:
 753                 thigh = IG4_SPEED_FAST_THIGH;
 754                 tlow = IG4_SPEED_FAST_TLOW;
 755                 tf_max = IG4_SPEED_FAST_TF_MAX;
 756                 break;
 757
 758         default:
 759                 return (EINVAL);
 760         }
 761
 762         /* Use slowest falling time defaults to be on the safe side */
 763         sda_fall_time = hw->sda_fall_time == 0 ? tf_max : hw->sda_fall_time;
 764         *scl_hcnt = (uint16_t)
 765             ((hw->ic_clock_rate * (thigh + sda_fall_time) + 500) / 1000 - 3);
 766
 767         scl_fall_time = hw->scl_fall_time == 0 ? tf_max : hw->scl_fall_time;
 768         *scl_lcnt = (uint16_t)
 769             ((hw->ic_clock_rate * (tlow + scl_fall_time) + 500) / 1000 - 1);
 770
 771         /*
 772          * There is no "known good" default value for tHD;DAT so keep SDA_HOLD
 773          * intact if sda_hold_time value is not provided.
 774          */
 775         if (hw->sda_hold_time != 0)
 776                 *sda_hold = (uint16_t)
 777                     ((hw->ic_clock_rate * hw->sda_hold_time + 500) / 1000);
 778
 779         return (0);
 780 }
 781
 782 #ifdef DEV_ACPI
 783 static ACPI_STATUS
 784 ig4iic_acpi_params(ACPI_HANDLE handle, char *method,
 785     uint16_t *scl_hcnt, uint16_t *scl_lcnt, uint16_t *sda_hold)
 786 {
 787         ACPI_BUFFER buf;
 788         ACPI_OBJECT *obj, *elems;
 789         ACPI_STATUS status;
 790
 791         buf.Pointer = NULL;
 792         buf.Length = ACPI_ALLOCATE_BUFFER;
 793
 794         status = AcpiEvaluateObject(handle, method, NULL, &buf);
 795         if (ACPI_FAILURE(status))
 796                 return (status);
 797
 798         status = AE_TYPE;
 799         obj = (ACPI_OBJECT *)buf.Pointer;
 800         if (obj->Type == ACPI_TYPE_PACKAGE && obj->Package.Count == 3) {
 801                 elems = obj->Package.Elements;
 802                 *scl_hcnt = elems[0].Integer.Value & IG4_SCL_CLOCK_MASK;
 803                 *scl_lcnt = elems[1].Integer.Value & IG4_SCL_CLOCK_MASK;
 804                 *sda_hold = elems[2].Integer.Value & IG4_SDA_TX_HOLD_MASK;
 805                 status = AE_OK;
 806         }
 807
 808         AcpiOsFree(obj);
 809
 810         return (status);
 811 }
 812 #endif /* DEV_ACPI */
 813
 814 static void
 815 ig4iic_get_config(ig4iic_softc_t *sc)
 816 {
 817         const struct ig4_hw *hw;
 818         uint32_t v;
 819 #ifdef DEV_ACPI
 820         ACPI_HANDLE handle;
 821 #endif
 822         /* Fetch default hardware config from controller */
 823         sc->cfg.version = reg_read(sc, IG4_REG_COMP_VER);
 824         sc->cfg.bus_speed = reg_read(sc, IG4_REG_CTL) & IG4_CTL_SPEED_MASK;
 825         sc->cfg.ss_scl_hcnt =
 826             reg_read(sc, IG4_REG_SS_SCL_HCNT) & IG4_SCL_CLOCK_MASK;
 827         sc->cfg.ss_scl_lcnt =
 828             reg_read(sc, IG4_REG_SS_SCL_LCNT) & IG4_SCL_CLOCK_MASK;
 829         sc->cfg.fs_scl_hcnt =
 830             reg_read(sc, IG4_REG_FS_SCL_HCNT) & IG4_SCL_CLOCK_MASK;
 831         sc->cfg.fs_scl_lcnt =
 832             reg_read(sc, IG4_REG_FS_SCL_LCNT) & IG4_SCL_CLOCK_MASK;
 833         sc->cfg.ss_sda_hold = sc->cfg.fs_sda_hold =
 834             reg_read(sc, IG4_REG_SDA_HOLD) & IG4_SDA_TX_HOLD_MASK;
 835
 836         if (sc->cfg.bus_speed != IG4_CTL_SPEED_STD)
 837                 sc->cfg.bus_speed = IG4_CTL_SPEED_FAST;
 838
 839         /* REG_COMP_PARAM1 is not documented in latest Intel specs */
 840         if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) {
 841                 v = reg_read(sc, IG4_REG_COMP_PARAM1);
 842                 if (IG4_PARAM1_TXFIFO_DEPTH(v) != 0)
 843                         sc->cfg.txfifo_depth = IG4_PARAM1_TXFIFO_DEPTH(v);
 844                 if (IG4_PARAM1_RXFIFO_DEPTH(v) != 0)
 845                         sc->cfg.rxfifo_depth = IG4_PARAM1_RXFIFO_DEPTH(v);
 846         } else {
 847                 /*
 848                  * Hardware does not allow FIFO Threshold Levels value to be
 849                  * set larger than the depth of the buffer. If an attempt is
 850                  * made to do that, the actual value set will be the maximum
 851                  * depth of the buffer.
 852                  */
 853                 v = reg_read(sc, IG4_REG_TX_TL);
 854                 reg_write(sc, IG4_REG_TX_TL, v | IG4_FIFO_MASK);
 855                 sc->cfg.txfifo_depth =
 856                     (reg_read(sc, IG4_REG_TX_TL) & IG4_FIFO_MASK) + 1;
 857                 reg_write(sc, IG4_REG_TX_TL, v);
 858                 v = reg_read(sc, IG4_REG_RX_TL);
 859                 reg_write(sc, IG4_REG_RX_TL, v | IG4_FIFO_MASK);
 860                 sc->cfg.rxfifo_depth =
 861                     (reg_read(sc, IG4_REG_RX_TL) & IG4_FIFO_MASK) + 1;
 862                 reg_write(sc, IG4_REG_RX_TL, v);
 863         }
 864
 865         /* Override hardware config with IC_clock-based counter values */
 866         if (ig4_timings < 2 && sc->version < nitems(ig4iic_hw)) {
 867                 hw = &ig4iic_hw[sc->version];
 868                 sc->cfg.bus_speed = IG4_CTL_SPEED_FAST;
 869                 ig4iic_clk_params(hw, IG4_CTL_SPEED_STD, &sc->cfg.ss_scl_hcnt,
 870                     &sc->cfg.ss_scl_lcnt, &sc->cfg.ss_sda_hold);
 871                 ig4iic_clk_params(hw, IG4_CTL_SPEED_FAST, &sc->cfg.fs_scl_hcnt,
 872                     &sc->cfg.fs_scl_lcnt, &sc->cfg.fs_sda_hold);
 873                 if (hw->txfifo_depth != 0)
 874                         sc->cfg.txfifo_depth = hw->txfifo_depth;
 875                 if (hw->rxfifo_depth != 0)
 876                         sc->cfg.rxfifo_depth = hw->rxfifo_depth;
 877         } else if (ig4_timings == 2) {
 878                 /*
 879                  * Timings of original ig4 driver:
 880                  * Program based on a 25000 Hz clock.  This is a bit of a
 881                  * hack (obviously).  The defaults are 400 and 470 for standard
 882                  * and 60 and 130 for fast.  The defaults for standard fail
 883                  * utterly (presumably cause an abort) because the clock time
 884                  * is ~18.8ms by default.  This brings it down to ~4ms.
 885                  */
 886                 sc->cfg.bus_speed = IG4_CTL_SPEED_STD;
 887                 sc->cfg.ss_scl_hcnt = sc->cfg.fs_scl_hcnt = 100;
 888                 sc->cfg.ss_scl_lcnt = sc->cfg.fs_scl_lcnt = 125;
 889                 if (sc->version == IG4_SKYLAKE)
 890                         sc->cfg.ss_sda_hold = sc->cfg.fs_sda_hold = 28;
 891         }
 892
 893 #ifdef DEV_ACPI
 894         /* Evaluate SSCN and FMCN ACPI methods to fetch timings */
 895         if (ig4_timings == 0 && (handle = acpi_get_handle(sc->dev)) != NULL) {
 896                 ig4iic_acpi_params(handle, "SSCN", &sc->cfg.ss_scl_hcnt,
 897                     &sc->cfg.ss_scl_lcnt, &sc->cfg.ss_sda_hold);
 898                 ig4iic_acpi_params(handle, "FMCN", &sc->cfg.fs_scl_hcnt,
 899                     &sc->cfg.fs_scl_lcnt, &sc->cfg.fs_sda_hold);
 900         }
 901 #endif
 902
 903         if (bootverbose) {
 904                 device_printf(sc->dev, "Controller parameters:\n");
 905                 printf("  Speed: %s\n",
 906                     sc->cfg.bus_speed == IG4_CTL_SPEED_STD ? "Std" : "Fast");
 907                 printf("  Regs:  HCNT  :LCNT  :SDAHLD\n");
 908                 printf("  Std:   0x%04hx:0x%04hx:0x%04hx\n",
 909                     sc->cfg.ss_scl_hcnt, sc->cfg.ss_scl_lcnt,
 910                     sc->cfg.ss_sda_hold);
 911                 printf("  Fast:  0x%04hx:0x%04hx:0x%04hx\n",
 912                     sc->cfg.fs_scl_hcnt, sc->cfg.fs_scl_lcnt,
 913                     sc->cfg.fs_sda_hold);
 914                 printf("  FIFO:  RX:0x%04x: TX:0x%04x\n",
 915                     sc->cfg.rxfifo_depth, sc->cfg.txfifo_depth);
 916         }
 917 }
 918
 919 static int
 920 ig4iic_set_config(ig4iic_softc_t *sc, bool reset)
 921 {
 922         uint32_t v;
 923
 924         v = reg_read(sc, IG4_REG_DEVIDLE_CTRL);
 925         if (IG4_HAS_ADDREGS(sc->version) && (v & IG4_RESTORE_REQUIRED)) {
 926                 reg_write(sc, IG4_REG_DEVIDLE_CTRL, IG4_DEVICE_IDLE | IG4_RESTORE_REQUIRED);
 927                 reg_write(sc, IG4_REG_DEVIDLE_CTRL, 0);
 928                 pause("i2crst", 1);
 929                 reset = true;
 930         }
 931
 932         if ((sc->version == IG4_HASWELL || sc->version == IG4_ATOM) && reset) {
 933                 reg_write(sc, IG4_REG_RESETS_HSW, IG4_RESETS_ASSERT_HSW);
 934                 reg_write(sc, IG4_REG_RESETS_HSW, IG4_RESETS_DEASSERT_HSW);
 935         } else if (IG4_HAS_ADDREGS(sc->version) && reset) {
 936                 reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_ASSERT_SKL);
 937                 reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_DEASSERT_SKL);
 938         }
 939
 940         if (sc->version == IG4_ATOM)
 941                 v = reg_read(sc, IG4_REG_COMP_TYPE);
 942
 943         if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) {
 944                 v = reg_read(sc, IG4_REG_COMP_PARAM1);
 945                 v = reg_read(sc, IG4_REG_GENERAL);
 946                 /*
 947                  * The content of IG4_REG_GENERAL is different for each
 948                  * controller version.
 949                  */
 950                 if (sc->version == IG4_HASWELL &&
 951                     (v & IG4_GENERAL_SWMODE) == 0) {
 952                         v |= IG4_GENERAL_SWMODE;
 953                         reg_write(sc, IG4_REG_GENERAL, v);
 954                         v = reg_read(sc, IG4_REG_GENERAL);
 955                 }
 956         }
 957
 958         if (sc->version == IG4_HASWELL) {
 959                 v = reg_read(sc, IG4_REG_SW_LTR_VALUE);
 960                 v = reg_read(sc, IG4_REG_AUTO_LTR_VALUE);
 961         } else if (IG4_HAS_ADDREGS(sc->version)) {
 962                 v = reg_read(sc, IG4_REG_ACTIVE_LTR_VALUE);
 963                 v = reg_read(sc, IG4_REG_IDLE_LTR_VALUE);
 964         }
 965
 966         if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) {
 967                 v = reg_read(sc, IG4_REG_COMP_VER);
 968                 if (v < IG4_COMP_MIN_VER)
 969                         return(ENXIO);
 970         }
 971
 972         if (set_controller(sc, 0)) {
 973                 device_printf(sc->dev, "controller error during attach-1\n");
 974                 return (ENXIO);
 975         }
 976
 977         reg_read(sc, IG4_REG_CLR_INTR);
 978         reg_write(sc, IG4_REG_INTR_MASK, 0);
 979         sc->intr_mask = 0;
 980
 981         reg_write(sc, IG4_REG_SS_SCL_HCNT, sc->cfg.ss_scl_hcnt);
 982         reg_write(sc, IG4_REG_SS_SCL_LCNT, sc->cfg.ss_scl_lcnt);
 983         reg_write(sc, IG4_REG_FS_SCL_HCNT, sc->cfg.fs_scl_hcnt);
 984         reg_write(sc, IG4_REG_FS_SCL_LCNT, sc->cfg.fs_scl_lcnt);
 985         reg_write(sc, IG4_REG_SDA_HOLD,
 986             (sc->cfg.bus_speed  & IG4_CTL_SPEED_MASK) == IG4_CTL_SPEED_STD ?
 987               sc->cfg.ss_sda_hold : sc->cfg.fs_sda_hold);
 988
 989         /*
 990          * Use a threshold of 1 so we get interrupted on each character,
 991          * allowing us to use mtx_sleep() in our poll code.  Not perfect
 992          * but this is better than using DELAY() for receiving data.
 993          *
 994          * See ig4_var.h for details on interrupt handler synchronization.
 995          */
 996         reg_write(sc, IG4_REG_RX_TL, 0);
 997         reg_write(sc, IG4_REG_TX_TL, 0);
 998
 999         reg_write(sc, IG4_REG_CTL,
1000                   IG4_CTL_MASTER |
1001                   IG4_CTL_SLAVE_DISABLE |
1002                   IG4_CTL_RESTARTEN |
1003                   (sc->cfg.bus_speed & IG4_CTL_SPEED_MASK));
1004
1005         /* Force setting of the target address on the next transfer */
1006         sc->slave_valid = 0;
1007
1008         return (0);
1009 }
1010
1011 /*
1012  * Called from ig4iic_pci_attach/detach()
1013  */
1014 int
1015 ig4iic_attach(ig4iic_softc_t *sc)
1016 {
1017         int error;
1018
1019         mtx_init(&sc->io_lock, "IG4 I/O lock", NULL, MTX_SPIN);
1020         sx_init(&sc->call_lock, "IG4 call lock");
1021
1022         ig4iic_get_config(sc);
1023
1024         error = ig4iic_set_config(sc, IG4_HAS_ADDREGS(sc->version));
1025         if (error)
1026                 goto done;
1027
1028         sc->iicbus = device_add_child(sc->dev, "iicbus", -1);
1029         if (sc->iicbus == NULL) {
1030                 device_printf(sc->dev, "iicbus driver not found\n");
1031                 error = ENXIO;
1032                 goto done;
1033         }
1034
1035         if (set_controller(sc, IG4_I2C_ENABLE)) {
1036                 device_printf(sc->dev, "controller error during attach-2\n");
1037                 error = ENXIO;
1038                 goto done;
1039         }
1040         if (set_controller(sc, 0)) {
1041                 device_printf(sc->dev, "controller error during attach-3\n");
1042                 error = ENXIO;
1043                 goto done;
1044         }
1045         error = bus_setup_intr(sc->dev, sc->intr_res, INTR_TYPE_MISC | INTR_MPSAFE,
1046                                ig4iic_intr, NULL, sc, &sc->intr_handle);
1047         if (error) {
1048                 device_printf(sc->dev,
1049                               "Unable to setup irq: error %d\n", error);
1050         }
1051
1052         error = bus_generic_attach(sc->dev);
1053         if (error) {
1054                 device_printf(sc->dev,
1055                               "failed to attach child: error %d\n", error);
1056         }
1057
1058 done:
1059         return (error);
1060 }
1061
1062 int
1063 ig4iic_detach(ig4iic_softc_t *sc)
1064 {
1065         int error;
1066
1067         if (device_is_attached(sc->dev)) {
1068                 error = bus_generic_detach(sc->dev);
1069                 if (error)
1070                         return (error);
1071         }
1072         if (sc->iicbus)
1073                 device_delete_child(sc->dev, sc->iicbus);
1074         if (sc->intr_handle)
1075                 bus_teardown_intr(sc->dev, sc->intr_res, sc->intr_handle);
1076
1077         sx_xlock(&sc->call_lock);
1078
1079         sc->iicbus = NULL;
1080         sc->intr_handle = NULL;
1081         reg_write(sc, IG4_REG_INTR_MASK, 0);
1082         set_controller(sc, 0);
1083
1084         sx_xunlock(&sc->call_lock);
1085
1086         mtx_destroy(&sc->io_lock);
1087         sx_destroy(&sc->call_lock);
1088
1089         return (0);
1090 }
1091
1092 int
1093 ig4iic_suspend(ig4iic_softc_t *sc)
1094 {
1095         int error;
1096
1097         /* suspend all children */
1098         error = bus_generic_suspend(sc->dev);
1099
1100         sx_xlock(&sc->call_lock);
1101         set_controller(sc, 0);
1102         if (IG4_HAS_ADDREGS(sc->version)) {
1103                 /*
1104                  * Place the device in the idle state, just to be safe
1105                  */
1106                 reg_write(sc, IG4_REG_DEVIDLE_CTRL, IG4_DEVICE_IDLE);
1107                 /*
1108                  * Controller can become dysfunctional if I2C lines are pulled
1109                  * down when suspend procedure turns off power to I2C device.
1110                  * Place device in the reset state to avoid this.
1111                  */
1112                 reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_ASSERT_SKL);
1113         }
1114         sx_xunlock(&sc->call_lock);
1115
1116         return (error);
1117 }
1118
1119 int ig4iic_resume(ig4iic_softc_t *sc)
1120 {
1121         int error;
1122
1123         sx_xlock(&sc->call_lock);
1124         if (ig4iic_set_config(sc, IG4_HAS_ADDREGS(sc->version)))
1125                 device_printf(sc->dev, "controller error during resume\n");
1126         sx_xunlock(&sc->call_lock);
1127
1128         error = bus_generic_resume(sc->dev);
1129
1130         return (error);
1131 }
1132
1133 /*
1134  * Interrupt Operation, see ig4_var.h for locking semantics.
1135  */
1136 static int
1137 ig4iic_intr(void *cookie)
1138 {
1139         ig4iic_softc_t *sc = cookie;
1140         int retval = FILTER_STRAY;
1141
1142         mtx_lock_spin(&sc->io_lock);
1143         /* Ignore stray interrupts */
1144         if (sc->intr_mask != 0 && reg_read(sc, IG4_REG_INTR_STAT) != 0) {
1145                 /* Interrupt bits are cleared in wait_intr() loop */
1146                 ig4iic_set_intr_mask(sc, 0);
1147                 wakeup(sc);
1148                 retval = FILTER_HANDLED;
1149         }
1150         mtx_unlock_spin(&sc->io_lock);
1151
1152         return (retval);
1153 }
1154
1155 #define REGDUMP(sc, reg)        \
1156         device_printf(sc->dev, "  %-23s %08x\n", #reg, reg_read(sc, reg))
1157
1158 static void
1159 ig4iic_dump(ig4iic_softc_t *sc)
1160 {
1161         device_printf(sc->dev, "ig4iic register dump:\n");
1162         REGDUMP(sc, IG4_REG_CTL);
1163         REGDUMP(sc, IG4_REG_TAR_ADD);
1164         REGDUMP(sc, IG4_REG_SS_SCL_HCNT);
1165         REGDUMP(sc, IG4_REG_SS_SCL_LCNT);
1166         REGDUMP(sc, IG4_REG_FS_SCL_HCNT);
1167         REGDUMP(sc, IG4_REG_FS_SCL_LCNT);
1168         REGDUMP(sc, IG4_REG_INTR_STAT);
1169         REGDUMP(sc, IG4_REG_INTR_MASK);
1170         REGDUMP(sc, IG4_REG_RAW_INTR_STAT);
1171         REGDUMP(sc, IG4_REG_RX_TL);
1172         REGDUMP(sc, IG4_REG_TX_TL);
1173         REGDUMP(sc, IG4_REG_I2C_EN);
1174         REGDUMP(sc, IG4_REG_I2C_STA);
1175         REGDUMP(sc, IG4_REG_TXFLR);
1176         REGDUMP(sc, IG4_REG_RXFLR);
1177         REGDUMP(sc, IG4_REG_SDA_HOLD);
1178         REGDUMP(sc, IG4_REG_TX_ABRT_SOURCE);
1179         REGDUMP(sc, IG4_REG_SLV_DATA_NACK);
1180         REGDUMP(sc, IG4_REG_DMA_CTRL);
1181         REGDUMP(sc, IG4_REG_DMA_TDLR);
1182         REGDUMP(sc, IG4_REG_DMA_RDLR);
1183         REGDUMP(sc, IG4_REG_SDA_SETUP);
1184         REGDUMP(sc, IG4_REG_ENABLE_STATUS);
1185         REGDUMP(sc, IG4_REG_COMP_PARAM1);
1186         REGDUMP(sc, IG4_REG_COMP_VER);
1187         if (sc->version == IG4_ATOM) {
1188                 REGDUMP(sc, IG4_REG_COMP_TYPE);
1189                 REGDUMP(sc, IG4_REG_CLK_PARMS);
1190         }
1191         if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) {
1192                 REGDUMP(sc, IG4_REG_RESETS_HSW);
1193                 REGDUMP(sc, IG4_REG_GENERAL);
1194         } else if (sc->version == IG4_SKYLAKE) {
1195                 REGDUMP(sc, IG4_REG_RESETS_SKL);
1196         }
1197         if (sc->version == IG4_HASWELL) {
1198                 REGDUMP(sc, IG4_REG_SW_LTR_VALUE);
1199                 REGDUMP(sc, IG4_REG_AUTO_LTR_VALUE);
1200         } else if (IG4_HAS_ADDREGS(sc->version)) {
1201                 REGDUMP(sc, IG4_REG_ACTIVE_LTR_VALUE);
1202                 REGDUMP(sc, IG4_REG_IDLE_LTR_VALUE);
1203         }
1204 }
1205 #undef REGDUMP
1206
1207 devclass_t ig4iic_devclass;
1208
1209 DRIVER_MODULE(iicbus, ig4iic, iicbus_driver, iicbus_devclass, NULL, NULL);
1210 #ifdef DEV_ACPI
1211 DRIVER_MODULE(acpi_iicbus, ig4iic, acpi_iicbus_driver, iicbus_devclass, NULL,
1212     NULL);
1213 #endif
1214 MODULE_DEPEND(ig4iic, iicbus, IICBUS_MINVER, IICBUS_PREFVER, IICBUS_MAXVER);
1215 MODULE_VERSION(ig4iic, 1);