2 * Copyright (c) 2014 The DragonFly Project. All rights reserved.
4 * This code is derived from software contributed to The DragonFly Project
5 * by Matthew Dillon <dillon@backplane.com> and was subsequently ported
6 * to FreeBSD by Michael Gmelin <freebsd@grem.de>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in
16 * the documentation and/or other materials provided with the
18 * 3. Neither the name of The DragonFly Project nor the names of its
19 * contributors may be used to endorse or promote products derived
20 * from this software without specific, prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
25 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
26 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 #include <sys/cdefs.h>
37 __FBSDID("$FreeBSD$");
40 * Intel fourth generation mobile cpus integrated I2C device, smbus driver.
42 * See ig4_reg.h for datasheet reference and notes.
43 * See ig4_var.h for locking semantics.
46 #include <sys/param.h>
47 #include <sys/systm.h>
48 #include <sys/kernel.h>
49 #include <sys/module.h>
50 #include <sys/errno.h>
52 #include <sys/mutex.h>
54 #include <sys/syslog.h>
56 #include <sys/sysctl.h>
58 #include <machine/bus.h>
61 #include <dev/pci/pcivar.h>
62 #include <dev/pci/pcireg.h>
63 #include <dev/smbus/smbconf.h>
65 #include <dev/ichiic/ig4_reg.h>
66 #include <dev/ichiic/ig4_var.h>
68 #define TRANS_NORMAL 1
72 static void ig4iic_start(void *xdev);
73 static void ig4iic_intr(void *cookie);
74 static void ig4iic_dump(ig4iic_softc_t *sc);
77 SYSCTL_INT(_debug, OID_AUTO, ig4_dump, CTLFLAG_RW,
78 &ig4_dump, 0, "Dump controller registers");
81 * Low-level inline support functions
84 reg_write(ig4iic_softc_t *sc, uint32_t reg, uint32_t value)
86 bus_write_4(sc->regs_res, reg, value);
87 bus_barrier(sc->regs_res, reg, 4, BUS_SPACE_BARRIER_WRITE);
90 static __inline uint32_t
91 reg_read(ig4iic_softc_t *sc, uint32_t reg)
95 bus_barrier(sc->regs_res, reg, 4, BUS_SPACE_BARRIER_READ);
96 value = bus_read_4(sc->regs_res, reg);
101 * Enable or disable the controller and wait for the controller to acknowledge
105 set_controller(ig4iic_softc_t *sc, uint32_t ctl)
112 * When the controller is enabled, interrupt on STOP detect
113 * or receive character ready and clear pending interrupts.
115 if (ctl & IG4_I2C_ENABLE) {
116 reg_write(sc, IG4_REG_INTR_MASK, IG4_INTR_STOP_DET |
118 reg_read(sc, IG4_REG_CLR_INTR);
120 reg_write(sc, IG4_REG_INTR_MASK, 0);
122 reg_write(sc, IG4_REG_I2C_EN, ctl);
123 error = SMB_ETIMEOUT;
125 for (retry = 100; retry > 0; --retry) {
126 v = reg_read(sc, IG4_REG_ENABLE_STATUS);
127 if (((v ^ ctl) & IG4_I2C_ENABLE) == 0) {
134 mtx_sleep(sc, &sc->io_lock, 0, "i2cslv", 1);
140 * Wait up to 25ms for the requested status using a 25uS polling loop.
143 wait_status(ig4iic_softc_t *sc, uint32_t status)
149 u_int limit_us = 25000; /* 25ms */
151 error = SMB_ETIMEOUT;
155 * Check requested status
157 v = reg_read(sc, IG4_REG_I2C_STA);
164 * When waiting for receive data break-out if the interrupt
165 * loaded data into the FIFO.
167 if (status & IG4_STATUS_RX_NOTEMPTY) {
168 if (sc->rpos != sc->rnext) {
175 * When waiting for the transmit FIFO to become empty,
176 * reset the timeout if we see a change in the transmit
177 * FIFO level as progress is being made.
179 if (status & IG4_STATUS_TX_EMPTY) {
180 v = reg_read(sc, IG4_REG_TXFLR) & IG4_FIFOLVL_MASK;
188 * Stop if we've run out of time.
190 if (count_us >= limit_us)
194 * When waiting for receive data let the interrupt do its
195 * work, otherwise poll with the lock held.
197 if (status & IG4_STATUS_RX_NOTEMPTY) {
198 mtx_sleep(sc, &sc->io_lock, 0, "i2cwait",
199 (hz + 99) / 100); /* sleep up to 10ms */
211 * Read I2C data. The data might have already been read by
212 * the interrupt code, otherwise it is sitting in the data
216 data_read(ig4iic_softc_t *sc)
220 if (sc->rpos == sc->rnext) {
221 c = (uint8_t)reg_read(sc, IG4_REG_DATA_CMD);
223 c = sc->rbuf[sc->rpos & IG4_RBUFMASK];
230 * Set the slave address. The controller must be disabled when
231 * changing the address.
233 * This operation does not issue anything to the I2C bus but sets
234 * the target address for when the controller later issues a START.
237 set_slave_addr(ig4iic_softc_t *sc, uint8_t slave, int trans_op)
243 use_10bit = sc->use_10bit;
244 if (trans_op & SMB_TRANS_7BIT)
246 if (trans_op & SMB_TRANS_10BIT)
249 if (sc->slave_valid && sc->last_slave == slave &&
250 sc->use_10bit == use_10bit) {
253 sc->use_10bit = use_10bit;
256 * Wait for TXFIFO to drain before disabling the controller.
258 * If a write message has not been completed it's really a
259 * programming error, but for now in that case issue an extra
262 * If a read message has not been completed it's also a programming
263 * error, for now just ignore it.
265 wait_status(sc, IG4_STATUS_TX_NOTFULL);
266 if (sc->write_started) {
267 reg_write(sc, IG4_REG_DATA_CMD, IG4_DATA_STOP);
268 sc->write_started = 0;
270 if (sc->read_started)
271 sc->read_started = 0;
272 wait_status(sc, IG4_STATUS_TX_EMPTY);
274 set_controller(sc, 0);
275 ctl = reg_read(sc, IG4_REG_CTL);
276 ctl &= ~IG4_CTL_10BIT;
277 ctl |= IG4_CTL_RESTARTEN;
281 tar |= IG4_TAR_10BIT;
282 ctl |= IG4_CTL_10BIT;
284 reg_write(sc, IG4_REG_CTL, ctl);
285 reg_write(sc, IG4_REG_TAR_ADD, tar);
286 set_controller(sc, IG4_I2C_ENABLE);
288 sc->last_slave = slave;
292 * Issue START with byte command, possible count, and a variable length
293 * read or write buffer, then possible turn-around read. The read also
294 * has a possible count received.
298 * Quick: START+ADDR+RD/WR STOP
300 * Normal: START+ADDR+WR CMD DATA..DATA STOP
303 * RESTART+ADDR RDATA..RDATA STOP
304 * (can also be used for I2C transactions)
306 * Process Call: START+ADDR+WR CMD DATAL DATAH
307 * RESTART+ADDR+RD RDATAL RDATAH STOP
309 * Block: START+ADDR+RD CMD
310 * RESTART+ADDR+RD RCOUNT DATA... STOP
313 * RESTART+ADDR+WR WCOUNT DATA... STOP
315 * For I2C - basically, no *COUNT fields, possibly no *CMD field. If the
316 * sender needs to issue a 2-byte command it will incorporate it
317 * into the write buffer and also set NOCMD.
319 * Generally speaking, the START+ADDR / RESTART+ADDR is handled automatically
320 * by the controller at the beginning of a command sequence or on a data
321 * direction turn-around, and we only need to tell it when to issue the STOP.
324 smb_transaction(ig4iic_softc_t *sc, char cmd, int op,
325 char *wbuf, int wcount, char *rbuf, int rcount, int *actualp)
332 * Debugging - dump registers
335 unit = device_get_unit(sc->dev);
336 if (ig4_dump & (1 << unit)) {
337 ig4_dump &= ~(1 << unit);
343 * Issue START or RESTART with next data byte, clear any previous
344 * abort condition that may have been holding the txfifo in reset.
346 last = IG4_DATA_RESTART;
347 reg_read(sc, IG4_REG_CLR_TX_ABORT);
352 * Issue command if not told otherwise (smbus).
354 if ((op & SMB_TRANS_NOCMD) == 0) {
355 error = wait_status(sc, IG4_STATUS_TX_NOTFULL);
359 if (wcount == 0 && rcount == 0 && (op & SMB_TRANS_NOSTOP) == 0)
360 last |= IG4_DATA_STOP;
361 reg_write(sc, IG4_REG_DATA_CMD, last);
366 * Clean out any previously received data.
368 if (sc->rpos != sc->rnext &&
369 (op & SMB_TRANS_NOREPORT) == 0) {
370 device_printf(sc->dev,
371 "discarding %d bytes of spurious data\n",
372 sc->rnext - sc->rpos);
378 * If writing and not told otherwise, issue the write count (smbus).
380 if (wcount && (op & SMB_TRANS_NOCNT) == 0) {
381 error = wait_status(sc, IG4_STATUS_TX_NOTFULL);
385 reg_write(sc, IG4_REG_DATA_CMD, last);
393 error = wait_status(sc, IG4_STATUS_TX_NOTFULL);
396 last |= (u_char)*wbuf;
397 if (wcount == 1 && rcount == 0 && (op & SMB_TRANS_NOSTOP) == 0)
398 last |= IG4_DATA_STOP;
399 reg_write(sc, IG4_REG_DATA_CMD, last);
406 * Issue reads to xmit FIFO (strange, I know) to tell the controller
407 * to clock in data. At the moment just issue one read ahead to
408 * pipeline the incoming data.
410 * NOTE: In the case of NOCMD and wcount == 0 we still issue a
411 * RESTART here, even if the data direction has not changed
412 * from the previous CHAINing call. This we force the RESTART.
413 * (A new START is issued automatically by the controller in
414 * the other nominal cases such as a data direction change or
415 * a previous STOP was issued).
417 * If this will be the last byte read we must also issue the STOP
418 * at the end of the read.
421 last = IG4_DATA_RESTART | IG4_DATA_COMMAND_RD;
423 (op & (SMB_TRANS_NOSTOP | SMB_TRANS_NOCNT)) ==
425 last |= IG4_DATA_STOP;
427 reg_write(sc, IG4_REG_DATA_CMD, last);
428 last = IG4_DATA_COMMAND_RD;
432 * Bulk read (i2c) and count field handling (smbus)
436 * Maintain a pipeline by queueing the allowance for the next
437 * read before waiting for the current read.
440 if (op & SMB_TRANS_NOCNT)
441 last = (rcount == 2) ? IG4_DATA_STOP : 0;
444 reg_write(sc, IG4_REG_DATA_CMD, IG4_DATA_COMMAND_RD |
447 error = wait_status(sc, IG4_STATUS_RX_NOTEMPTY);
449 if ((op & SMB_TRANS_NOREPORT) == 0) {
450 device_printf(sc->dev,
451 "rx timeout addr 0x%02x\n",
456 last = data_read(sc);
458 if (op & SMB_TRANS_NOCNT) {
459 *rbuf = (u_char)last;
466 * Handle count field (smbus), which is not part of
467 * the rcount'ed buffer. The first read data in a
468 * bulk transfer is the count.
470 * XXX if rcount is loaded as 0 how do I generate a
471 * STOP now without issuing another RD or WR?
473 if (rcount > (u_char)last)
474 rcount = (u_char)last;
475 op |= SMB_TRANS_NOCNT;
480 /* XXX wait for xmit buffer to become empty */
481 last = reg_read(sc, IG4_REG_TX_ABRT_SOURCE);
487 * SMBUS API FUNCTIONS
489 * Called from ig4iic_pci_attach/detach()
492 ig4iic_attach(ig4iic_softc_t *sc)
497 v = reg_read(sc, IG4_REG_COMP_TYPE);
498 v = reg_read(sc, IG4_REG_COMP_PARAM1);
499 v = reg_read(sc, IG4_REG_GENERAL);
500 if ((v & IG4_GENERAL_SWMODE) == 0) {
501 v |= IG4_GENERAL_SWMODE;
502 reg_write(sc, IG4_REG_GENERAL, v);
503 v = reg_read(sc, IG4_REG_GENERAL);
506 v = reg_read(sc, IG4_REG_SW_LTR_VALUE);
507 v = reg_read(sc, IG4_REG_AUTO_LTR_VALUE);
509 v = reg_read(sc, IG4_REG_COMP_VER);
510 if (v != IG4_COMP_VER) {
514 v = reg_read(sc, IG4_REG_SS_SCL_HCNT);
515 v = reg_read(sc, IG4_REG_SS_SCL_LCNT);
516 v = reg_read(sc, IG4_REG_FS_SCL_HCNT);
517 v = reg_read(sc, IG4_REG_FS_SCL_LCNT);
518 v = reg_read(sc, IG4_REG_SDA_HOLD);
520 v = reg_read(sc, IG4_REG_SS_SCL_HCNT);
521 reg_write(sc, IG4_REG_FS_SCL_HCNT, v);
522 v = reg_read(sc, IG4_REG_SS_SCL_LCNT);
523 reg_write(sc, IG4_REG_FS_SCL_LCNT, v);
526 * Program based on a 25000 Hz clock. This is a bit of a
527 * hack (obviously). The defaults are 400 and 470 for standard
528 * and 60 and 130 for fast. The defaults for standard fail
529 * utterly (presumably cause an abort) because the clock time
530 * is ~18.8ms by default. This brings it down to ~4ms (for now).
532 reg_write(sc, IG4_REG_SS_SCL_HCNT, 100);
533 reg_write(sc, IG4_REG_SS_SCL_LCNT, 125);
534 reg_write(sc, IG4_REG_FS_SCL_HCNT, 100);
535 reg_write(sc, IG4_REG_FS_SCL_LCNT, 125);
538 * Use a threshold of 1 so we get interrupted on each character,
539 * allowing us to use mtx_sleep() in our poll code. Not perfect
540 * but this is better than using DELAY() for receiving data.
542 * See ig4_var.h for details on interrupt handler synchronization.
544 reg_write(sc, IG4_REG_RX_TL, 1);
546 reg_write(sc, IG4_REG_CTL,
548 IG4_CTL_SLAVE_DISABLE |
552 sc->smb = device_add_child(sc->dev, "smbus", -1);
553 if (sc->smb == NULL) {
554 device_printf(sc->dev, "smbus driver not found\n");
561 * Don't do this, it blows up the PCI config
563 reg_write(sc, IG4_REG_RESETS, IG4_RESETS_ASSERT);
564 reg_write(sc, IG4_REG_RESETS, IG4_RESETS_DEASSERT);
567 mtx_lock(&sc->io_lock);
568 if (set_controller(sc, 0))
569 device_printf(sc->dev, "controller error during attach-1\n");
570 if (set_controller(sc, IG4_I2C_ENABLE))
571 device_printf(sc->dev, "controller error during attach-2\n");
572 mtx_unlock(&sc->io_lock);
573 error = bus_setup_intr(sc->dev, sc->intr_res, INTR_TYPE_MISC | INTR_MPSAFE,
574 NULL, ig4iic_intr, sc, &sc->intr_handle);
576 device_printf(sc->dev,
577 "Unable to setup irq: error %d\n", error);
580 sc->enum_hook.ich_func = ig4iic_start;
581 sc->enum_hook.ich_arg = sc->dev;
584 * We have to wait until interrupts are enabled. I2C read and write
585 * only works if the interrupts are available.
587 if (config_intrhook_establish(&sc->enum_hook) != 0)
597 ig4iic_start(void *xdev)
601 device_t dev = (device_t)xdev;
603 sc = device_get_softc(dev);
605 config_intrhook_disestablish(&sc->enum_hook);
607 /* Attach us to the smbus */
608 error = bus_generic_attach(sc->dev);
610 device_printf(sc->dev,
611 "failed to attach child: error %d\n", error);
618 ig4iic_detach(ig4iic_softc_t *sc)
622 if (device_is_attached(sc->dev)) {
623 error = bus_generic_detach(sc->dev);
628 device_delete_child(sc->dev, sc->smb);
630 bus_teardown_intr(sc->dev, sc->intr_res, sc->intr_handle);
632 sx_xlock(&sc->call_lock);
633 mtx_lock(&sc->io_lock);
636 sc->intr_handle = NULL;
637 reg_write(sc, IG4_REG_INTR_MASK, 0);
638 set_controller(sc, 0);
640 mtx_unlock(&sc->io_lock);
641 sx_xunlock(&sc->call_lock);
646 ig4iic_smb_callback(device_t dev, int index, void *data)
651 case SMB_REQUEST_BUS:
654 case SMB_RELEASE_BUS:
666 * Quick command. i.e. START + cmd + R/W + STOP and no data. It is
667 * unclear to me how I could implement this with the intel i2c controller
668 * because the controller sends STARTs and STOPs automatically with data.
671 ig4iic_smb_quick(device_t dev, u_char slave, int how)
674 return (SMB_ENOTSUPP);
678 * Incremental send byte without stop (?). It is unclear why the slave
679 * address is specified if this presumably is used in combination with
680 * ig4iic_smb_quick().
682 * (Also, how would this work anyway? Issue the last byte with writeb()?)
685 ig4iic_smb_sendb(device_t dev, u_char slave, char byte)
687 ig4iic_softc_t *sc = device_get_softc(dev);
691 sx_xlock(&sc->call_lock);
692 mtx_lock(&sc->io_lock);
694 set_slave_addr(sc, slave, 0);
696 if (wait_status(sc, IG4_STATUS_TX_NOTFULL) == 0) {
697 reg_write(sc, IG4_REG_DATA_CMD, cmd);
700 error = SMB_ETIMEOUT;
703 mtx_unlock(&sc->io_lock);
704 sx_xunlock(&sc->call_lock);
709 * Incremental receive byte without stop (?). It is unclear why the slave
710 * address is specified if this presumably is used in combination with
711 * ig4iic_smb_quick().
714 ig4iic_smb_recvb(device_t dev, u_char slave, char *byte)
716 ig4iic_softc_t *sc = device_get_softc(dev);
719 sx_xlock(&sc->call_lock);
720 mtx_lock(&sc->io_lock);
722 set_slave_addr(sc, slave, 0);
723 reg_write(sc, IG4_REG_DATA_CMD, IG4_DATA_COMMAND_RD);
724 if (wait_status(sc, IG4_STATUS_RX_NOTEMPTY) == 0) {
725 *byte = data_read(sc);
729 error = SMB_ETIMEOUT;
732 mtx_unlock(&sc->io_lock);
733 sx_xunlock(&sc->call_lock);
738 * Write command and single byte in transaction.
741 ig4iic_smb_writeb(device_t dev, u_char slave, char cmd, char byte)
743 ig4iic_softc_t *sc = device_get_softc(dev);
746 sx_xlock(&sc->call_lock);
747 mtx_lock(&sc->io_lock);
749 set_slave_addr(sc, slave, 0);
750 error = smb_transaction(sc, cmd, SMB_TRANS_NOCNT,
751 &byte, 1, NULL, 0, NULL);
753 mtx_unlock(&sc->io_lock);
754 sx_xunlock(&sc->call_lock);
759 * Write command and single word in transaction.
762 ig4iic_smb_writew(device_t dev, u_char slave, char cmd, short word)
764 ig4iic_softc_t *sc = device_get_softc(dev);
768 sx_xlock(&sc->call_lock);
769 mtx_lock(&sc->io_lock);
771 set_slave_addr(sc, slave, 0);
772 buf[0] = word & 0xFF;
774 error = smb_transaction(sc, cmd, SMB_TRANS_NOCNT,
775 buf, 2, NULL, 0, NULL);
777 mtx_unlock(&sc->io_lock);
778 sx_xunlock(&sc->call_lock);
783 * write command and read single byte in transaction.
786 ig4iic_smb_readb(device_t dev, u_char slave, char cmd, char *byte)
788 ig4iic_softc_t *sc = device_get_softc(dev);
791 sx_xlock(&sc->call_lock);
792 mtx_lock(&sc->io_lock);
794 set_slave_addr(sc, slave, 0);
795 error = smb_transaction(sc, cmd, SMB_TRANS_NOCNT,
796 NULL, 0, byte, 1, NULL);
798 mtx_unlock(&sc->io_lock);
799 sx_xunlock(&sc->call_lock);
804 * write command and read word in transaction.
807 ig4iic_smb_readw(device_t dev, u_char slave, char cmd, short *word)
809 ig4iic_softc_t *sc = device_get_softc(dev);
813 sx_xlock(&sc->call_lock);
814 mtx_lock(&sc->io_lock);
816 set_slave_addr(sc, slave, 0);
817 if ((error = smb_transaction(sc, cmd, SMB_TRANS_NOCNT,
818 NULL, 0, buf, 2, NULL)) == 0) {
819 *word = (u_char)buf[0] | ((u_char)buf[1] << 8);
822 mtx_unlock(&sc->io_lock);
823 sx_xunlock(&sc->call_lock);
828 * write command and word and read word in transaction
831 ig4iic_smb_pcall(device_t dev, u_char slave, char cmd,
832 short sdata, short *rdata)
834 ig4iic_softc_t *sc = device_get_softc(dev);
839 sx_xlock(&sc->call_lock);
840 mtx_lock(&sc->io_lock);
842 set_slave_addr(sc, slave, 0);
843 wbuf[0] = sdata & 0xFF;
844 wbuf[1] = sdata >> 8;
845 if ((error = smb_transaction(sc, cmd, SMB_TRANS_NOCNT,
846 wbuf, 2, rbuf, 2, NULL)) == 0) {
847 *rdata = (u_char)rbuf[0] | ((u_char)rbuf[1] << 8);
850 mtx_unlock(&sc->io_lock);
851 sx_xunlock(&sc->call_lock);
856 ig4iic_smb_bwrite(device_t dev, u_char slave, char cmd,
857 u_char wcount, char *buf)
859 ig4iic_softc_t *sc = device_get_softc(dev);
862 sx_xlock(&sc->call_lock);
863 mtx_lock(&sc->io_lock);
865 set_slave_addr(sc, slave, 0);
866 error = smb_transaction(sc, cmd, 0,
867 buf, wcount, NULL, 0, NULL);
869 mtx_unlock(&sc->io_lock);
870 sx_xunlock(&sc->call_lock);
875 ig4iic_smb_bread(device_t dev, u_char slave, char cmd,
876 u_char *countp_char, char *buf)
878 ig4iic_softc_t *sc = device_get_softc(dev);
879 int rcount = *countp_char;
882 sx_xlock(&sc->call_lock);
883 mtx_lock(&sc->io_lock);
885 set_slave_addr(sc, slave, 0);
886 error = smb_transaction(sc, cmd, 0,
887 NULL, 0, buf, rcount, &rcount);
888 *countp_char = rcount;
890 mtx_unlock(&sc->io_lock);
891 sx_xunlock(&sc->call_lock);
896 ig4iic_smb_trans(device_t dev, int slave, char cmd, int op,
897 char *wbuf, int wcount, char *rbuf, int rcount,
900 ig4iic_softc_t *sc = device_get_softc(dev);
903 sx_xlock(&sc->call_lock);
904 mtx_lock(&sc->io_lock);
906 set_slave_addr(sc, slave, op);
907 error = smb_transaction(sc, cmd, op,
908 wbuf, wcount, rbuf, rcount, actualp);
910 mtx_unlock(&sc->io_lock);
911 sx_xunlock(&sc->call_lock);
916 * Interrupt Operation, see ig4_var.h for locking semantics.
919 ig4iic_intr(void *cookie)
921 ig4iic_softc_t *sc = cookie;
924 mtx_lock(&sc->io_lock);
925 /* reg_write(sc, IG4_REG_INTR_MASK, IG4_INTR_STOP_DET);*/
926 reg_read(sc, IG4_REG_CLR_INTR);
927 status = reg_read(sc, IG4_REG_I2C_STA);
928 while (status & IG4_STATUS_RX_NOTEMPTY) {
929 sc->rbuf[sc->rnext & IG4_RBUFMASK] =
930 (uint8_t)reg_read(sc, IG4_REG_DATA_CMD);
932 status = reg_read(sc, IG4_REG_I2C_STA);
935 mtx_unlock(&sc->io_lock);
938 #define REGDUMP(sc, reg) \
939 device_printf(sc->dev, " %-23s %08x\n", #reg, reg_read(sc, reg))
942 ig4iic_dump(ig4iic_softc_t *sc)
944 device_printf(sc->dev, "ig4iic register dump:\n");
945 REGDUMP(sc, IG4_REG_CTL);
946 REGDUMP(sc, IG4_REG_TAR_ADD);
947 REGDUMP(sc, IG4_REG_SS_SCL_HCNT);
948 REGDUMP(sc, IG4_REG_SS_SCL_LCNT);
949 REGDUMP(sc, IG4_REG_FS_SCL_HCNT);
950 REGDUMP(sc, IG4_REG_FS_SCL_LCNT);
951 REGDUMP(sc, IG4_REG_INTR_STAT);
952 REGDUMP(sc, IG4_REG_INTR_MASK);
953 REGDUMP(sc, IG4_REG_RAW_INTR_STAT);
954 REGDUMP(sc, IG4_REG_RX_TL);
955 REGDUMP(sc, IG4_REG_TX_TL);
956 REGDUMP(sc, IG4_REG_I2C_EN);
957 REGDUMP(sc, IG4_REG_I2C_STA);
958 REGDUMP(sc, IG4_REG_TXFLR);
959 REGDUMP(sc, IG4_REG_RXFLR);
960 REGDUMP(sc, IG4_REG_SDA_HOLD);
961 REGDUMP(sc, IG4_REG_TX_ABRT_SOURCE);
962 REGDUMP(sc, IG4_REG_SLV_DATA_NACK);
963 REGDUMP(sc, IG4_REG_DMA_CTRL);
964 REGDUMP(sc, IG4_REG_DMA_TDLR);
965 REGDUMP(sc, IG4_REG_DMA_RDLR);
966 REGDUMP(sc, IG4_REG_SDA_SETUP);
967 REGDUMP(sc, IG4_REG_ENABLE_STATUS);
968 REGDUMP(sc, IG4_REG_COMP_PARAM1);
969 REGDUMP(sc, IG4_REG_COMP_VER);
970 REGDUMP(sc, IG4_REG_COMP_TYPE);
971 REGDUMP(sc, IG4_REG_CLK_PARMS);
972 REGDUMP(sc, IG4_REG_RESETS);
973 REGDUMP(sc, IG4_REG_GENERAL);
974 REGDUMP(sc, IG4_REG_SW_LTR_VALUE);
975 REGDUMP(sc, IG4_REG_AUTO_LTR_VALUE);
979 DRIVER_MODULE(smbus, ig4iic, smbus_driver, smbus_devclass, NULL, NULL);