sys/dev/ichiic/ig4_iic.c

   1 /*
   2  * Copyright (c) 2014 The DragonFly Project.  All rights reserved.
   3  *
   4  * This code is derived from software contributed to The DragonFly Project
   5  * by Matthew Dillon <dillon@backplane.com> and was subsequently ported
   6  * to FreeBSD by Michael Gmelin <freebsd@grem.de>
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  *
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in
  16  *    the documentation and/or other materials provided with the
  17  *    distribution.
  18  * 3. Neither the name of The DragonFly Project nor the names of its
  19  *    contributors may be used to endorse or promote products derived
  20  *    from this software without specific, prior written permission.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  23  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  24  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  25  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
  26  * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  27  * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
  28  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  30  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  31  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  32  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  33  * SUCH DAMAGE.
  34  */
  35
  36 #include <sys/cdefs.h>
  37 __FBSDID("$FreeBSD$");
  38
  39 /*
  40  * Intel fourth generation mobile cpus integrated I2C device.
  41  *
  42  * See ig4_reg.h for datasheet reference and notes.
  43  * See ig4_var.h for locking semantics.
  44  */
  45
  46 #include "opt_acpi.h"
  47
  48 #include <sys/param.h>
  49 #include <sys/systm.h>
  50 #include <sys/kernel.h>
  51 #include <sys/module.h>
  52 #include <sys/errno.h>
  53 #include <sys/kdb.h>
  54 #include <sys/lock.h>
  55 #include <sys/mutex.h>
  56 #include <sys/proc.h>
  57 #include <sys/sx.h>
  58 #include <sys/syslog.h>
  59 #include <sys/bus.h>
  60 #include <sys/sysctl.h>
  61
  62 #include <machine/bus.h>
  63 #include <sys/rman.h>
  64
  65 #ifdef DEV_ACPI
  66 #include <contrib/dev/acpica/include/acpi.h>
  67 #include <contrib/dev/acpica/include/accommon.h>
  68 #include <dev/acpica/acpivar.h>
  69 #endif
  70
  71 #include <dev/iicbus/iicbus.h>
  72 #include <dev/iicbus/iiconf.h>
  73
  74 #include <dev/ichiic/ig4_reg.h>
  75 #include <dev/ichiic/ig4_var.h>
  76
  77 #define DO_POLL(sc)     (cold || kdb_active || SCHEDULER_STOPPED() || sc->poll)
  78
  79 /*
  80  * tLOW, tHIGH periods of the SCL clock and maximal falling time of both
  81  * lines are taken from I2C specifications.
  82  */
  83 #define IG4_SPEED_STD_THIGH     4000    /* nsec */
  84 #define IG4_SPEED_STD_TLOW      4700    /* nsec */
  85 #define IG4_SPEED_STD_TF_MAX    300     /* nsec */
  86 #define IG4_SPEED_FAST_THIGH    600     /* nsec */
  87 #define IG4_SPEED_FAST_TLOW     1300    /* nsec */
  88 #define IG4_SPEED_FAST_TF_MAX   300     /* nsec */
  89
  90 /*
  91  * Ig4 hardware parameters except Haswell are taken from intel_lpss driver
  92  */
  93 static const struct ig4_hw ig4iic_hw[] = {
  94         [IG4_HASWELL] = {
  95                 .ic_clock_rate = 100,   /* MHz */
  96                 .sda_hold_time = 90,    /* nsec */
  97                 .txfifo_depth = 32,
  98                 .rxfifo_depth = 32,
  99         },
 100         [IG4_ATOM] = {
 101                 .ic_clock_rate = 100,
 102                 .sda_fall_time = 280,
 103                 .scl_fall_time = 240,
 104                 .sda_hold_time = 60,
 105                 .txfifo_depth = 32,
 106                 .rxfifo_depth = 32,
 107         },
 108         [IG4_SKYLAKE] = {
 109                 .ic_clock_rate = 120,
 110                 .sda_hold_time = 230,
 111         },
 112         [IG4_APL] = {
 113                 .ic_clock_rate = 133,
 114                 .sda_fall_time = 171,
 115                 .scl_fall_time = 208,
 116                 .sda_hold_time = 207,
 117         },
 118         [IG4_CANNONLAKE] = {
 119                 .ic_clock_rate = 216,
 120                 .sda_hold_time = 230,
 121         },
 122 };
 123
 124 static int ig4iic_set_config(ig4iic_softc_t *sc, bool reset);
 125 static driver_filter_t ig4iic_intr;
 126 static void ig4iic_dump(ig4iic_softc_t *sc);
 127
 128 static int ig4_dump;
 129 SYSCTL_INT(_debug, OID_AUTO, ig4_dump, CTLFLAG_RW,
 130            &ig4_dump, 0, "Dump controller registers");
 131
 132 /*
 133  * Clock registers initialization control
 134  * 0 - Try read clock registers from ACPI and fallback to p.1.
 135  * 1 - Calculate values based on controller type (IC clock rate).
 136  * 2 - Use values inherited from DragonflyBSD driver (old behavior).
 137  * 3 - Keep clock registers intact.
 138  */
 139 static int ig4_timings;
 140 SYSCTL_INT(_debug, OID_AUTO, ig4_timings, CTLFLAG_RDTUN, &ig4_timings, 0,
 141     "Controller timings 0=ACPI, 1=predefined, 2=legacy, 3=do not change");
 142
 143 /*
 144  * Low-level inline support functions
 145  */
 146 static __inline void
 147 reg_write(ig4iic_softc_t *sc, uint32_t reg, uint32_t value)
 148 {
 149         bus_write_4(sc->regs_res, reg, value);
 150         bus_barrier(sc->regs_res, reg, 4, BUS_SPACE_BARRIER_WRITE);
 151 }
 152
 153 static __inline uint32_t
 154 reg_read(ig4iic_softc_t *sc, uint32_t reg)
 155 {
 156         uint32_t value;
 157
 158         bus_barrier(sc->regs_res, reg, 4, BUS_SPACE_BARRIER_READ);
 159         value = bus_read_4(sc->regs_res, reg);
 160         return (value);
 161 }
 162
 163 static void
 164 ig4iic_set_intr_mask(ig4iic_softc_t *sc, uint32_t val)
 165 {
 166         if (sc->intr_mask != val) {
 167                 reg_write(sc, IG4_REG_INTR_MASK, val);
 168                 sc->intr_mask = val;
 169         }
 170 }
 171
 172 static int
 173 intrstat2iic(ig4iic_softc_t *sc, uint32_t val)
 174 {
 175         uint32_t src;
 176
 177         if (val & IG4_INTR_RX_UNDER)
 178                 reg_read(sc, IG4_REG_CLR_RX_UNDER);
 179         if (val & IG4_INTR_RX_OVER)
 180                 reg_read(sc, IG4_REG_CLR_RX_OVER);
 181         if (val & IG4_INTR_TX_OVER)
 182                 reg_read(sc, IG4_REG_CLR_TX_OVER);
 183
 184         if (val & IG4_INTR_TX_ABRT) {
 185                 src = reg_read(sc, IG4_REG_TX_ABRT_SOURCE);
 186                 reg_read(sc, IG4_REG_CLR_TX_ABORT);
 187                 /* User-requested abort. Not really a error */
 188                 if (src & IG4_ABRTSRC_TRANSFER)
 189                         return (IIC_ESTATUS);
 190                 /* Master has lost arbitration */
 191                 if (src & IG4_ABRTSRC_ARBLOST)
 192                         return (IIC_EBUSBSY);
 193                 /* Did not receive an acknowledge from the remote slave */
 194                 if (src & (IG4_ABRTSRC_TXNOACK_ADDR7 |
 195                            IG4_ABRTSRC_TXNOACK_ADDR10_1 |
 196                            IG4_ABRTSRC_TXNOACK_ADDR10_2 |
 197                            IG4_ABRTSRC_TXNOACK_DATA |
 198                            IG4_ABRTSRC_GENCALL_NOACK))
 199                         return (IIC_ENOACK);
 200                 /* Programming errors */
 201                 if (src & (IG4_ABRTSRC_GENCALL_READ |
 202                            IG4_ABRTSRC_NORESTART_START |
 203                            IG4_ABRTSRC_NORESTART_10))
 204                         return (IIC_ENOTSUPP);
 205                 /* Other errors */
 206                 if (src & IG4_ABRTSRC_ACKED_START)
 207                         return (IIC_EBUSERR);
 208         }
 209         /*
 210          * TX_OVER, RX_OVER and RX_UNDER are caused by wrong RX/TX FIFO depth
 211          * detection or driver's read/write pipelining errors.
 212          */
 213         if (val & (IG4_INTR_TX_OVER | IG4_INTR_RX_OVER))
 214                 return (IIC_EOVERFLOW);
 215         if (val & IG4_INTR_RX_UNDER)
 216                 return (IIC_EUNDERFLOW);
 217
 218         return (IIC_NOERR);
 219 }
 220
 221 /*
 222  * Enable or disable the controller and wait for the controller to acknowledge
 223  * the state change.
 224  */
 225 static int
 226 set_controller(ig4iic_softc_t *sc, uint32_t ctl)
 227 {
 228         int retry;
 229         int error;
 230         uint32_t v;
 231
 232         /*
 233          * When the controller is enabled, interrupt on STOP detect
 234          * or receive character ready and clear pending interrupts.
 235          */
 236         ig4iic_set_intr_mask(sc, 0);
 237         if (ctl & IG4_I2C_ENABLE)
 238                 reg_read(sc, IG4_REG_CLR_INTR);
 239
 240         reg_write(sc, IG4_REG_I2C_EN, ctl);
 241         error = IIC_ETIMEOUT;
 242
 243         for (retry = 100; retry > 0; --retry) {
 244                 v = reg_read(sc, IG4_REG_ENABLE_STATUS);
 245                 if (((v ^ ctl) & IG4_I2C_ENABLE) == 0) {
 246                         error = 0;
 247                         break;
 248                 }
 249                 pause("i2cslv", 1);
 250         }
 251         return (error);
 252 }
 253
 254 /*
 255  * Wait up to 25ms for the requested interrupt using a 25uS polling loop.
 256  */
 257 static int
 258 wait_intr(ig4iic_softc_t *sc, uint32_t intr)
 259 {
 260         uint32_t v;
 261         int error;
 262         int txlvl = -1;
 263         u_int count_us = 0;
 264         u_int limit_us = 25000; /* 25ms */
 265
 266         for (;;) {
 267                 /*
 268                  * Check requested status
 269                  */
 270                 v = reg_read(sc, IG4_REG_RAW_INTR_STAT);
 271                 error = intrstat2iic(sc, v & IG4_INTR_ERR_MASK);
 272                 if (error || (v & intr))
 273                         break;
 274
 275                 /*
 276                  * When waiting for the transmit FIFO to become empty,
 277                  * reset the timeout if we see a change in the transmit
 278                  * FIFO level as progress is being made.
 279                  */
 280                 if (intr & (IG4_INTR_TX_EMPTY | IG4_INTR_STOP_DET)) {
 281                         v = reg_read(sc, IG4_REG_TXFLR) & IG4_FIFOLVL_MASK;
 282                         if (txlvl != v) {
 283                                 txlvl = v;
 284                                 count_us = 0;
 285                         }
 286                 }
 287
 288                 /*
 289                  * Stop if we've run out of time.
 290                  */
 291                 if (count_us >= limit_us) {
 292                         error = IIC_ETIMEOUT;
 293                         break;
 294                 }
 295
 296                 /*
 297                  * When polling is not requested let the interrupt do its work.
 298                  */
 299                 if (!DO_POLL(sc)) {
 300                         mtx_lock_spin(&sc->io_lock);
 301                         ig4iic_set_intr_mask(sc, intr | IG4_INTR_ERR_MASK);
 302                         msleep_spin(sc, &sc->io_lock, "i2cwait",
 303                                   (hz + 99) / 100); /* sleep up to 10ms */
 304                         ig4iic_set_intr_mask(sc, 0);
 305                         mtx_unlock_spin(&sc->io_lock);
 306                         count_us += 10000;
 307                 } else {
 308                         DELAY(25);
 309                         count_us += 25;
 310                 }
 311         }
 312
 313         return (error);
 314 }
 315
 316 /*
 317  * Set the slave address.  The controller must be disabled when
 318  * changing the address.
 319  *
 320  * This operation does not issue anything to the I2C bus but sets
 321  * the target address for when the controller later issues a START.
 322  */
 323 static void
 324 set_slave_addr(ig4iic_softc_t *sc, uint8_t slave)
 325 {
 326         uint32_t tar;
 327         uint32_t ctl;
 328         int use_10bit;
 329
 330         use_10bit = 0;
 331         if (sc->slave_valid && sc->last_slave == slave &&
 332             sc->use_10bit == use_10bit) {
 333                 return;
 334         }
 335         sc->use_10bit = use_10bit;
 336
 337         /*
 338          * Wait for TXFIFO to drain before disabling the controller.
 339          */
 340         wait_intr(sc, IG4_INTR_TX_EMPTY);
 341
 342         set_controller(sc, 0);
 343         ctl = reg_read(sc, IG4_REG_CTL);
 344         ctl &= ~IG4_CTL_10BIT;
 345         ctl |= IG4_CTL_RESTARTEN;
 346
 347         tar = slave;
 348         if (sc->use_10bit) {
 349                 tar |= IG4_TAR_10BIT;
 350                 ctl |= IG4_CTL_10BIT;
 351         }
 352         reg_write(sc, IG4_REG_CTL, ctl);
 353         reg_write(sc, IG4_REG_TAR_ADD, tar);
 354         set_controller(sc, IG4_I2C_ENABLE);
 355         sc->slave_valid = 1;
 356         sc->last_slave = slave;
 357 }
 358
 359 /*
 360  *                              IICBUS API FUNCTIONS
 361  */
 362 static int
 363 ig4iic_xfer_start(ig4iic_softc_t *sc, uint16_t slave, bool repeated_start)
 364 {
 365         set_slave_addr(sc, slave >> 1);
 366
 367         if (!repeated_start) {
 368                 /*
 369                  * Clear any previous TX/RX FIFOs overflow/underflow bits
 370                  * and I2C bus STOP condition.
 371                  */
 372                 reg_read(sc, IG4_REG_CLR_INTR);
 373         }
 374
 375         return (0);
 376 }
 377
 378 static bool
 379 ig4iic_xfer_is_started(ig4iic_softc_t *sc)
 380 {
 381         /*
 382          * It requires that no IG4_REG_CLR_INTR or IG4_REG_CLR_START/STOP_DET
 383          * register reads is issued after START condition.
 384          */
 385         return ((reg_read(sc, IG4_REG_RAW_INTR_STAT) &
 386             (IG4_INTR_START_DET | IG4_INTR_STOP_DET)) == IG4_INTR_START_DET);
 387 }
 388
 389 static int
 390 ig4iic_xfer_abort(ig4iic_softc_t *sc)
 391 {
 392         int error;
 393
 394         /* Request send of STOP condition and flush of TX FIFO */
 395         set_controller(sc, IG4_I2C_ABORT | IG4_I2C_ENABLE);
 396         /*
 397          * Wait for the TX_ABRT interrupt with ABRTSRC_TRANSFER
 398          * bit set in TX_ABRT_SOURCE register.
 399          */
 400         error = wait_intr(sc, IG4_INTR_STOP_DET);
 401         set_controller(sc, IG4_I2C_ENABLE);
 402
 403         return (error == IIC_ESTATUS ? 0 : error);
 404 }
 405
 406 /*
 407  * Amount of unread data before next burst to get better I2C bus utilization.
 408  * 2 bytes is enough in FAST mode. 8 bytes is better in FAST+ and HIGH modes.
 409  * Intel-recommended value is 16 for DMA transfers with 64-byte depth FIFOs.
 410  */
 411 #define IG4_FIFO_LOWAT  2
 412
 413 static int
 414 ig4iic_read(ig4iic_softc_t *sc, uint8_t *buf, uint16_t len,
 415     bool repeated_start, bool stop)
 416 {
 417         uint32_t cmd;
 418         int requested = 0;
 419         int received = 0;
 420         int burst, target, lowat = 0;
 421         int error;
 422
 423         if (len == 0)
 424                 return (0);
 425
 426         while (received < len) {
 427                 burst = sc->cfg.txfifo_depth -
 428                     (reg_read(sc, IG4_REG_TXFLR) & IG4_FIFOLVL_MASK);
 429                 if (burst <= 0) {
 430                         error = wait_intr(sc, IG4_INTR_TX_EMPTY);
 431                         if (error)
 432                                 break;
 433                         burst = sc->cfg.txfifo_depth;
 434                 }
 435                 /* Ensure we have enough free space in RXFIFO */
 436                 burst = MIN(burst, sc->cfg.rxfifo_depth - lowat);
 437                 target = MIN(requested + burst, (int)len);
 438                 while (requested < target) {
 439                         cmd = IG4_DATA_COMMAND_RD;
 440                         if (repeated_start && requested == 0)
 441                                 cmd |= IG4_DATA_RESTART;
 442                         if (stop && requested == len - 1)
 443                                 cmd |= IG4_DATA_STOP;
 444                         reg_write(sc, IG4_REG_DATA_CMD, cmd);
 445                         requested++;
 446                 }
 447                 /* Leave some data queued to maintain the hardware pipeline */
 448                 lowat = 0;
 449                 if (requested != len && requested - received > IG4_FIFO_LOWAT)
 450                         lowat = IG4_FIFO_LOWAT;
 451                 /* After TXFLR fills up, clear it by reading available data */
 452                 while (received < requested - lowat) {
 453                         burst = MIN((int)len - received,
 454                             reg_read(sc, IG4_REG_RXFLR) & IG4_FIFOLVL_MASK);
 455                         if (burst > 0) {
 456                                 while (burst--)
 457                                         buf[received++] = 0xFF &
 458                                             reg_read(sc, IG4_REG_DATA_CMD);
 459                         } else {
 460                                 error = wait_intr(sc, IG4_INTR_RX_FULL);
 461                                 if (error)
 462                                         goto out;
 463                         }
 464                 }
 465         }
 466 out:
 467         return (error);
 468 }
 469
 470 static int
 471 ig4iic_write(ig4iic_softc_t *sc, uint8_t *buf, uint16_t len,
 472     bool repeated_start, bool stop)
 473 {
 474         uint32_t cmd;
 475         int sent = 0;
 476         int burst, target;
 477         int error;
 478         bool lowat_set = false;
 479
 480         if (len == 0)
 481                 return (0);
 482
 483         while (sent < len) {
 484                 burst = sc->cfg.txfifo_depth -
 485                     (reg_read(sc, IG4_REG_TXFLR) & IG4_FIFOLVL_MASK);
 486                 target = MIN(sent + burst, (int)len);
 487                 /* Leave some data queued to maintain the hardware pipeline */
 488                 if (!lowat_set && target != len) {
 489                         lowat_set = true;
 490                         reg_write(sc, IG4_REG_TX_TL, IG4_FIFO_LOWAT);
 491                 }
 492                 while(sent < target) {
 493                         cmd = buf[sent];
 494                         if (repeated_start && sent == 0)
 495                                 cmd |= IG4_DATA_RESTART;
 496                         if (stop && sent == len - 1)
 497                                 cmd |= IG4_DATA_STOP;
 498                         reg_write(sc, IG4_REG_DATA_CMD, cmd);
 499                         sent++;
 500                 }
 501                 if (sent < len) {
 502                         error = wait_intr(sc, IG4_INTR_TX_EMPTY);
 503                         if (error)
 504                                 break;
 505                 }
 506         }
 507         if (lowat_set)
 508                 reg_write(sc, IG4_REG_TX_TL, 0);
 509
 510         return (error);
 511 }
 512
 513 int
 514 ig4iic_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
 515 {
 516         ig4iic_softc_t *sc = device_get_softc(dev);
 517         const char *reason = NULL;
 518         uint32_t i;
 519         int error;
 520         int unit;
 521         bool rpstart;
 522         bool stop;
 523         bool allocated;
 524
 525         /*
 526          * The hardware interface imposes limits on allowed I2C messages.
 527          * It is not possible to explicitly send a start or stop.
 528          * They are automatically sent (or not sent, depending on the
 529          * configuration) when a data byte is transferred.
 530          * For this reason it's impossible to send a message with no data
 531          * at all (like an SMBus quick message).
 532          * The start condition is automatically generated after the stop
 533          * condition, so it's impossible to not have a start after a stop.
 534          * The repeated start condition is automatically sent if a change
 535          * of the transfer direction happens, so it's impossible to have
 536          * a change of direction without a (repeated) start.
 537          * The repeated start can be forced even without the change of
 538          * direction.
 539          * Changing the target slave address requires resetting the hardware
 540          * state, so it's impossible to do that without the stop followed
 541          * by the start.
 542          */
 543         for (i = 0; i < nmsgs; i++) {
 544 #if 0
 545                 if (i == 0 && (msgs[i].flags & IIC_M_NOSTART) != 0) {
 546                         reason = "first message without start";
 547                         break;
 548                 }
 549                 if (i == nmsgs - 1 && (msgs[i].flags & IIC_M_NOSTOP) != 0) {
 550                         reason = "last message without stop";
 551                         break;
 552                 }
 553 #endif
 554                 if (msgs[i].len == 0) {
 555                         reason = "message with no data";
 556                         break;
 557                 }
 558                 if (i > 0) {
 559                         if ((msgs[i].flags & IIC_M_NOSTART) != 0 &&
 560                             (msgs[i - 1].flags & IIC_M_NOSTOP) == 0) {
 561                                 reason = "stop not followed by start";
 562                                 break;
 563                         }
 564                         if ((msgs[i - 1].flags & IIC_M_NOSTOP) != 0 &&
 565                             msgs[i].slave != msgs[i - 1].slave) {
 566                                 reason = "change of slave without stop";
 567                                 break;
 568                         }
 569                         if ((msgs[i].flags & IIC_M_NOSTART) != 0 &&
 570                             (msgs[i].flags & IIC_M_RD) !=
 571                             (msgs[i - 1].flags & IIC_M_RD)) {
 572                                 reason = "change of direction without repeated"
 573                                     " start";
 574                                 break;
 575                         }
 576                 }
 577         }
 578         if (reason != NULL) {
 579                 if (bootverbose)
 580                         device_printf(dev, "%s\n", reason);
 581                 return (IIC_ENOTSUPP);
 582         }
 583
 584         /* Check if device is already allocated with iicbus_request_bus() */
 585         allocated = sx_xlocked(&sc->call_lock) != 0;
 586         if (!allocated)
 587                 sx_xlock(&sc->call_lock);
 588
 589         /* Debugging - dump registers. */
 590         if (ig4_dump) {
 591                 unit = device_get_unit(dev);
 592                 if (ig4_dump & (1 << unit)) {
 593                         ig4_dump &= ~(1 << unit);
 594                         ig4iic_dump(sc);
 595                 }
 596         }
 597
 598         /*
 599          * Clear any previous abort condition that may have been holding
 600          * the txfifo in reset.
 601          */
 602         reg_read(sc, IG4_REG_CLR_TX_ABORT);
 603
 604         rpstart = false;
 605         error = 0;
 606         for (i = 0; i < nmsgs; i++) {
 607                 if ((msgs[i].flags & IIC_M_NOSTART) == 0) {
 608                         error = ig4iic_xfer_start(sc, msgs[i].slave, rpstart);
 609                 } else {
 610                         if (!sc->slave_valid ||
 611                             (msgs[i].slave >> 1) != sc->last_slave) {
 612                                 device_printf(dev, "start condition suppressed"
 613                                     "but slave address is not set up");
 614                                 error = EINVAL;
 615                                 break;
 616                         }
 617                         rpstart = false;
 618                 }
 619                 if (error != 0)
 620                         break;
 621
 622                 stop = (msgs[i].flags & IIC_M_NOSTOP) == 0;
 623                 if (msgs[i].flags & IIC_M_RD)
 624                         error = ig4iic_read(sc, msgs[i].buf, msgs[i].len,
 625                             rpstart, stop);
 626                 else
 627                         error = ig4iic_write(sc, msgs[i].buf, msgs[i].len,
 628                             rpstart, stop);
 629
 630                 /* Wait for error or stop condition occurred on the I2C bus */
 631                 if (stop && error == 0) {
 632                         error = wait_intr(sc, IG4_INTR_STOP_DET);
 633                         if (error == 0)
 634                                 reg_read(sc, IG4_REG_CLR_INTR);
 635                 }
 636
 637                 if (error != 0) {
 638                         /*
 639                          * Send STOP condition if it's not done yet and flush
 640                          * both FIFOs. Do a controller soft reset if transfer
 641                          * abort is failed.
 642                          */
 643                         if (ig4iic_xfer_is_started(sc) &&
 644                             ig4iic_xfer_abort(sc) != 0) {
 645                                 device_printf(sc->dev, "Failed to abort "
 646                                     "transfer. Do the controller reset.\n");
 647                                 ig4iic_set_config(sc, true);
 648                         } else {
 649                                 while (reg_read(sc, IG4_REG_I2C_STA) &
 650                                     IG4_STATUS_RX_NOTEMPTY)
 651                                         reg_read(sc, IG4_REG_DATA_CMD);
 652                                 reg_read(sc, IG4_REG_TX_ABRT_SOURCE);
 653                                 reg_read(sc, IG4_REG_CLR_INTR);
 654                         }
 655                         break;
 656                 }
 657
 658                 rpstart = !stop;
 659         }
 660
 661         if (!allocated)
 662                 sx_unlock(&sc->call_lock);
 663         return (error);
 664 }
 665
 666 int
 667 ig4iic_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
 668 {
 669         ig4iic_softc_t *sc = device_get_softc(dev);
 670         bool allocated;
 671
 672         allocated = sx_xlocked(&sc->call_lock) != 0;
 673         if (!allocated)
 674                 sx_xlock(&sc->call_lock);
 675
 676         /* TODO handle speed configuration? */
 677         if (oldaddr != NULL)
 678                 *oldaddr = sc->last_slave << 1;
 679         set_slave_addr(sc, addr >> 1);
 680         if (addr == IIC_UNKNOWN)
 681                 sc->slave_valid = false;
 682
 683         if (!allocated)
 684                 sx_unlock(&sc->call_lock);
 685         return (0);
 686 }
 687
 688 int
 689 ig4iic_callback(device_t dev, int index, caddr_t data)
 690 {
 691         ig4iic_softc_t *sc = device_get_softc(dev);
 692         int error = 0;
 693         int how;
 694
 695         switch (index) {
 696         case IIC_REQUEST_BUS:
 697                 /* force polling if ig4iic is requested with IIC_DONTWAIT */
 698                 how = *(int *)data;
 699                 if ((how & IIC_WAIT) == 0) {
 700                         if (sx_try_xlock(&sc->call_lock) == 0)
 701                                 error = IIC_EBUSBSY;
 702                         else
 703                                 sc->poll = true;
 704                 } else
 705                         sx_xlock(&sc->call_lock);
 706                 break;
 707
 708         case IIC_RELEASE_BUS:
 709                 sc->poll = false;
 710                 sx_unlock(&sc->call_lock);
 711                 break;
 712
 713         default:
 714                 error = errno2iic(EINVAL);
 715         }
 716
 717         return (error);
 718 }
 719
 720 /*
 721  * Clock register values can be calculated with following rough equations:
 722  * SCL_HCNT = ceil(IC clock rate * tHIGH)
 723  * SCL_LCNT = ceil(IC clock rate * tLOW)
 724  * SDA_HOLD = ceil(IC clock rate * SDA hold time)
 725  * Precise equations take signal's falling, rising and spike suppression
 726  * times in to account. They can be found in Synopsys or Intel documentation.
 727  *
 728  * Here we snarf formulas and defaults from Linux driver to be able to use
 729  * timing values provided by Intel LPSS driver "as is".
 730  */
 731 static int
 732 ig4iic_clk_params(const struct ig4_hw *hw, int speed,
 733     uint16_t *scl_hcnt, uint16_t *scl_lcnt, uint16_t *sda_hold)
 734 {
 735         uint32_t thigh, tlow, tf_max;   /* nsec */
 736         uint32_t sda_fall_time;         /* nsec */
 737         uint32_t scl_fall_time;         /* nsec */
 738
 739         switch (speed) {
 740         case IG4_CTL_SPEED_STD:
 741                 thigh = IG4_SPEED_STD_THIGH;
 742                 tlow = IG4_SPEED_STD_TLOW;
 743                 tf_max = IG4_SPEED_STD_TF_MAX;
 744                 break;
 745
 746         case IG4_CTL_SPEED_FAST:
 747                 thigh = IG4_SPEED_FAST_THIGH;
 748                 tlow = IG4_SPEED_FAST_TLOW;
 749                 tf_max = IG4_SPEED_FAST_TF_MAX;
 750                 break;
 751
 752         default:
 753                 return (EINVAL);
 754         }
 755
 756         /* Use slowest falling time defaults to be on the safe side */
 757         sda_fall_time = hw->sda_fall_time == 0 ? tf_max : hw->sda_fall_time;
 758         *scl_hcnt = (uint16_t)
 759             ((hw->ic_clock_rate * (thigh + sda_fall_time) + 500) / 1000 - 3);
 760
 761         scl_fall_time = hw->scl_fall_time == 0 ? tf_max : hw->scl_fall_time;
 762         *scl_lcnt = (uint16_t)
 763             ((hw->ic_clock_rate * (tlow + scl_fall_time) + 500) / 1000 - 1);
 764
 765         /*
 766          * There is no "known good" default value for tHD;DAT so keep SDA_HOLD
 767          * intact if sda_hold_time value is not provided.
 768          */
 769         if (hw->sda_hold_time != 0)
 770                 *sda_hold = (uint16_t)
 771                     ((hw->ic_clock_rate * hw->sda_hold_time + 500) / 1000);
 772
 773         return (0);
 774 }
 775
 776 #ifdef DEV_ACPI
 777 static ACPI_STATUS
 778 ig4iic_acpi_params(ACPI_HANDLE handle, char *method,
 779     uint16_t *scl_hcnt, uint16_t *scl_lcnt, uint16_t *sda_hold)
 780 {
 781         ACPI_BUFFER buf;
 782         ACPI_OBJECT *obj, *elems;
 783         ACPI_STATUS status;
 784
 785         buf.Pointer = NULL;
 786         buf.Length = ACPI_ALLOCATE_BUFFER;
 787
 788         status = AcpiEvaluateObject(handle, method, NULL, &buf);
 789         if (ACPI_FAILURE(status))
 790                 return (status);
 791
 792         status = AE_TYPE;
 793         obj = (ACPI_OBJECT *)buf.Pointer;
 794         if (obj->Type == ACPI_TYPE_PACKAGE && obj->Package.Count == 3) {
 795                 elems = obj->Package.Elements;
 796                 *scl_hcnt = elems[0].Integer.Value & IG4_SCL_CLOCK_MASK;
 797                 *scl_lcnt = elems[1].Integer.Value & IG4_SCL_CLOCK_MASK;
 798                 *sda_hold = elems[2].Integer.Value & IG4_SDA_TX_HOLD_MASK;
 799                 status = AE_OK;
 800         }
 801
 802         AcpiOsFree(obj);
 803
 804         return (status);
 805 }
 806 #endif /* DEV_ACPI */
 807
 808 static void
 809 ig4iic_get_config(ig4iic_softc_t *sc)
 810 {
 811         const struct ig4_hw *hw;
 812         uint32_t v;
 813 #ifdef DEV_ACPI
 814         ACPI_HANDLE handle;
 815 #endif
 816         /* Fetch default hardware config from controller */
 817         sc->cfg.version = reg_read(sc, IG4_REG_COMP_VER);
 818         sc->cfg.bus_speed = reg_read(sc, IG4_REG_CTL) & IG4_CTL_SPEED_MASK;
 819         sc->cfg.ss_scl_hcnt =
 820             reg_read(sc, IG4_REG_SS_SCL_HCNT) & IG4_SCL_CLOCK_MASK;
 821         sc->cfg.ss_scl_lcnt =
 822             reg_read(sc, IG4_REG_SS_SCL_LCNT) & IG4_SCL_CLOCK_MASK;
 823         sc->cfg.fs_scl_hcnt =
 824             reg_read(sc, IG4_REG_FS_SCL_HCNT) & IG4_SCL_CLOCK_MASK;
 825         sc->cfg.fs_scl_lcnt =
 826             reg_read(sc, IG4_REG_FS_SCL_LCNT) & IG4_SCL_CLOCK_MASK;
 827         sc->cfg.ss_sda_hold = sc->cfg.fs_sda_hold =
 828             reg_read(sc, IG4_REG_SDA_HOLD) & IG4_SDA_TX_HOLD_MASK;
 829
 830         if (sc->cfg.bus_speed != IG4_CTL_SPEED_STD)
 831                 sc->cfg.bus_speed = IG4_CTL_SPEED_FAST;
 832
 833         /* REG_COMP_PARAM1 is not documented in latest Intel specs */
 834         if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) {
 835                 v = reg_read(sc, IG4_REG_COMP_PARAM1);
 836                 if (IG4_PARAM1_TXFIFO_DEPTH(v) != 0)
 837                         sc->cfg.txfifo_depth = IG4_PARAM1_TXFIFO_DEPTH(v);
 838                 if (IG4_PARAM1_RXFIFO_DEPTH(v) != 0)
 839                         sc->cfg.rxfifo_depth = IG4_PARAM1_RXFIFO_DEPTH(v);
 840         } else {
 841                 /*
 842                  * Hardware does not allow FIFO Threshold Levels value to be
 843                  * set larger than the depth of the buffer. If an attempt is
 844                  * made to do that, the actual value set will be the maximum
 845                  * depth of the buffer.
 846                  */
 847                 v = reg_read(sc, IG4_REG_TX_TL);
 848                 reg_write(sc, IG4_REG_TX_TL, v | IG4_FIFO_MASK);
 849                 sc->cfg.txfifo_depth =
 850                     (reg_read(sc, IG4_REG_TX_TL) & IG4_FIFO_MASK) + 1;
 851                 reg_write(sc, IG4_REG_TX_TL, v);
 852                 v = reg_read(sc, IG4_REG_RX_TL);
 853                 reg_write(sc, IG4_REG_RX_TL, v | IG4_FIFO_MASK);
 854                 sc->cfg.rxfifo_depth =
 855                     (reg_read(sc, IG4_REG_RX_TL) & IG4_FIFO_MASK) + 1;
 856                 reg_write(sc, IG4_REG_RX_TL, v);
 857         }
 858
 859         /* Override hardware config with IC_clock-based counter values */
 860         if (ig4_timings < 2 && sc->version < nitems(ig4iic_hw)) {
 861                 hw = &ig4iic_hw[sc->version];
 862                 sc->cfg.bus_speed = IG4_CTL_SPEED_FAST;
 863                 ig4iic_clk_params(hw, IG4_CTL_SPEED_STD, &sc->cfg.ss_scl_hcnt,
 864                     &sc->cfg.ss_scl_lcnt, &sc->cfg.ss_sda_hold);
 865                 ig4iic_clk_params(hw, IG4_CTL_SPEED_FAST, &sc->cfg.fs_scl_hcnt,
 866                     &sc->cfg.fs_scl_lcnt, &sc->cfg.fs_sda_hold);
 867                 if (hw->txfifo_depth != 0)
 868                         sc->cfg.txfifo_depth = hw->txfifo_depth;
 869                 if (hw->rxfifo_depth != 0)
 870                         sc->cfg.rxfifo_depth = hw->rxfifo_depth;
 871         } else if (ig4_timings == 2) {
 872                 /*
 873                  * Timings of original ig4 driver:
 874                  * Program based on a 25000 Hz clock.  This is a bit of a
 875                  * hack (obviously).  The defaults are 400 and 470 for standard
 876                  * and 60 and 130 for fast.  The defaults for standard fail
 877                  * utterly (presumably cause an abort) because the clock time
 878                  * is ~18.8ms by default.  This brings it down to ~4ms.
 879                  */
 880                 sc->cfg.bus_speed = IG4_CTL_SPEED_STD;
 881                 sc->cfg.ss_scl_hcnt = sc->cfg.fs_scl_hcnt = 100;
 882                 sc->cfg.ss_scl_lcnt = sc->cfg.fs_scl_lcnt = 125;
 883                 if (sc->version == IG4_SKYLAKE)
 884                         sc->cfg.ss_sda_hold = sc->cfg.fs_sda_hold = 28;
 885         }
 886
 887 #ifdef DEV_ACPI
 888         /* Evaluate SSCN and FMCN ACPI methods to fetch timings */
 889         if (ig4_timings == 0 && (handle = acpi_get_handle(sc->dev)) != NULL) {
 890                 ig4iic_acpi_params(handle, "SSCN", &sc->cfg.ss_scl_hcnt,
 891                     &sc->cfg.ss_scl_lcnt, &sc->cfg.ss_sda_hold);
 892                 ig4iic_acpi_params(handle, "FMCN", &sc->cfg.fs_scl_hcnt,
 893                     &sc->cfg.fs_scl_lcnt, &sc->cfg.fs_sda_hold);
 894         }
 895 #endif
 896
 897         if (bootverbose) {
 898                 device_printf(sc->dev, "Controller parameters:\n");
 899                 printf("  Speed: %s\n",
 900                     sc->cfg.bus_speed == IG4_CTL_SPEED_STD ? "Std" : "Fast");
 901                 printf("  Regs:  HCNT  :LCNT  :SDAHLD\n");
 902                 printf("  Std:   0x%04hx:0x%04hx:0x%04hx\n",
 903                     sc->cfg.ss_scl_hcnt, sc->cfg.ss_scl_lcnt,
 904                     sc->cfg.ss_sda_hold);
 905                 printf("  Fast:  0x%04hx:0x%04hx:0x%04hx\n",
 906                     sc->cfg.fs_scl_hcnt, sc->cfg.fs_scl_lcnt,
 907                     sc->cfg.fs_sda_hold);
 908                 printf("  FIFO:  RX:0x%04x: TX:0x%04x\n",
 909                     sc->cfg.rxfifo_depth, sc->cfg.txfifo_depth);
 910         }
 911 }
 912
 913 static int
 914 ig4iic_set_config(ig4iic_softc_t *sc, bool reset)
 915 {
 916         uint32_t v;
 917
 918         v = reg_read(sc, IG4_REG_DEVIDLE_CTRL);
 919         if (IG4_HAS_ADDREGS(sc->version) && (v & IG4_RESTORE_REQUIRED)) {
 920                 reg_write(sc, IG4_REG_DEVIDLE_CTRL, IG4_DEVICE_IDLE | IG4_RESTORE_REQUIRED);
 921                 reg_write(sc, IG4_REG_DEVIDLE_CTRL, 0);
 922                 pause("i2crst", 1);
 923                 reset = true;
 924         }
 925
 926         if ((sc->version == IG4_HASWELL || sc->version == IG4_ATOM) && reset) {
 927                 reg_write(sc, IG4_REG_RESETS_HSW, IG4_RESETS_ASSERT_HSW);
 928                 reg_write(sc, IG4_REG_RESETS_HSW, IG4_RESETS_DEASSERT_HSW);
 929         } else if (IG4_HAS_ADDREGS(sc->version) && reset) {
 930                 reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_ASSERT_SKL);
 931                 reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_DEASSERT_SKL);
 932         }
 933
 934         if (sc->version == IG4_ATOM)
 935                 v = reg_read(sc, IG4_REG_COMP_TYPE);
 936
 937         if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) {
 938                 v = reg_read(sc, IG4_REG_COMP_PARAM1);
 939                 v = reg_read(sc, IG4_REG_GENERAL);
 940                 /*
 941                  * The content of IG4_REG_GENERAL is different for each
 942                  * controller version.
 943                  */
 944                 if (sc->version == IG4_HASWELL &&
 945                     (v & IG4_GENERAL_SWMODE) == 0) {
 946                         v |= IG4_GENERAL_SWMODE;
 947                         reg_write(sc, IG4_REG_GENERAL, v);
 948                         v = reg_read(sc, IG4_REG_GENERAL);
 949                 }
 950         }
 951
 952         if (sc->version == IG4_HASWELL) {
 953                 v = reg_read(sc, IG4_REG_SW_LTR_VALUE);
 954                 v = reg_read(sc, IG4_REG_AUTO_LTR_VALUE);
 955         } else if (IG4_HAS_ADDREGS(sc->version)) {
 956                 v = reg_read(sc, IG4_REG_ACTIVE_LTR_VALUE);
 957                 v = reg_read(sc, IG4_REG_IDLE_LTR_VALUE);
 958         }
 959
 960         if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) {
 961                 v = reg_read(sc, IG4_REG_COMP_VER);
 962                 if (v < IG4_COMP_MIN_VER)
 963                         return(ENXIO);
 964         }
 965
 966         if (set_controller(sc, 0)) {
 967                 device_printf(sc->dev, "controller error during attach-1\n");
 968                 return (ENXIO);
 969         }
 970
 971         reg_read(sc, IG4_REG_CLR_INTR);
 972         reg_write(sc, IG4_REG_INTR_MASK, 0);
 973         sc->intr_mask = 0;
 974
 975         reg_write(sc, IG4_REG_SS_SCL_HCNT, sc->cfg.ss_scl_hcnt);
 976         reg_write(sc, IG4_REG_SS_SCL_LCNT, sc->cfg.ss_scl_lcnt);
 977         reg_write(sc, IG4_REG_FS_SCL_HCNT, sc->cfg.fs_scl_hcnt);
 978         reg_write(sc, IG4_REG_FS_SCL_LCNT, sc->cfg.fs_scl_lcnt);
 979         reg_write(sc, IG4_REG_SDA_HOLD,
 980             (sc->cfg.bus_speed  & IG4_CTL_SPEED_MASK) == IG4_CTL_SPEED_STD ?
 981               sc->cfg.ss_sda_hold : sc->cfg.fs_sda_hold);
 982
 983         /*
 984          * Use a threshold of 1 so we get interrupted on each character,
 985          * allowing us to use mtx_sleep() in our poll code.  Not perfect
 986          * but this is better than using DELAY() for receiving data.
 987          *
 988          * See ig4_var.h for details on interrupt handler synchronization.
 989          */
 990         reg_write(sc, IG4_REG_RX_TL, 0);
 991         reg_write(sc, IG4_REG_TX_TL, 0);
 992
 993         reg_write(sc, IG4_REG_CTL,
 994                   IG4_CTL_MASTER |
 995                   IG4_CTL_SLAVE_DISABLE |
 996                   IG4_CTL_RESTARTEN |
 997                   (sc->cfg.bus_speed & IG4_CTL_SPEED_MASK));
 998
 999         /* Force setting of the target address on the next transfer */
1000         sc->slave_valid = 0;
1001
1002         return (0);
1003 }
1004
1005 /*
1006  * Called from ig4iic_pci_attach/detach()
1007  */
1008 int
1009 ig4iic_attach(ig4iic_softc_t *sc)
1010 {
1011         int error;
1012
1013         mtx_init(&sc->io_lock, "IG4 I/O lock", NULL, MTX_SPIN);
1014         sx_init(&sc->call_lock, "IG4 call lock");
1015
1016         ig4iic_get_config(sc);
1017
1018         error = ig4iic_set_config(sc, IG4_HAS_ADDREGS(sc->version));
1019         if (error)
1020                 goto done;
1021
1022         sc->iicbus = device_add_child(sc->dev, "iicbus", -1);
1023         if (sc->iicbus == NULL) {
1024                 device_printf(sc->dev, "iicbus driver not found\n");
1025                 error = ENXIO;
1026                 goto done;
1027         }
1028
1029         if (set_controller(sc, IG4_I2C_ENABLE)) {
1030                 device_printf(sc->dev, "controller error during attach-2\n");
1031                 error = ENXIO;
1032                 goto done;
1033         }
1034         if (set_controller(sc, 0)) {
1035                 device_printf(sc->dev, "controller error during attach-3\n");
1036                 error = ENXIO;
1037                 goto done;
1038         }
1039         error = bus_setup_intr(sc->dev, sc->intr_res, INTR_TYPE_MISC | INTR_MPSAFE,
1040                                ig4iic_intr, NULL, sc, &sc->intr_handle);
1041         if (error) {
1042                 device_printf(sc->dev,
1043                               "Unable to setup irq: error %d\n", error);
1044         }
1045
1046         error = bus_generic_attach(sc->dev);
1047         if (error) {
1048                 device_printf(sc->dev,
1049                               "failed to attach child: error %d\n", error);
1050         }
1051
1052 done:
1053         return (error);
1054 }
1055
1056 int
1057 ig4iic_detach(ig4iic_softc_t *sc)
1058 {
1059         int error;
1060
1061         if (device_is_attached(sc->dev)) {
1062                 error = bus_generic_detach(sc->dev);
1063                 if (error)
1064                         return (error);
1065         }
1066         if (sc->iicbus)
1067                 device_delete_child(sc->dev, sc->iicbus);
1068         if (sc->intr_handle)
1069                 bus_teardown_intr(sc->dev, sc->intr_res, sc->intr_handle);
1070
1071         sx_xlock(&sc->call_lock);
1072
1073         sc->iicbus = NULL;
1074         sc->intr_handle = NULL;
1075         reg_write(sc, IG4_REG_INTR_MASK, 0);
1076         set_controller(sc, 0);
1077
1078         sx_xunlock(&sc->call_lock);
1079
1080         mtx_destroy(&sc->io_lock);
1081         sx_destroy(&sc->call_lock);
1082
1083         return (0);
1084 }
1085
1086 int
1087 ig4iic_suspend(ig4iic_softc_t *sc)
1088 {
1089         int error;
1090
1091         /* suspend all children */
1092         error = bus_generic_suspend(sc->dev);
1093
1094         sx_xlock(&sc->call_lock);
1095         set_controller(sc, 0);
1096         if (IG4_HAS_ADDREGS(sc->version)) {
1097                 /*
1098                  * Place the device in the idle state, just to be safe
1099                  */
1100                 reg_write(sc, IG4_REG_DEVIDLE_CTRL, IG4_DEVICE_IDLE);
1101                 /*
1102                  * Controller can become dysfunctional if I2C lines are pulled
1103                  * down when suspend procedure turns off power to I2C device.
1104                  * Place device in the reset state to avoid this.
1105                  */
1106                 reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_ASSERT_SKL);
1107         }
1108         sx_xunlock(&sc->call_lock);
1109
1110         return (error);
1111 }
1112
1113 int ig4iic_resume(ig4iic_softc_t *sc)
1114 {
1115         int error;
1116
1117         sx_xlock(&sc->call_lock);
1118         if (ig4iic_set_config(sc, IG4_HAS_ADDREGS(sc->version)))
1119                 device_printf(sc->dev, "controller error during resume\n");
1120         sx_xunlock(&sc->call_lock);
1121
1122         error = bus_generic_resume(sc->dev);
1123
1124         return (error);
1125 }
1126
1127 /*
1128  * Interrupt Operation, see ig4_var.h for locking semantics.
1129  */
1130 static int
1131 ig4iic_intr(void *cookie)
1132 {
1133         ig4iic_softc_t *sc = cookie;
1134         int retval = FILTER_STRAY;
1135
1136         mtx_lock_spin(&sc->io_lock);
1137         /* Ignore stray interrupts */
1138         if (sc->intr_mask != 0 && reg_read(sc, IG4_REG_INTR_STAT) != 0) {
1139                 /* Interrupt bits are cleared in wait_intr() loop */
1140                 ig4iic_set_intr_mask(sc, 0);
1141                 wakeup(sc);
1142                 retval = FILTER_HANDLED;
1143         }
1144         mtx_unlock_spin(&sc->io_lock);
1145
1146         return (retval);
1147 }
1148
1149 #define REGDUMP(sc, reg)        \
1150         device_printf(sc->dev, "  %-23s %08x\n", #reg, reg_read(sc, reg))
1151
1152 static void
1153 ig4iic_dump(ig4iic_softc_t *sc)
1154 {
1155         device_printf(sc->dev, "ig4iic register dump:\n");
1156         REGDUMP(sc, IG4_REG_CTL);
1157         REGDUMP(sc, IG4_REG_TAR_ADD);
1158         REGDUMP(sc, IG4_REG_SS_SCL_HCNT);
1159         REGDUMP(sc, IG4_REG_SS_SCL_LCNT);
1160         REGDUMP(sc, IG4_REG_FS_SCL_HCNT);
1161         REGDUMP(sc, IG4_REG_FS_SCL_LCNT);
1162         REGDUMP(sc, IG4_REG_INTR_STAT);
1163         REGDUMP(sc, IG4_REG_INTR_MASK);
1164         REGDUMP(sc, IG4_REG_RAW_INTR_STAT);
1165         REGDUMP(sc, IG4_REG_RX_TL);
1166         REGDUMP(sc, IG4_REG_TX_TL);
1167         REGDUMP(sc, IG4_REG_I2C_EN);
1168         REGDUMP(sc, IG4_REG_I2C_STA);
1169         REGDUMP(sc, IG4_REG_TXFLR);
1170         REGDUMP(sc, IG4_REG_RXFLR);
1171         REGDUMP(sc, IG4_REG_SDA_HOLD);
1172         REGDUMP(sc, IG4_REG_TX_ABRT_SOURCE);
1173         REGDUMP(sc, IG4_REG_SLV_DATA_NACK);
1174         REGDUMP(sc, IG4_REG_DMA_CTRL);
1175         REGDUMP(sc, IG4_REG_DMA_TDLR);
1176         REGDUMP(sc, IG4_REG_DMA_RDLR);
1177         REGDUMP(sc, IG4_REG_SDA_SETUP);
1178         REGDUMP(sc, IG4_REG_ENABLE_STATUS);
1179         REGDUMP(sc, IG4_REG_COMP_PARAM1);
1180         REGDUMP(sc, IG4_REG_COMP_VER);
1181         if (sc->version == IG4_ATOM) {
1182                 REGDUMP(sc, IG4_REG_COMP_TYPE);
1183                 REGDUMP(sc, IG4_REG_CLK_PARMS);
1184         }
1185         if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) {
1186                 REGDUMP(sc, IG4_REG_RESETS_HSW);
1187                 REGDUMP(sc, IG4_REG_GENERAL);
1188         } else if (sc->version == IG4_SKYLAKE) {
1189                 REGDUMP(sc, IG4_REG_RESETS_SKL);
1190         }
1191         if (sc->version == IG4_HASWELL) {
1192                 REGDUMP(sc, IG4_REG_SW_LTR_VALUE);
1193                 REGDUMP(sc, IG4_REG_AUTO_LTR_VALUE);
1194         } else if (IG4_HAS_ADDREGS(sc->version)) {
1195                 REGDUMP(sc, IG4_REG_ACTIVE_LTR_VALUE);
1196                 REGDUMP(sc, IG4_REG_IDLE_LTR_VALUE);
1197         }
1198 }
1199 #undef REGDUMP
1200
1201 devclass_t ig4iic_devclass;
1202
1203 DRIVER_MODULE(iicbus, ig4iic, iicbus_driver, iicbus_devclass, NULL, NULL);
1204 #ifdef DEV_ACPI
1205 DRIVER_MODULE(acpi_iicbus, ig4iic, acpi_iicbus_driver, iicbus_devclass, NULL,
1206     NULL);
1207 #endif
1208 MODULE_DEPEND(ig4iic, iicbus, IICBUS_MINVER, IICBUS_PREFVER, IICBUS_MAXVER);
1209 MODULE_VERSION(ig4iic, 1);