2 * Copyright (c) 2014 The DragonFly Project. All rights reserved.
4 * This code is derived from software contributed to The DragonFly Project
5 * by Matthew Dillon <dillon@backplane.com> and was subsequently ported
6 * to FreeBSD by Michael Gmelin <freebsd@grem.de>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in
16 * the documentation and/or other materials provided with the
18 * 3. Neither the name of The DragonFly Project nor the names of its
19 * contributors may be used to endorse or promote products derived
20 * from this software without specific, prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
25 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
26 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 #include <sys/cdefs.h>
37 __FBSDID("$FreeBSD$");
40 * Intel fourth generation mobile cpus integrated I2C device.
42 * See ig4_reg.h for datasheet reference and notes.
45 #include <sys/param.h>
46 #include <sys/systm.h>
47 #include <sys/kernel.h>
48 #include <sys/module.h>
49 #include <sys/errno.h>
51 #include <sys/mutex.h>
53 #include <sys/syslog.h>
56 #include <machine/bus.h>
58 #include <machine/resource.h>
60 #include <dev/pci/pcivar.h>
61 #include <dev/pci/pcireg.h>
62 #include <dev/iicbus/iiconf.h>
64 #include <dev/ichiic/ig4_reg.h>
65 #include <dev/ichiic/ig4_var.h>
67 static int ig4iic_pci_detach(device_t dev);
69 #define PCI_CHIP_BAYTRAIL_I2C_1 0x0f418086
70 #define PCI_CHIP_BAYTRAIL_I2C_2 0x0f428086
71 #define PCI_CHIP_BAYTRAIL_I2C_3 0x0f438086
72 #define PCI_CHIP_BAYTRAIL_I2C_4 0x0f448086
73 #define PCI_CHIP_BAYTRAIL_I2C_5 0x0f458086
74 #define PCI_CHIP_BAYTRAIL_I2C_6 0x0f468086
75 #define PCI_CHIP_BAYTRAIL_I2C_7 0x0f478086
76 #define PCI_CHIP_LYNXPT_LP_I2C_1 0x9c618086
77 #define PCI_CHIP_LYNXPT_LP_I2C_2 0x9c628086
78 #define PCI_CHIP_BRASWELL_I2C_1 0x22c18086
79 #define PCI_CHIP_BRASWELL_I2C_2 0x22c28086
80 #define PCI_CHIP_BRASWELL_I2C_3 0x22c38086
81 #define PCI_CHIP_BRASWELL_I2C_5 0x22c58086
82 #define PCI_CHIP_BRASWELL_I2C_6 0x22c68086
83 #define PCI_CHIP_BRASWELL_I2C_7 0x22c78086
84 #define PCI_CHIP_SKYLAKE_I2C_0 0x9d608086
85 #define PCI_CHIP_SKYLAKE_I2C_1 0x9d618086
86 #define PCI_CHIP_SKYLAKE_I2C_2 0x9d628086
87 #define PCI_CHIP_SKYLAKE_I2C_3 0x9d638086
88 #define PCI_CHIP_SKYLAKE_I2C_4 0x9d648086
89 #define PCI_CHIP_SKYLAKE_I2C_5 0x9d658086
90 #define PCI_CHIP_KABYLAKE_I2C_0 0xa1608086
91 #define PCI_CHIP_KABYLAKE_I2C_1 0xa1618086
92 #define PCI_CHIP_APL_I2C_0 0x5aac8086
93 #define PCI_CHIP_APL_I2C_1 0x5aae8086
94 #define PCI_CHIP_APL_I2C_2 0x5ab08086
95 #define PCI_CHIP_APL_I2C_3 0x5ab28086
96 #define PCI_CHIP_APL_I2C_4 0x5ab48086
97 #define PCI_CHIP_APL_I2C_5 0x5ab68086
98 #define PCI_CHIP_APL_I2C_6 0x5ab88086
99 #define PCI_CHIP_APL_I2C_7 0x5aba8086
100 #define PCI_CHIP_CANNONLAKE_LP_I2C_0 0x9dc58086
101 #define PCI_CHIP_CANNONLAKE_LP_I2C_1 0x9dc68086
102 #define PCI_CHIP_CANNONLAKE_LP_I2C_2 0x9de88086
103 #define PCI_CHIP_CANNONLAKE_LP_I2C_3 0x9de98086
104 #define PCI_CHIP_CANNONLAKE_LP_I2C_4 0x9dea8086
105 #define PCI_CHIP_CANNONLAKE_LP_I2C_5 0x9deb8086
106 #define PCI_CHIP_CANNONLAKE_H_I2C_0 0xa3688086
107 #define PCI_CHIP_CANNONLAKE_H_I2C_1 0xa3698086
108 #define PCI_CHIP_CANNONLAKE_H_I2C_2 0xa36a8086
109 #define PCI_CHIP_CANNONLAKE_H_I2C_3 0xa36b8086
110 #define PCI_CHIP_COMETLAKE_LP_I2C_0 0x02e88086
111 #define PCI_CHIP_COMETLAKE_LP_I2C_1 0x02e98086
112 #define PCI_CHIP_COMETLAKE_LP_I2C_2 0x02ea8086
113 #define PCI_CHIP_COMETLAKE_LP_I2C_3 0x02eb8086
114 #define PCI_CHIP_COMETLAKE_LP_I2C_4 0x02c58086
115 #define PCI_CHIP_COMETLAKE_LP_I2C_5 0x02c68086
116 #define PCI_CHIP_COMETLAKE_H_I2C_0 0x06e88086
117 #define PCI_CHIP_COMETLAKE_H_I2C_1 0x06e98086
118 #define PCI_CHIP_COMETLAKE_H_I2C_2 0x06ea8086
119 #define PCI_CHIP_COMETLAKE_H_I2C_3 0x06eb8086
120 #define PCI_CHIP_COMETLAKE_V_I2C_0 0xa3e08086
121 #define PCI_CHIP_COMETLAKE_V_I2C_1 0xa3e18086
122 #define PCI_CHIP_COMETLAKE_V_I2C_2 0xa3e28086
123 #define PCI_CHIP_COMETLAKE_V_I2C_3 0xa3e38086
124 #define PCI_CHIP_TIGERLAKE_H_I2C_0 0x43d88086
125 #define PCI_CHIP_TIGERLAKE_H_I2C_1 0x43e88086
126 #define PCI_CHIP_TIGERLAKE_H_I2C_2 0x43e98086
127 #define PCI_CHIP_TIGERLAKE_H_I2C_3 0x43ea8086
128 #define PCI_CHIP_TIGERLAKE_H_I2C_4 0x43eb8086
129 #define PCI_CHIP_TIGERLAKE_H_I2C_5 0x43ad8086
130 #define PCI_CHIP_TIGERLAKE_H_I2C_6 0x43ae8086
131 #define PCI_CHIP_TIGERLAKE_LP_I2C_0 0xa0c58086
132 #define PCI_CHIP_TIGERLAKE_LP_I2C_1 0xa0c68086
133 #define PCI_CHIP_TIGERLAKE_LP_I2C_2 0xa0d88086
134 #define PCI_CHIP_TIGERLAKE_LP_I2C_3 0xa0d98086
135 #define PCI_CHIP_TIGERLAKE_LP_I2C_4 0xa0e88086
136 #define PCI_CHIP_TIGERLAKE_LP_I2C_5 0xa0e98086
137 #define PCI_CHIP_TIGERLAKE_LP_I2C_6 0xa0ea8086
138 #define PCI_CHIP_TIGERLAKE_LP_I2C_7 0xa0eb8086
139 #define PCI_CHIP_GEMINILAKE_I2C_0 0x31ac8086
140 #define PCI_CHIP_GEMINILAKE_I2C_1 0x31ae8086
141 #define PCI_CHIP_GEMINILAKE_I2C_2 0x31b08086
142 #define PCI_CHIP_GEMINILAKE_I2C_3 0x31b28086
143 #define PCI_CHIP_GEMINILAKE_I2C_4 0x31b48086
144 #define PCI_CHIP_GEMINILAKE_I2C_5 0x31b68086
145 #define PCI_CHIP_GEMINILAKE_I2C_6 0x31b88086
146 #define PCI_CHIP_GEMINILAKE_I2C_7 0x31ba8086
148 struct ig4iic_pci_device {
151 enum ig4_vers version;
154 static struct ig4iic_pci_device ig4iic_pci_devices[] = {
155 { PCI_CHIP_BAYTRAIL_I2C_1, "Intel BayTrail Serial I/O I2C Port 1", IG4_ATOM},
156 { PCI_CHIP_BAYTRAIL_I2C_2, "Intel BayTrail Serial I/O I2C Port 2", IG4_ATOM},
157 { PCI_CHIP_BAYTRAIL_I2C_3, "Intel BayTrail Serial I/O I2C Port 3", IG4_ATOM},
158 { PCI_CHIP_BAYTRAIL_I2C_4, "Intel BayTrail Serial I/O I2C Port 4", IG4_ATOM},
159 { PCI_CHIP_BAYTRAIL_I2C_5, "Intel BayTrail Serial I/O I2C Port 5", IG4_ATOM},
160 { PCI_CHIP_BAYTRAIL_I2C_6, "Intel BayTrail Serial I/O I2C Port 6", IG4_ATOM},
161 { PCI_CHIP_BAYTRAIL_I2C_7, "Intel BayTrail Serial I/O I2C Port 7", IG4_ATOM},
162 { PCI_CHIP_LYNXPT_LP_I2C_1, "Intel Lynx Point-LP I2C Controller-1", IG4_HASWELL},
163 { PCI_CHIP_LYNXPT_LP_I2C_2, "Intel Lynx Point-LP I2C Controller-2", IG4_HASWELL},
164 { PCI_CHIP_BRASWELL_I2C_1, "Intel Braswell Serial I/O I2C Port 1", IG4_ATOM},
165 { PCI_CHIP_BRASWELL_I2C_2, "Intel Braswell Serial I/O I2C Port 2", IG4_ATOM},
166 { PCI_CHIP_BRASWELL_I2C_3, "Intel Braswell Serial I/O I2C Port 3", IG4_ATOM},
167 { PCI_CHIP_BRASWELL_I2C_5, "Intel Braswell Serial I/O I2C Port 5", IG4_ATOM},
168 { PCI_CHIP_BRASWELL_I2C_6, "Intel Braswell Serial I/O I2C Port 6", IG4_ATOM},
169 { PCI_CHIP_BRASWELL_I2C_7, "Intel Braswell Serial I/O I2C Port 7", IG4_ATOM},
170 { PCI_CHIP_SKYLAKE_I2C_0, "Intel Sunrise Point-LP I2C Controller-0", IG4_SKYLAKE},
171 { PCI_CHIP_SKYLAKE_I2C_1, "Intel Sunrise Point-LP I2C Controller-1", IG4_SKYLAKE},
172 { PCI_CHIP_SKYLAKE_I2C_2, "Intel Sunrise Point-LP I2C Controller-2", IG4_SKYLAKE},
173 { PCI_CHIP_SKYLAKE_I2C_3, "Intel Sunrise Point-LP I2C Controller-3", IG4_SKYLAKE},
174 { PCI_CHIP_SKYLAKE_I2C_4, "Intel Sunrise Point-LP I2C Controller-4", IG4_SKYLAKE},
175 { PCI_CHIP_SKYLAKE_I2C_5, "Intel Sunrise Point-LP I2C Controller-5", IG4_SKYLAKE},
176 { PCI_CHIP_KABYLAKE_I2C_0, "Intel Sunrise Point-H I2C Controller-0", IG4_SKYLAKE},
177 { PCI_CHIP_KABYLAKE_I2C_1, "Intel Sunrise Point-H I2C Controller-1", IG4_SKYLAKE},
178 { PCI_CHIP_APL_I2C_0, "Intel Apollo Lake I2C Controller-0", IG4_APL},
179 { PCI_CHIP_APL_I2C_1, "Intel Apollo Lake I2C Controller-1", IG4_APL},
180 { PCI_CHIP_APL_I2C_2, "Intel Apollo Lake I2C Controller-2", IG4_APL},
181 { PCI_CHIP_APL_I2C_3, "Intel Apollo Lake I2C Controller-3", IG4_APL},
182 { PCI_CHIP_APL_I2C_4, "Intel Apollo Lake I2C Controller-4", IG4_APL},
183 { PCI_CHIP_APL_I2C_5, "Intel Apollo Lake I2C Controller-5", IG4_APL},
184 { PCI_CHIP_APL_I2C_6, "Intel Apollo Lake I2C Controller-6", IG4_APL},
185 { PCI_CHIP_APL_I2C_7, "Intel Apollo Lake I2C Controller-7", IG4_APL},
186 { PCI_CHIP_CANNONLAKE_LP_I2C_0, "Intel Cannon Lake-LP I2C Controller-0", IG4_CANNONLAKE},
187 { PCI_CHIP_CANNONLAKE_LP_I2C_1, "Intel Cannon Lake-LP I2C Controller-1", IG4_CANNONLAKE},
188 { PCI_CHIP_CANNONLAKE_LP_I2C_2, "Intel Cannon Lake-LP I2C Controller-2", IG4_CANNONLAKE},
189 { PCI_CHIP_CANNONLAKE_LP_I2C_3, "Intel Cannon Lake-LP I2C Controller-3", IG4_CANNONLAKE},
190 { PCI_CHIP_CANNONLAKE_LP_I2C_4, "Intel Cannon Lake-LP I2C Controller-4", IG4_CANNONLAKE},
191 { PCI_CHIP_CANNONLAKE_LP_I2C_5, "Intel Cannon Lake-LP I2C Controller-5", IG4_CANNONLAKE},
192 { PCI_CHIP_CANNONLAKE_H_I2C_0, "Intel Cannon Lake-H I2C Controller-0", IG4_CANNONLAKE},
193 { PCI_CHIP_CANNONLAKE_H_I2C_1, "Intel Cannon Lake-H I2C Controller-1", IG4_CANNONLAKE},
194 { PCI_CHIP_CANNONLAKE_H_I2C_2, "Intel Cannon Lake-H I2C Controller-2", IG4_CANNONLAKE},
195 { PCI_CHIP_CANNONLAKE_H_I2C_3, "Intel Cannon Lake-H I2C Controller-3", IG4_CANNONLAKE},
196 { PCI_CHIP_COMETLAKE_LP_I2C_0, "Intel Comet Lake-LP I2C Controller-0", IG4_CANNONLAKE},
197 { PCI_CHIP_COMETLAKE_LP_I2C_1, "Intel Comet Lake-LP I2C Controller-1", IG4_CANNONLAKE},
198 { PCI_CHIP_COMETLAKE_LP_I2C_2, "Intel Comet Lake-LP I2C Controller-2", IG4_CANNONLAKE},
199 { PCI_CHIP_COMETLAKE_LP_I2C_3, "Intel Comet Lake-LP I2C Controller-3", IG4_CANNONLAKE},
200 { PCI_CHIP_COMETLAKE_LP_I2C_4, "Intel Comet Lake-LP I2C Controller-4", IG4_CANNONLAKE},
201 { PCI_CHIP_COMETLAKE_LP_I2C_5, "Intel Comet Lake-LP I2C Controller-5", IG4_CANNONLAKE},
202 { PCI_CHIP_COMETLAKE_H_I2C_0, "Intel Comet Lake-H I2C Controller-0", IG4_CANNONLAKE},
203 { PCI_CHIP_COMETLAKE_H_I2C_1, "Intel Comet Lake-H I2C Controller-1", IG4_CANNONLAKE},
204 { PCI_CHIP_COMETLAKE_H_I2C_2, "Intel Comet Lake-H I2C Controller-2", IG4_CANNONLAKE},
205 { PCI_CHIP_COMETLAKE_H_I2C_3, "Intel Comet Lake-H I2C Controller-3", IG4_CANNONLAKE},
206 { PCI_CHIP_COMETLAKE_V_I2C_0, "Intel Comet Lake-V I2C Controller-0", IG4_CANNONLAKE},
207 { PCI_CHIP_COMETLAKE_V_I2C_1, "Intel Comet Lake-V I2C Controller-1", IG4_CANNONLAKE},
208 { PCI_CHIP_COMETLAKE_V_I2C_2, "Intel Comet Lake-V I2C Controller-2", IG4_CANNONLAKE},
209 { PCI_CHIP_COMETLAKE_V_I2C_3, "Intel Comet Lake-V I2C Controller-3", IG4_CANNONLAKE},
210 { PCI_CHIP_TIGERLAKE_H_I2C_0, "Intel Tiger Lake-H I2C Controller-0", IG4_TIGERLAKE},
211 { PCI_CHIP_TIGERLAKE_H_I2C_1, "Intel Tiger Lake-H I2C Controller-1", IG4_TIGERLAKE},
212 { PCI_CHIP_TIGERLAKE_H_I2C_2, "Intel Tiger Lake-H I2C Controller-2", IG4_TIGERLAKE},
213 { PCI_CHIP_TIGERLAKE_H_I2C_3, "Intel Tiger Lake-H I2C Controller-3", IG4_TIGERLAKE},
214 { PCI_CHIP_TIGERLAKE_H_I2C_4, "Intel Tiger Lake-H I2C Controller-4", IG4_TIGERLAKE},
215 { PCI_CHIP_TIGERLAKE_H_I2C_5, "Intel Tiger Lake-H I2C Controller-5", IG4_TIGERLAKE},
216 { PCI_CHIP_TIGERLAKE_H_I2C_6, "Intel Tiger Lake-H I2C Controller-6", IG4_TIGERLAKE},
217 { PCI_CHIP_TIGERLAKE_LP_I2C_0, "Intel Tiger Lake-LP I2C Controller-0", IG4_SKYLAKE},
218 { PCI_CHIP_TIGERLAKE_LP_I2C_1, "Intel Tiger Lake-LP I2C Controller-1", IG4_SKYLAKE},
219 { PCI_CHIP_TIGERLAKE_LP_I2C_2, "Intel Tiger Lake-LP I2C Controller-2", IG4_SKYLAKE},
220 { PCI_CHIP_TIGERLAKE_LP_I2C_3, "Intel Tiger Lake-LP I2C Controller-3", IG4_SKYLAKE},
221 { PCI_CHIP_TIGERLAKE_LP_I2C_4, "Intel Tiger Lake-LP I2C Controller-4", IG4_SKYLAKE},
222 { PCI_CHIP_TIGERLAKE_LP_I2C_5, "Intel Tiger Lake-LP I2C Controller-5", IG4_SKYLAKE},
223 { PCI_CHIP_TIGERLAKE_LP_I2C_6, "Intel Tiger Lake-LP I2C Controller-6", IG4_SKYLAKE},
224 { PCI_CHIP_TIGERLAKE_LP_I2C_7, "Intel Tiger Lake-LP I2C Controller-7", IG4_SKYLAKE},
225 { PCI_CHIP_GEMINILAKE_I2C_0, "Intel Gemini Lake I2C Controller-0", IG4_GEMINILAKE},
226 { PCI_CHIP_GEMINILAKE_I2C_1, "Intel Gemini Lake I2C Controller-1", IG4_GEMINILAKE},
227 { PCI_CHIP_GEMINILAKE_I2C_2, "Intel Gemini Lake I2C Controller-2", IG4_GEMINILAKE},
228 { PCI_CHIP_GEMINILAKE_I2C_3, "Intel Gemini Lake I2C Controller-3", IG4_GEMINILAKE},
229 { PCI_CHIP_GEMINILAKE_I2C_4, "Intel Gemini Lake I2C Controller-4", IG4_GEMINILAKE},
230 { PCI_CHIP_GEMINILAKE_I2C_5, "Intel Gemini Lake I2C Controller-5", IG4_GEMINILAKE},
231 { PCI_CHIP_GEMINILAKE_I2C_6, "Intel Gemini Lake I2C Controller-6", IG4_GEMINILAKE},
232 { PCI_CHIP_GEMINILAKE_I2C_7, "Intel Gemini Lake I2C Controller-7", IG4_GEMINILAKE},
236 ig4iic_pci_probe(device_t dev)
238 ig4iic_softc_t *sc = device_get_softc(dev);
242 devid = pci_get_devid(dev);
243 for (i = 0; i < nitems(ig4iic_pci_devices); i++) {
244 if (ig4iic_pci_devices[i].devid == devid) {
245 device_set_desc(dev, ig4iic_pci_devices[i].desc);
246 sc->version = ig4iic_pci_devices[i].version;
247 return (BUS_PROBE_DEFAULT);
254 ig4iic_pci_attach(device_t dev)
256 ig4iic_softc_t *sc = device_get_softc(dev);
260 sc->regs_rid = PCIR_BAR(0);
261 sc->regs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
262 &sc->regs_rid, RF_ACTIVE);
263 if (sc->regs_res == NULL) {
264 device_printf(dev, "unable to map registers\n");
265 ig4iic_pci_detach(dev);
269 if (pci_alloc_msi(dev, &sc->intr_rid)) {
270 device_printf(dev, "Using MSI\n");
272 sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
273 &sc->intr_rid, RF_SHAREABLE | RF_ACTIVE);
274 if (sc->intr_res == NULL) {
275 device_printf(dev, "unable to map interrupt\n");
276 ig4iic_pci_detach(dev);
279 sc->platform_attached = 1;
281 error = ig4iic_attach(sc);
283 ig4iic_pci_detach(dev);
289 ig4iic_pci_detach(device_t dev)
291 ig4iic_softc_t *sc = device_get_softc(dev);
294 if (sc->platform_attached) {
295 error = ig4iic_detach(sc);
298 sc->platform_attached = 0;
302 bus_release_resource(dev, SYS_RES_IRQ,
303 sc->intr_rid, sc->intr_res);
306 if (sc->intr_rid != 0)
307 pci_release_msi(dev);
309 bus_release_resource(dev, SYS_RES_MEMORY,
310 sc->regs_rid, sc->regs_res);
318 ig4iic_pci_suspend(device_t dev)
320 ig4iic_softc_t *sc = device_get_softc(dev);
322 return (ig4iic_suspend(sc));
326 ig4iic_pci_resume(device_t dev)
328 ig4iic_softc_t *sc = device_get_softc(dev);
330 return (ig4iic_resume(sc));
333 static device_method_t ig4iic_pci_methods[] = {
334 /* Device interface */
335 DEVMETHOD(device_probe, ig4iic_pci_probe),
336 DEVMETHOD(device_attach, ig4iic_pci_attach),
337 DEVMETHOD(device_detach, ig4iic_pci_detach),
338 DEVMETHOD(device_suspend, ig4iic_pci_suspend),
339 DEVMETHOD(device_resume, ig4iic_pci_resume),
342 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
343 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
344 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource),
345 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
346 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
347 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
348 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource),
350 /* iicbus interface */
351 DEVMETHOD(iicbus_transfer, ig4iic_transfer),
352 DEVMETHOD(iicbus_reset, ig4iic_reset),
353 DEVMETHOD(iicbus_callback, ig4iic_callback),
358 static driver_t ig4iic_pci_driver = {
361 sizeof(struct ig4iic_softc)
364 DRIVER_MODULE_ORDERED(ig4iic, pci, ig4iic_pci_driver, ig4iic_devclass, 0, 0,
366 MODULE_DEPEND(ig4iic, pci, 1, 1, 1);
367 MODULE_PNP_INFO("W32:vendor/device", pci, ig4iic, ig4iic_pci_devices,
368 nitems(ig4iic_pci_devices));