2 * Copyright (c) 2014 The DragonFly Project. All rights reserved.
4 * This code is derived from software contributed to The DragonFly Project
5 * by Matthew Dillon <dillon@backplane.com> and was subsequently ported
6 * to FreeBSD by Michael Gmelin <freebsd@grem.de>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in
16 * the documentation and/or other materials provided with the
18 * 3. Neither the name of The DragonFly Project nor the names of its
19 * contributors may be used to endorse or promote products derived
20 * from this software without specific, prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
25 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
26 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 #include <sys/cdefs.h>
37 __FBSDID("$FreeBSD$");
40 * Intel fourth generation mobile cpus integrated I2C device.
42 * See ig4_reg.h for datasheet reference and notes.
45 #include <sys/param.h>
46 #include <sys/systm.h>
47 #include <sys/kernel.h>
48 #include <sys/module.h>
49 #include <sys/errno.h>
51 #include <sys/mutex.h>
53 #include <sys/syslog.h>
56 #include <machine/bus.h>
58 #include <machine/resource.h>
60 #include <dev/pci/pcivar.h>
61 #include <dev/pci/pcireg.h>
62 #include <dev/iicbus/iiconf.h>
64 #include <dev/ichiic/ig4_reg.h>
65 #include <dev/ichiic/ig4_var.h>
67 static int ig4iic_pci_detach(device_t dev);
69 #define PCI_CHIP_BAYTRAIL_I2C_1 0x0f418086
70 #define PCI_CHIP_BAYTRAIL_I2C_2 0x0f428086
71 #define PCI_CHIP_BAYTRAIL_I2C_3 0x0f438086
72 #define PCI_CHIP_BAYTRAIL_I2C_4 0x0f448086
73 #define PCI_CHIP_BAYTRAIL_I2C_5 0x0f458086
74 #define PCI_CHIP_BAYTRAIL_I2C_6 0x0f468086
75 #define PCI_CHIP_BAYTRAIL_I2C_7 0x0f478086
76 #define PCI_CHIP_LYNXPT_LP_I2C_1 0x9c618086
77 #define PCI_CHIP_LYNXPT_LP_I2C_2 0x9c628086
78 #define PCI_CHIP_BRASWELL_I2C_1 0x22c18086
79 #define PCI_CHIP_BRASWELL_I2C_2 0x22c28086
80 #define PCI_CHIP_BRASWELL_I2C_3 0x22c38086
81 #define PCI_CHIP_BRASWELL_I2C_5 0x22c58086
82 #define PCI_CHIP_BRASWELL_I2C_6 0x22c68086
83 #define PCI_CHIP_BRASWELL_I2C_7 0x22c78086
84 #define PCI_CHIP_SKYLAKE_I2C_0 0x9d608086
85 #define PCI_CHIP_SKYLAKE_I2C_1 0x9d618086
86 #define PCI_CHIP_SKYLAKE_I2C_2 0x9d628086
87 #define PCI_CHIP_SKYLAKE_I2C_3 0x9d638086
88 #define PCI_CHIP_SKYLAKE_I2C_4 0x9d648086
89 #define PCI_CHIP_SKYLAKE_I2C_5 0x9d658086
90 #define PCI_CHIP_KABYLAKE_I2C_0 0xa1608086
91 #define PCI_CHIP_KABYLAKE_I2C_1 0xa1618086
92 #define PCI_CHIP_APL_I2C_0 0x5aac8086
93 #define PCI_CHIP_APL_I2C_1 0x5aae8086
94 #define PCI_CHIP_APL_I2C_2 0x5ab08086
95 #define PCI_CHIP_APL_I2C_3 0x5ab28086
96 #define PCI_CHIP_APL_I2C_4 0x5ab48086
97 #define PCI_CHIP_APL_I2C_5 0x5ab68086
98 #define PCI_CHIP_APL_I2C_6 0x5ab88086
99 #define PCI_CHIP_APL_I2C_7 0x5aba8086
100 #define PCI_CHIP_CANNONLAKE_LP_I2C_0 0x9dc58086
101 #define PCI_CHIP_CANNONLAKE_LP_I2C_1 0x9dc68086
102 #define PCI_CHIP_CANNONLAKE_LP_I2C_2 0x9de88086
103 #define PCI_CHIP_CANNONLAKE_LP_I2C_3 0x9de98086
104 #define PCI_CHIP_CANNONLAKE_LP_I2C_4 0x9dea8086
105 #define PCI_CHIP_CANNONLAKE_LP_I2C_5 0x9deb8086
106 #define PCI_CHIP_CANNONLAKE_H_I2C_0 0xa3688086
107 #define PCI_CHIP_CANNONLAKE_H_I2C_1 0xa3698086
108 #define PCI_CHIP_CANNONLAKE_H_I2C_2 0xa36a8086
109 #define PCI_CHIP_CANNONLAKE_H_I2C_3 0xa36b8086
111 struct ig4iic_pci_device {
114 enum ig4_vers version;
117 static struct ig4iic_pci_device ig4iic_pci_devices[] = {
118 { PCI_CHIP_BAYTRAIL_I2C_1, "Intel BayTrail Serial I/O I2C Port 1", IG4_ATOM},
119 { PCI_CHIP_BAYTRAIL_I2C_2, "Intel BayTrail Serial I/O I2C Port 2", IG4_ATOM},
120 { PCI_CHIP_BAYTRAIL_I2C_3, "Intel BayTrail Serial I/O I2C Port 3", IG4_ATOM},
121 { PCI_CHIP_BAYTRAIL_I2C_4, "Intel BayTrail Serial I/O I2C Port 4", IG4_ATOM},
122 { PCI_CHIP_BAYTRAIL_I2C_5, "Intel BayTrail Serial I/O I2C Port 5", IG4_ATOM},
123 { PCI_CHIP_BAYTRAIL_I2C_6, "Intel BayTrail Serial I/O I2C Port 6", IG4_ATOM},
124 { PCI_CHIP_BAYTRAIL_I2C_7, "Intel BayTrail Serial I/O I2C Port 7", IG4_ATOM},
125 { PCI_CHIP_LYNXPT_LP_I2C_1, "Intel Lynx Point-LP I2C Controller-1", IG4_HASWELL},
126 { PCI_CHIP_LYNXPT_LP_I2C_2, "Intel Lynx Point-LP I2C Controller-2", IG4_HASWELL},
127 { PCI_CHIP_BRASWELL_I2C_1, "Intel Braswell Serial I/O I2C Port 1", IG4_ATOM},
128 { PCI_CHIP_BRASWELL_I2C_2, "Intel Braswell Serial I/O I2C Port 2", IG4_ATOM},
129 { PCI_CHIP_BRASWELL_I2C_3, "Intel Braswell Serial I/O I2C Port 3", IG4_ATOM},
130 { PCI_CHIP_BRASWELL_I2C_5, "Intel Braswell Serial I/O I2C Port 5", IG4_ATOM},
131 { PCI_CHIP_BRASWELL_I2C_6, "Intel Braswell Serial I/O I2C Port 6", IG4_ATOM},
132 { PCI_CHIP_BRASWELL_I2C_7, "Intel Braswell Serial I/O I2C Port 7", IG4_ATOM},
133 { PCI_CHIP_SKYLAKE_I2C_0, "Intel Sunrise Point-LP I2C Controller-0", IG4_SKYLAKE},
134 { PCI_CHIP_SKYLAKE_I2C_1, "Intel Sunrise Point-LP I2C Controller-1", IG4_SKYLAKE},
135 { PCI_CHIP_SKYLAKE_I2C_2, "Intel Sunrise Point-LP I2C Controller-2", IG4_SKYLAKE},
136 { PCI_CHIP_SKYLAKE_I2C_3, "Intel Sunrise Point-LP I2C Controller-3", IG4_SKYLAKE},
137 { PCI_CHIP_SKYLAKE_I2C_4, "Intel Sunrise Point-LP I2C Controller-4", IG4_SKYLAKE},
138 { PCI_CHIP_SKYLAKE_I2C_5, "Intel Sunrise Point-LP I2C Controller-5", IG4_SKYLAKE},
139 { PCI_CHIP_KABYLAKE_I2C_0, "Intel Sunrise Point-H I2C Controller-0", IG4_SKYLAKE},
140 { PCI_CHIP_KABYLAKE_I2C_1, "Intel Sunrise Point-H I2C Controller-1", IG4_SKYLAKE},
141 { PCI_CHIP_APL_I2C_0, "Intel Apollo Lake I2C Controller-0", IG4_APL},
142 { PCI_CHIP_APL_I2C_1, "Intel Apollo Lake I2C Controller-1", IG4_APL},
143 { PCI_CHIP_APL_I2C_2, "Intel Apollo Lake I2C Controller-2", IG4_APL},
144 { PCI_CHIP_APL_I2C_3, "Intel Apollo Lake I2C Controller-3", IG4_APL},
145 { PCI_CHIP_APL_I2C_4, "Intel Apollo Lake I2C Controller-4", IG4_APL},
146 { PCI_CHIP_APL_I2C_5, "Intel Apollo Lake I2C Controller-5", IG4_APL},
147 { PCI_CHIP_APL_I2C_6, "Intel Apollo Lake I2C Controller-6", IG4_APL},
148 { PCI_CHIP_APL_I2C_7, "Intel Apollo Lake I2C Controller-7", IG4_APL},
149 { PCI_CHIP_CANNONLAKE_LP_I2C_0, "Intel Cannon Lake-LP I2C Controller-0", IG4_CANNONLAKE},
150 { PCI_CHIP_CANNONLAKE_LP_I2C_1, "Intel Cannon Lake-LP I2C Controller-1", IG4_CANNONLAKE},
151 { PCI_CHIP_CANNONLAKE_LP_I2C_2, "Intel Cannon Lake-LP I2C Controller-2", IG4_CANNONLAKE},
152 { PCI_CHIP_CANNONLAKE_LP_I2C_3, "Intel Cannon Lake-LP I2C Controller-3", IG4_CANNONLAKE},
153 { PCI_CHIP_CANNONLAKE_LP_I2C_4, "Intel Cannon Lake-LP I2C Controller-4", IG4_CANNONLAKE},
154 { PCI_CHIP_CANNONLAKE_LP_I2C_5, "Intel Cannon Lake-LP I2C Controller-5", IG4_CANNONLAKE},
155 { PCI_CHIP_CANNONLAKE_H_I2C_0, "Intel Cannon Lake-H I2C Controller-0", IG4_CANNONLAKE},
156 { PCI_CHIP_CANNONLAKE_H_I2C_1, "Intel Cannon Lake-H I2C Controller-1", IG4_CANNONLAKE},
157 { PCI_CHIP_CANNONLAKE_H_I2C_2, "Intel Cannon Lake-H I2C Controller-2", IG4_CANNONLAKE},
158 { PCI_CHIP_CANNONLAKE_H_I2C_3, "Intel Cannon Lake-H I2C Controller-3", IG4_CANNONLAKE},
162 ig4iic_pci_probe(device_t dev)
164 ig4iic_softc_t *sc = device_get_softc(dev);
168 devid = pci_get_devid(dev);
169 for (i = 0; i < nitems(ig4iic_pci_devices); i++) {
170 if (ig4iic_pci_devices[i].devid == devid) {
171 device_set_desc(dev, ig4iic_pci_devices[i].desc);
172 sc->version = ig4iic_pci_devices[i].version;
173 return (BUS_PROBE_DEFAULT);
180 ig4iic_pci_attach(device_t dev)
182 ig4iic_softc_t *sc = device_get_softc(dev);
186 sc->regs_rid = PCIR_BAR(0);
187 sc->regs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
188 &sc->regs_rid, RF_ACTIVE);
189 if (sc->regs_res == NULL) {
190 device_printf(dev, "unable to map registers\n");
191 ig4iic_pci_detach(dev);
195 if (pci_alloc_msi(dev, &sc->intr_rid)) {
196 device_printf(dev, "Using MSI\n");
198 sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
199 &sc->intr_rid, RF_SHAREABLE | RF_ACTIVE);
200 if (sc->intr_res == NULL) {
201 device_printf(dev, "unable to map interrupt\n");
202 ig4iic_pci_detach(dev);
205 sc->platform_attached = 1;
207 error = ig4iic_attach(sc);
209 ig4iic_pci_detach(dev);
215 ig4iic_pci_detach(device_t dev)
217 ig4iic_softc_t *sc = device_get_softc(dev);
220 if (sc->platform_attached) {
221 error = ig4iic_detach(sc);
224 sc->platform_attached = 0;
228 bus_release_resource(dev, SYS_RES_IRQ,
229 sc->intr_rid, sc->intr_res);
232 if (sc->intr_rid != 0)
233 pci_release_msi(dev);
235 bus_release_resource(dev, SYS_RES_MEMORY,
236 sc->regs_rid, sc->regs_res);
244 ig4iic_pci_suspend(device_t dev)
246 ig4iic_softc_t *sc = device_get_softc(dev);
248 return (ig4iic_suspend(sc));
252 ig4iic_pci_resume(device_t dev)
254 ig4iic_softc_t *sc = device_get_softc(dev);
256 return (ig4iic_resume(sc));
259 static device_method_t ig4iic_pci_methods[] = {
260 /* Device interface */
261 DEVMETHOD(device_probe, ig4iic_pci_probe),
262 DEVMETHOD(device_attach, ig4iic_pci_attach),
263 DEVMETHOD(device_detach, ig4iic_pci_detach),
264 DEVMETHOD(device_suspend, ig4iic_pci_suspend),
265 DEVMETHOD(device_resume, ig4iic_pci_resume),
268 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
269 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
270 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource),
271 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
272 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
273 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
274 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource),
276 /* iicbus interface */
277 DEVMETHOD(iicbus_transfer, ig4iic_transfer),
278 DEVMETHOD(iicbus_reset, ig4iic_reset),
279 DEVMETHOD(iicbus_callback, ig4iic_callback),
284 static driver_t ig4iic_pci_driver = {
287 sizeof(struct ig4iic_softc)
290 DRIVER_MODULE_ORDERED(ig4iic, pci, ig4iic_pci_driver, ig4iic_devclass, 0, 0,
292 MODULE_DEPEND(ig4iic, pci, 1, 1, 1);
293 MODULE_PNP_INFO("W32:vendor/device", pci, ig4iic, ig4iic_pci_devices,
294 nitems(ig4iic_pci_devices));