2 * Copyright (c) 2014 The DragonFly Project. All rights reserved.
4 * This code is derived from software contributed to The DragonFly Project
5 * by Matthew Dillon <dillon@backplane.com> and was subsequently ported
6 * to FreeBSD by Michael Gmelin <freebsd@grem.de>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in
16 * the documentation and/or other materials provided with the
18 * 3. Neither the name of The DragonFly Project nor the names of its
19 * contributors may be used to endorse or promote products derived
20 * from this software without specific, prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
25 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
26 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 #include <sys/cdefs.h>
37 __FBSDID("$FreeBSD$");
40 * Intel fourth generation mobile cpus integrated I2C device.
42 * See ig4_reg.h for datasheet reference and notes.
45 #include <sys/param.h>
46 #include <sys/systm.h>
47 #include <sys/kernel.h>
48 #include <sys/module.h>
49 #include <sys/errno.h>
51 #include <sys/mutex.h>
53 #include <sys/syslog.h>
56 #include <machine/bus.h>
58 #include <machine/resource.h>
60 #include <dev/pci/pcivar.h>
61 #include <dev/pci/pcireg.h>
62 #include <dev/iicbus/iiconf.h>
64 #include <dev/ichiic/ig4_reg.h>
65 #include <dev/ichiic/ig4_var.h>
67 static int ig4iic_pci_detach(device_t dev);
69 #define PCI_CHIP_LYNXPT_LP_I2C_1 0x9c618086
70 #define PCI_CHIP_LYNXPT_LP_I2C_2 0x9c628086
71 #define PCI_CHIP_BRASWELL_I2C_1 0x22c18086
72 #define PCI_CHIP_BRASWELL_I2C_2 0x22c28086
73 #define PCI_CHIP_BRASWELL_I2C_3 0x22c38086
74 #define PCI_CHIP_BRASWELL_I2C_5 0x22c58086
75 #define PCI_CHIP_BRASWELL_I2C_6 0x22c68086
76 #define PCI_CHIP_BRASWELL_I2C_7 0x22c78086
77 #define PCI_CHIP_SKYLAKE_I2C_0 0x9d608086
78 #define PCI_CHIP_SKYLAKE_I2C_1 0x9d618086
79 #define PCI_CHIP_SKYLAKE_I2C_2 0x9d628086
80 #define PCI_CHIP_SKYLAKE_I2C_3 0x9d638086
81 #define PCI_CHIP_SKYLAKE_I2C_4 0x9d648086
82 #define PCI_CHIP_SKYLAKE_I2C_5 0x9d658086
83 #define PCI_CHIP_KABYLAKE_I2C_0 0xa1608086
84 #define PCI_CHIP_KABYLAKE_I2C_1 0xa1618086
85 #define PCI_CHIP_APL_I2C_0 0x5aac8086
86 #define PCI_CHIP_APL_I2C_1 0x5aae8086
87 #define PCI_CHIP_APL_I2C_2 0x5ab08086
88 #define PCI_CHIP_APL_I2C_3 0x5ab28086
89 #define PCI_CHIP_APL_I2C_4 0x5ab48086
90 #define PCI_CHIP_APL_I2C_5 0x5ab68086
91 #define PCI_CHIP_APL_I2C_6 0x5ab88086
92 #define PCI_CHIP_APL_I2C_7 0x5aba8086
94 struct ig4iic_pci_device {
97 enum ig4_vers version;
100 static struct ig4iic_pci_device ig4iic_pci_devices[] = {
101 { PCI_CHIP_LYNXPT_LP_I2C_1, "Intel Lynx Point-LP I2C Controller-1", IG4_HASWELL},
102 { PCI_CHIP_LYNXPT_LP_I2C_2, "Intel Lynx Point-LP I2C Controller-2", IG4_HASWELL},
103 { PCI_CHIP_BRASWELL_I2C_1, "Intel Braswell Serial I/O I2C Port 1", IG4_ATOM},
104 { PCI_CHIP_BRASWELL_I2C_2, "Intel Braswell Serial I/O I2C Port 2", IG4_ATOM},
105 { PCI_CHIP_BRASWELL_I2C_3, "Intel Braswell Serial I/O I2C Port 3", IG4_ATOM},
106 { PCI_CHIP_BRASWELL_I2C_5, "Intel Braswell Serial I/O I2C Port 5", IG4_ATOM},
107 { PCI_CHIP_BRASWELL_I2C_6, "Intel Braswell Serial I/O I2C Port 6", IG4_ATOM},
108 { PCI_CHIP_BRASWELL_I2C_7, "Intel Braswell Serial I/O I2C Port 7", IG4_ATOM},
109 { PCI_CHIP_SKYLAKE_I2C_0, "Intel Sunrise Point-LP I2C Controller-0", IG4_SKYLAKE},
110 { PCI_CHIP_SKYLAKE_I2C_1, "Intel Sunrise Point-LP I2C Controller-1", IG4_SKYLAKE},
111 { PCI_CHIP_SKYLAKE_I2C_2, "Intel Sunrise Point-LP I2C Controller-2", IG4_SKYLAKE},
112 { PCI_CHIP_SKYLAKE_I2C_3, "Intel Sunrise Point-LP I2C Controller-3", IG4_SKYLAKE},
113 { PCI_CHIP_SKYLAKE_I2C_4, "Intel Sunrise Point-LP I2C Controller-4", IG4_SKYLAKE},
114 { PCI_CHIP_SKYLAKE_I2C_5, "Intel Sunrise Point-LP I2C Controller-5", IG4_SKYLAKE},
115 { PCI_CHIP_KABYLAKE_I2C_0, "Intel Sunrise Point-H I2C Controller-0", IG4_SKYLAKE},
116 { PCI_CHIP_KABYLAKE_I2C_1, "Intel Sunrise Point-H I2C Controller-1", IG4_SKYLAKE},
117 { PCI_CHIP_APL_I2C_0, "Intel Apollo Lake I2C Controller-0", IG4_APL},
118 { PCI_CHIP_APL_I2C_1, "Intel Apollo Lake I2C Controller-1", IG4_APL},
119 { PCI_CHIP_APL_I2C_2, "Intel Apollo Lake I2C Controller-2", IG4_APL},
120 { PCI_CHIP_APL_I2C_3, "Intel Apollo Lake I2C Controller-3", IG4_APL},
121 { PCI_CHIP_APL_I2C_4, "Intel Apollo Lake I2C Controller-4", IG4_APL},
122 { PCI_CHIP_APL_I2C_5, "Intel Apollo Lake I2C Controller-5", IG4_APL},
123 { PCI_CHIP_APL_I2C_6, "Intel Apollo Lake I2C Controller-6", IG4_APL},
124 { PCI_CHIP_APL_I2C_7, "Intel Apollo Lake I2C Controller-7", IG4_APL}
128 ig4iic_pci_probe(device_t dev)
130 ig4iic_softc_t *sc = device_get_softc(dev);
134 devid = pci_get_devid(dev);
135 for (i = 0; i < nitems(ig4iic_pci_devices); i++) {
136 if (ig4iic_pci_devices[i].devid == devid) {
137 device_set_desc(dev, ig4iic_pci_devices[i].desc);
138 sc->version = ig4iic_pci_devices[i].version;
139 return (BUS_PROBE_DEFAULT);
146 ig4iic_pci_attach(device_t dev)
148 ig4iic_softc_t *sc = device_get_softc(dev);
152 sc->regs_rid = PCIR_BAR(0);
153 sc->regs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
154 &sc->regs_rid, RF_ACTIVE);
155 if (sc->regs_res == NULL) {
156 device_printf(dev, "unable to map registers\n");
157 ig4iic_pci_detach(dev);
161 if (pci_alloc_msi(dev, &sc->intr_rid)) {
162 device_printf(dev, "Using MSI\n");
164 sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
165 &sc->intr_rid, RF_SHAREABLE | RF_ACTIVE);
166 if (sc->intr_res == NULL) {
167 device_printf(dev, "unable to map interrupt\n");
168 ig4iic_pci_detach(dev);
171 sc->platform_attached = 1;
173 error = ig4iic_attach(sc);
175 ig4iic_pci_detach(dev);
181 ig4iic_pci_detach(device_t dev)
183 ig4iic_softc_t *sc = device_get_softc(dev);
186 if (sc->platform_attached) {
187 error = ig4iic_detach(sc);
190 sc->platform_attached = 0;
194 bus_release_resource(dev, SYS_RES_IRQ,
195 sc->intr_rid, sc->intr_res);
198 if (sc->intr_rid != 0)
199 pci_release_msi(dev);
201 bus_release_resource(dev, SYS_RES_MEMORY,
202 sc->regs_rid, sc->regs_res);
210 ig4iic_pci_suspend(device_t dev)
212 ig4iic_softc_t *sc = device_get_softc(dev);
214 return (ig4iic_suspend(sc));
218 ig4iic_pci_resume(device_t dev)
220 ig4iic_softc_t *sc = device_get_softc(dev);
222 return (ig4iic_resume(sc));
225 static device_method_t ig4iic_pci_methods[] = {
226 /* Device interface */
227 DEVMETHOD(device_probe, ig4iic_pci_probe),
228 DEVMETHOD(device_attach, ig4iic_pci_attach),
229 DEVMETHOD(device_detach, ig4iic_pci_detach),
230 DEVMETHOD(device_suspend, ig4iic_pci_suspend),
231 DEVMETHOD(device_resume, ig4iic_pci_resume),
233 DEVMETHOD(iicbus_transfer, ig4iic_transfer),
234 DEVMETHOD(iicbus_reset, ig4iic_reset),
235 DEVMETHOD(iicbus_callback, ig4iic_callback),
240 static driver_t ig4iic_pci_driver = {
243 sizeof(struct ig4iic_softc)
246 DRIVER_MODULE_ORDERED(ig4iic, pci, ig4iic_pci_driver, ig4iic_devclass, 0, 0,
248 MODULE_DEPEND(ig4iic, pci, 1, 1, 1);
249 MODULE_PNP_INFO("W32:vendor/device", pci, ig4iic, ig4iic_pci_devices,
250 nitems(ig4iic_pci_devices));