4 * Author: Archie Cobbs <archie@freebsd.org>
5 * Copyright (c) 2000 Whistle Communications, Inc.
7 * Author: Archie Cobbs <archie@freebsd.org>
9 * Subject to the following obligations and disclaimer of warranty, use and
10 * redistribution of this software, in source or object code forms, with or
11 * without modifications are expressly permitted by Whistle Communications;
12 * provided, however, that:
13 * 1. Any and all reproductions of the source or object code must include the
14 * copyright notice above and the following disclaimer of warranties; and
15 * 2. No rights are granted, in any manner or form, to use Whistle
16 * Communications, Inc. trademarks, including the mark "WHISTLE
17 * COMMUNICATIONS" on advertising, endorsements, or otherwise except as
18 * such appears in the above copyright notice or in the software.
20 * THIS SOFTWARE IS BEING PROVIDED BY WHISTLE COMMUNICATIONS "AS IS", AND
21 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, WHISTLE COMMUNICATIONS MAKES NO
22 * REPRESENTATIONS OR WARRANTIES, EXPRESS OR IMPLIED, REGARDING THIS SOFTWARE,
23 * INCLUDING WITHOUT LIMITATION, ANY AND ALL IMPLIED WARRANTIES OF
24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
25 * WHISTLE COMMUNICATIONS DOES NOT WARRANT, GUARANTEE, OR MAKE ANY
26 * REPRESENTATIONS REGARDING THE USE OF, OR THE RESULTS OF THE USE OF THIS
27 * SOFTWARE IN TERMS OF ITS CORRECTNESS, ACCURACY, RELIABILITY OR OTHERWISE.
28 * IN NO EVENT SHALL WHISTLE COMMUNICATIONS BE LIABLE FOR ANY DAMAGES
29 * RESULTING FROM OR ARISING OUT OF ANY USE OF THIS SOFTWARE, INCLUDING
30 * WITHOUT LIMITATION, ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
31 * PUNITIVE, OR CONSEQUENTIAL DAMAGES, PROCUREMENT OF SUBSTITUTE GOODS OR
32 * SERVICES, LOSS OF USE, DATA OR PROFITS, HOWEVER CAUSED AND UNDER ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
35 * THIS SOFTWARE, EVEN IF WHISTLE COMMUNICATIONS IS ADVISED OF THE POSSIBILITY
39 #include <sys/cdefs.h>
40 __FBSDID("$FreeBSD$");
43 * Support for the SMBus controller logical device which is part of the
44 * Intel 81801AA/AB/BA/CA/DC/EB (ICH/ICH[02345]) I/O controller hub chips.
47 #include <sys/param.h>
48 #include <sys/systm.h>
49 #include <sys/kernel.h>
50 #include <sys/module.h>
51 #include <sys/errno.h>
53 #include <sys/mutex.h>
54 #include <sys/syslog.h>
57 #include <machine/bus.h>
59 #include <machine/resource.h>
61 #include <dev/pci/pcivar.h>
62 #include <dev/pci/pcireg.h>
64 #include <dev/smbus/smbconf.h>
66 #include <dev/ichsmb/ichsmb_var.h>
67 #include <dev/ichsmb/ichsmb_reg.h>
69 /* PCI unique identifiers */
70 #define ID_82801AA 0x24138086
71 #define ID_82801AB 0x24238086
72 #define ID_82801BA 0x24438086
73 #define ID_82801CA 0x24838086
74 #define ID_82801DC 0x24C38086
75 #define ID_82801EB 0x24D38086
76 #define ID_82801FB 0x266A8086
77 #define ID_82801GB 0x27da8086
78 #define ID_82801H 0x283e8086
79 #define ID_82801I 0x29308086
80 #define ID_82801JI 0x3a308086
81 #define ID_PCH 0x3b308086
82 #define ID_6300ESB 0x25a48086
83 #define ID_631xESB 0x269b8086
84 #define ID_DH89XXCC 0x23308086
85 #define ID_PATSBURG 0x1d228086
86 #define ID_CPT 0x1c228086
87 #define ID_PPT 0x1e228086
88 #define ID_AVOTON 0x1f3c8086
89 #define ID_COLETOCRK 0x23B08086
90 #define ID_LPT 0x8c228086
91 #define ID_WCPT 0x8ca28086
92 #define ID_WCPTLP 0x9ca28086
94 #define PCIS_SERIALBUS_SMBUS_PROGIF 0x00
96 /* Internal functions */
97 static int ichsmb_pci_probe(device_t dev);
98 static int ichsmb_pci_attach(device_t dev);
99 /*Use generic one for now*/
101 static int ichsmb_pci_detach(device_t dev);
105 static device_method_t ichsmb_pci_methods[] = {
106 /* Device interface */
107 DEVMETHOD(device_probe, ichsmb_pci_probe),
108 DEVMETHOD(device_attach, ichsmb_pci_attach),
109 DEVMETHOD(device_detach, ichsmb_detach),
112 DEVMETHOD(smbus_callback, ichsmb_callback),
113 DEVMETHOD(smbus_quick, ichsmb_quick),
114 DEVMETHOD(smbus_sendb, ichsmb_sendb),
115 DEVMETHOD(smbus_recvb, ichsmb_recvb),
116 DEVMETHOD(smbus_writeb, ichsmb_writeb),
117 DEVMETHOD(smbus_writew, ichsmb_writew),
118 DEVMETHOD(smbus_readb, ichsmb_readb),
119 DEVMETHOD(smbus_readw, ichsmb_readw),
120 DEVMETHOD(smbus_pcall, ichsmb_pcall),
121 DEVMETHOD(smbus_bwrite, ichsmb_bwrite),
122 DEVMETHOD(smbus_bread, ichsmb_bread),
127 static driver_t ichsmb_pci_driver = {
130 sizeof(struct ichsmb_softc)
133 static devclass_t ichsmb_pci_devclass;
135 DRIVER_MODULE(ichsmb, pci, ichsmb_pci_driver, ichsmb_pci_devclass, 0, 0);
138 ichsmb_pci_probe(device_t dev)
140 /* Check PCI identifier */
141 switch (pci_get_devid(dev)) {
143 device_set_desc(dev, "Intel 82801AA (ICH) SMBus controller");
146 device_set_desc(dev, "Intel 82801AB (ICH0) SMBus controller");
149 device_set_desc(dev, "Intel 82801BA (ICH2) SMBus controller");
152 device_set_desc(dev, "Intel 82801CA (ICH3) SMBus controller");
155 device_set_desc(dev, "Intel 82801DC (ICH4) SMBus controller");
158 device_set_desc(dev, "Intel 82801EB (ICH5) SMBus controller");
161 device_set_desc(dev, "Intel 82801FB (ICH6) SMBus controller");
164 device_set_desc(dev, "Intel 82801GB (ICH7) SMBus controller");
167 device_set_desc(dev, "Intel 82801H (ICH8) SMBus controller");
170 device_set_desc(dev, "Intel 82801I (ICH9) SMBus controller");
173 device_set_desc(dev, "Intel 82801JI (ICH10) SMBus controller");
176 device_set_desc(dev, "Intel PCH SMBus controller");
179 device_set_desc(dev, "Intel 6300ESB (ICH) SMBus controller");
182 device_set_desc(dev, "Intel 631xESB/6321ESB (ESB2) SMBus controller");
185 device_set_desc(dev, "Intel DH89xxCC SMBus controller");
188 device_set_desc(dev, "Intel Patsburg SMBus controller");
191 device_set_desc(dev, "Intel Cougar Point SMBus controller");
194 device_set_desc(dev, "Intel Panther Point SMBus controller");
197 device_set_desc(dev, "Intel Avoton SMBus controller");
200 device_set_desc(dev, "Intel Lynx Point SMBus controller");
203 device_set_desc(dev, "Intel Wildcat Point SMBus controller");
206 device_set_desc(dev, "Intel Wildcat Point-LP SMBus controller");
209 device_set_desc(dev, "Intel Coleto Creek SMBus controller");
216 return (ichsmb_probe(dev));
220 ichsmb_pci_attach(device_t dev)
222 const sc_p sc = device_get_softc(dev);
225 /* Initialize private state */
226 bzero(sc, sizeof(*sc));
230 /* Allocate an I/O range */
231 sc->io_rid = ICH_SMB_BASE;
232 sc->io_res = bus_alloc_resource(dev, SYS_RES_IOPORT,
233 &sc->io_rid, 0, ~0, 16, RF_ACTIVE);
234 if (sc->io_res == NULL)
235 sc->io_res = bus_alloc_resource(dev, SYS_RES_IOPORT,
236 &sc->io_rid, 0ul, ~0ul, 32, RF_ACTIVE);
237 if (sc->io_res == NULL) {
238 device_printf(dev, "can't map I/O\n");
243 /* Allocate interrupt */
245 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
246 &sc->irq_rid, RF_ACTIVE | RF_SHAREABLE);
247 if (sc->irq_res == NULL) {
248 device_printf(dev, "can't get IRQ\n");
254 pci_write_config(dev, ICH_HOSTC, ICH_HOSTC_HST_EN, 1);
257 error = ichsmb_attach(dev);
263 /* Attach failed, release resources */
264 ichsmb_release_resources(sc);
269 MODULE_DEPEND(ichsmb, pci, 1, 1, 1);
270 MODULE_DEPEND(ichsmb, smbus, SMBUS_MINVER, SMBUS_PREFVER, SMBUS_MAXVER);
271 MODULE_VERSION(ichsmb, 1);