2 * Copyright (c) 2004 Texas A&M University
5 * Developer: Wm. Daryl Hawkins
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * Intel ICH Watchdog Timer (WDT) driver
32 * Originally developed by Wm. Daryl Hawkins of Texas A&M
33 * Heavily modified by <des@FreeBSD.org>
35 * This is a tricky one. The ICH WDT can't be treated as a regular PCI
36 * device as it's actually an integrated function of the ICH LPC interface
37 * bridge. Detection is also awkward, because we can only infer the
38 * presence of the watchdog timer from the fact that the machine has an
39 * ICH chipset, or, on ACPI 2.x systems, by the presence of the 'WDDT'
40 * ACPI table (although this driver does not support the ACPI detection
43 * There is one slight problem on non-ACPI or ACPI 1.x systems: we have no
44 * way of knowing if the WDT is permanently disabled (either by the BIOS
47 * The WDT is programmed through I/O registers in the ACPI I/O space.
48 * Intel swears it's always at offset 0x60, so we use that.
50 * For details about the ICH WDT, see Intel Application Note AP-725
51 * (document no. 292273-001). The WDT is also described in the individual
52 * chipset datasheets, e.g. Intel82801EB ICH5 / 82801ER ICH5R Datasheet
53 * (document no. 252516-001) sections 9.10 and 9.11.
55 * ICH6/7/8 support by Takeharu KATO <takeharu1219@ybb.ne.jp>
58 #include <sys/cdefs.h>
59 __FBSDID("$FreeBSD$");
61 #include <sys/param.h>
62 #include <sys/kernel.h>
63 #include <sys/module.h>
64 #include <sys/systm.h>
66 #include <machine/bus.h>
68 #include <machine/resource.h>
69 #include <sys/watchdog.h>
71 #include <isa/isavar.h>
72 #include <dev/pci/pcivar.h>
74 #include <dev/ichwd/ichwd.h>
76 static struct ichwd_device ichwd_devices[] = {
77 { DEVICEID_82801AA, "Intel 82801AA watchdog timer", 1 },
78 { DEVICEID_82801AB, "Intel 82801AB watchdog timer", 1 },
79 { DEVICEID_82801BA, "Intel 82801BA watchdog timer", 2 },
80 { DEVICEID_82801BAM, "Intel 82801BAM watchdog timer", 2 },
81 { DEVICEID_82801CA, "Intel 82801CA watchdog timer", 3 },
82 { DEVICEID_82801CAM, "Intel 82801CAM watchdog timer", 3 },
83 { DEVICEID_82801DB, "Intel 82801DB watchdog timer", 4 },
84 { DEVICEID_82801DBM, "Intel 82801DBM watchdog timer", 4 },
85 { DEVICEID_82801E, "Intel 82801E watchdog timer", 5 },
86 { DEVICEID_82801EB, "Intel 82801EB watchdog timer", 5 },
87 { DEVICEID_82801EBR, "Intel 82801EB/ER watchdog timer", 5 },
88 { DEVICEID_6300ESB, "Intel 6300ESB watchdog timer", 5 },
89 { DEVICEID_82801FBR, "Intel 82801FB/FR watchdog timer", 6 },
90 { DEVICEID_ICH6M, "Intel ICH6M watchdog timer", 6 },
91 { DEVICEID_ICH6W, "Intel ICH6W watchdog timer", 6 },
92 { DEVICEID_ICH7, "Intel ICH7 watchdog timer", 7 },
93 { DEVICEID_ICH7DH, "Intel ICH7DH watchdog timer", 7 },
94 { DEVICEID_ICH7M, "Intel ICH7M watchdog timer", 7 },
95 { DEVICEID_ICH7MDH, "Intel ICH7MDH watchdog timer", 7 },
96 { DEVICEID_NM10, "Intel NM10 watchdog timer", 7 },
97 { DEVICEID_ICH8, "Intel ICH8 watchdog timer", 8 },
98 { DEVICEID_ICH8DH, "Intel ICH8DH watchdog timer", 8 },
99 { DEVICEID_ICH8DO, "Intel ICH8DO watchdog timer", 8 },
100 { DEVICEID_ICH8M, "Intel ICH8M watchdog timer", 8 },
101 { DEVICEID_ICH8ME, "Intel ICH8M-E watchdog timer", 8 },
102 { DEVICEID_63XXESB, "Intel 63XXESB watchdog timer", 8 },
103 { DEVICEID_ICH9, "Intel ICH9 watchdog timer", 9 },
104 { DEVICEID_ICH9DH, "Intel ICH9DH watchdog timer", 9 },
105 { DEVICEID_ICH9DO, "Intel ICH9DO watchdog timer", 9 },
106 { DEVICEID_ICH9M, "Intel ICH9M watchdog timer", 9 },
107 { DEVICEID_ICH9ME, "Intel ICH9M-E watchdog timer", 9 },
108 { DEVICEID_ICH9R, "Intel ICH9R watchdog timer", 9 },
109 { DEVICEID_ICH10, "Intel ICH10 watchdog timer", 10 },
110 { DEVICEID_ICH10D, "Intel ICH10D watchdog timer", 10 },
111 { DEVICEID_ICH10DO, "Intel ICH10DO watchdog timer", 10 },
112 { DEVICEID_ICH10R, "Intel ICH10R watchdog timer", 10 },
113 { DEVICEID_H55, "Intel H55 watchdog timer", 10 },
117 static devclass_t ichwd_devclass;
119 #define ichwd_read_tco_1(sc, off) \
120 bus_space_read_1((sc)->tco_bst, (sc)->tco_bsh, (off))
121 #define ichwd_read_tco_2(sc, off) \
122 bus_space_read_2((sc)->tco_bst, (sc)->tco_bsh, (off))
123 #define ichwd_read_tco_4(sc, off) \
124 bus_space_read_4((sc)->tco_bst, (sc)->tco_bsh, (off))
125 #define ichwd_read_smi_4(sc, off) \
126 bus_space_read_4((sc)->smi_bst, (sc)->smi_bsh, (off))
127 #define ichwd_read_gcs_4(sc, off) \
128 bus_space_read_4((sc)->gcs_bst, (sc)->gcs_bsh, (off))
130 #define ichwd_write_tco_1(sc, off, val) \
131 bus_space_write_1((sc)->tco_bst, (sc)->tco_bsh, (off), (val))
132 #define ichwd_write_tco_2(sc, off, val) \
133 bus_space_write_2((sc)->tco_bst, (sc)->tco_bsh, (off), (val))
134 #define ichwd_write_tco_4(sc, off, val) \
135 bus_space_write_4((sc)->tco_bst, (sc)->tco_bsh, (off), (val))
136 #define ichwd_write_smi_4(sc, off, val) \
137 bus_space_write_4((sc)->smi_bst, (sc)->smi_bsh, (off), (val))
138 #define ichwd_write_gcs_4(sc, off, val) \
139 bus_space_write_4((sc)->gcs_bst, (sc)->gcs_bsh, (off), (val))
141 #define ichwd_verbose_printf(dev, ...) \
144 device_printf(dev, __VA_ARGS__);\
148 * Disable the watchdog timeout SMI handler.
150 * Apparently, some BIOSes install handlers that reset or disable the
151 * watchdog timer instead of resetting the system, so we disable the SMI
152 * (by clearing the SMI_TCO_EN bit of the SMI_EN register) to prevent this
156 ichwd_smi_disable(struct ichwd_softc *sc)
158 ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) & ~SMI_TCO_EN);
162 * Enable the watchdog timeout SMI handler. See above for details.
165 ichwd_smi_enable(struct ichwd_softc *sc)
167 ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) | SMI_TCO_EN);
171 * Reset the watchdog status bits.
174 ichwd_sts_reset(struct ichwd_softc *sc)
177 * The watchdog status bits are set to 1 by the hardware to
178 * indicate various conditions. They can be cleared by software
179 * by writing a 1, not a 0.
181 ichwd_write_tco_2(sc, TCO1_STS, TCO_TIMEOUT);
183 * XXX The datasheet says that TCO_SECOND_TO_STS must be cleared
184 * before TCO_BOOT_STS, not the other way around.
186 ichwd_write_tco_2(sc, TCO2_STS, TCO_BOOT_STS);
187 ichwd_write_tco_2(sc, TCO2_STS, TCO_SECOND_TO_STS);
191 * Enable the watchdog timer by clearing the TCO_TMR_HALT bit in the
192 * TCO1_CNT register. This is complicated by the need to preserve bit 9
193 * of that same register, and the requirement that all other bits must be
194 * written back as zero.
197 ichwd_tmr_enable(struct ichwd_softc *sc)
201 cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE;
202 ichwd_write_tco_2(sc, TCO1_CNT, cnt & ~TCO_TMR_HALT);
204 ichwd_verbose_printf(sc->device, "timer enabled\n");
208 * Disable the watchdog timer. See above for details.
211 ichwd_tmr_disable(struct ichwd_softc *sc)
215 cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE;
216 ichwd_write_tco_2(sc, TCO1_CNT, cnt | TCO_TMR_HALT);
218 ichwd_verbose_printf(sc->device, "timer disabled\n");
222 * Reload the watchdog timer: writing anything to any of the lower five
223 * bits of the TCO_RLD register reloads the timer from the last value
224 * written to TCO_TMR.
227 ichwd_tmr_reload(struct ichwd_softc *sc)
229 if (sc->ich_version <= 5)
230 ichwd_write_tco_1(sc, TCO_RLD, 1);
232 ichwd_write_tco_2(sc, TCO_RLD, 1);
234 ichwd_verbose_printf(sc->device, "timer reloaded\n");
238 * Set the initial timeout value. Note that this must always be followed
242 ichwd_tmr_set(struct ichwd_softc *sc, unsigned int timeout)
246 * If the datasheets are to be believed, the minimum value
247 * actually varies from chipset to chipset - 4 for ICH5 and 2 for
248 * all other chipsets. I suspect this is a bug in the ICH5
249 * datasheet and that the minimum is uniformly 2, but I'd rather
250 * err on the side of caution.
255 if (sc->ich_version <= 5) {
256 uint8_t tmr_val8 = ichwd_read_tco_1(sc, TCO_TMR1);
262 ichwd_write_tco_1(sc, TCO_TMR1, tmr_val8);
264 uint16_t tmr_val16 = ichwd_read_tco_2(sc, TCO_TMR2);
267 if (timeout > 0x03ff)
269 tmr_val16 |= timeout;
270 ichwd_write_tco_2(sc, TCO_TMR2, tmr_val16);
273 sc->timeout = timeout;
275 ichwd_verbose_printf(sc->device, "timeout set to %u ticks\n", timeout);
279 ichwd_clear_noreboot(struct ichwd_softc *sc)
284 /* try to clear the NO_REBOOT bit */
285 if (sc->ich_version <= 5) {
286 status = pci_read_config(sc->ich, ICH_GEN_STA, 1);
287 status &= ~ICH_GEN_STA_NO_REBOOT;
288 pci_write_config(sc->ich, ICH_GEN_STA, status, 1);
289 status = pci_read_config(sc->ich, ICH_GEN_STA, 1);
290 if (status & ICH_GEN_STA_NO_REBOOT)
293 status = ichwd_read_gcs_4(sc, 0);
294 status &= ~ICH_GCS_NO_REBOOT;
295 ichwd_write_gcs_4(sc, 0, status);
296 status = ichwd_read_gcs_4(sc, 0);
297 if (status & ICH_GCS_NO_REBOOT)
302 device_printf(sc->device,
303 "ICH WDT present but disabled in BIOS or hardware\n");
309 * Watchdog event handler - called by the framework to enable or disable
310 * the watchdog or change the initial timeout value.
313 ichwd_event(void *arg, unsigned int cmd, int *error)
315 struct ichwd_softc *sc = arg;
316 unsigned int timeout;
318 /* convert from power-of-two-ns to WDT ticks */
320 timeout = ((uint64_t)1 << cmd) / ICHWD_TICK;
322 if (timeout != sc->timeout) {
324 ichwd_tmr_enable(sc);
325 ichwd_tmr_set(sc, timeout);
327 ichwd_tmr_reload(sc);
331 ichwd_tmr_disable(sc);
336 ichwd_find_ich_lpc_bridge(struct ichwd_device **id_p)
338 struct ichwd_device *id;
341 /* look for an ICH LPC interface bridge */
342 for (id = ichwd_devices; id->desc != NULL; ++id)
343 if ((ich = pci_find_device(VENDORID_INTEL, id->device)) != NULL)
349 ichwd_verbose_printf(ich, "found ICH%d or equivalent chipset: %s\n",
350 id->version, id->desc);
359 * Look for an ICH LPC interface bridge. If one is found, register an
360 * ichwd device. There can be only one.
363 ichwd_identify(driver_t *driver, device_t parent)
365 struct ichwd_device *id_p;
371 ich = ichwd_find_ich_lpc_bridge(&id_p);
375 /* good, add child to bus */
376 if ((dev = device_find_child(parent, driver->name, 0)) == NULL)
377 dev = BUS_ADD_CHILD(parent, 0, driver->name, 0);
382 device_set_desc_copy(dev, id_p->desc);
384 if (id_p->version >= 6) {
385 /* get RCBA (root complex base address) */
386 rcba = pci_read_config(ich, ICH_RCBA, 4);
387 rc = bus_set_resource(ich, SYS_RES_MEMORY, 0,
388 (rcba & 0xffffc000) + ICH_GCS_OFFSET, ICH_GCS_SIZE);
390 ichwd_verbose_printf(dev,
391 "Can not set memory resource for RCBA\n");
396 ichwd_probe(device_t dev)
399 /* Do not claim some ISA PnP device by accident. */
400 if (isa_get_logicalid(dev) != 0)
406 ichwd_attach(device_t dev)
408 struct ichwd_softc *sc;
409 struct ichwd_device *id_p;
411 unsigned int pmbase = 0;
413 sc = device_get_softc(dev);
416 ich = ichwd_find_ich_lpc_bridge(&id_p);
418 device_printf(sc->device, "Can not find ICH device.\n");
422 sc->ich_version = id_p->version;
424 /* get ACPI base address */
425 pmbase = pci_read_config(ich, ICH_PMBASE, 2) & ICH_PMBASE_MASK;
427 device_printf(dev, "ICH PMBASE register is empty\n");
431 /* allocate I/O register space */
433 sc->smi_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->smi_rid,
434 pmbase + SMI_BASE, pmbase + SMI_BASE + SMI_LEN - 1, SMI_LEN,
435 RF_ACTIVE | RF_SHAREABLE);
436 if (sc->smi_res == NULL) {
437 device_printf(dev, "unable to reserve SMI registers\n");
440 sc->smi_bst = rman_get_bustag(sc->smi_res);
441 sc->smi_bsh = rman_get_bushandle(sc->smi_res);
444 sc->tco_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->tco_rid,
445 pmbase + TCO_BASE, pmbase + TCO_BASE + TCO_LEN - 1, TCO_LEN,
446 RF_ACTIVE | RF_SHAREABLE);
447 if (sc->tco_res == NULL) {
448 device_printf(dev, "unable to reserve TCO registers\n");
451 sc->tco_bst = rman_get_bustag(sc->tco_res);
452 sc->tco_bsh = rman_get_bushandle(sc->tco_res);
455 if (sc->ich_version >= 6) {
456 sc->gcs_res = bus_alloc_resource_any(ich, SYS_RES_MEMORY,
457 &sc->gcs_rid, RF_ACTIVE|RF_SHAREABLE);
458 if (sc->gcs_res == NULL) {
459 device_printf(dev, "unable to reserve GCS registers\n");
462 sc->gcs_bst = rman_get_bustag(sc->gcs_res);
463 sc->gcs_bsh = rman_get_bushandle(sc->gcs_res);
470 if (ichwd_clear_noreboot(sc) != 0)
473 device_printf(dev, "%s (ICH%d or equivalent)\n",
474 device_get_desc(dev), sc->ich_version);
477 * XXX we should check the status registers (specifically, the
478 * TCO_SECOND_TO_STS bit in the TCO2_STS register) to see if we
479 * just came back from a watchdog-induced reset, and let the user
483 /* reset the watchdog status registers */
486 /* make sure the WDT starts out inactive */
487 ichwd_tmr_disable(sc);
489 /* register the watchdog event handler */
490 sc->ev_tag = EVENTHANDLER_REGISTER(watchdog_list, ichwd_event, sc, 0);
492 /* disable the SMI handler */
493 ichwd_smi_disable(sc);
497 sc = device_get_softc(dev);
498 if (sc->tco_res != NULL)
499 bus_release_resource(dev, SYS_RES_IOPORT,
500 sc->tco_rid, sc->tco_res);
501 if (sc->smi_res != NULL)
502 bus_release_resource(dev, SYS_RES_IOPORT,
503 sc->smi_rid, sc->smi_res);
504 if (sc->gcs_res != NULL)
505 bus_release_resource(ich, SYS_RES_MEMORY,
506 sc->gcs_rid, sc->gcs_res);
512 ichwd_detach(device_t dev)
514 struct ichwd_softc *sc;
517 sc = device_get_softc(dev);
519 /* halt the watchdog timer */
521 ichwd_tmr_disable(sc);
523 /* enable the SMI handler */
524 ichwd_smi_enable(sc);
526 /* deregister event handler */
527 if (sc->ev_tag != NULL)
528 EVENTHANDLER_DEREGISTER(watchdog_list, sc->ev_tag);
531 /* reset the watchdog status registers */
534 /* deallocate I/O register space */
535 bus_release_resource(dev, SYS_RES_IOPORT, sc->tco_rid, sc->tco_res);
536 bus_release_resource(dev, SYS_RES_IOPORT, sc->smi_rid, sc->smi_res);
538 /* deallocate memory resource */
539 ich = ichwd_find_ich_lpc_bridge(NULL);
540 if (sc->gcs_res && ich)
541 bus_release_resource(ich, SYS_RES_MEMORY, sc->gcs_rid, sc->gcs_res);
546 static device_method_t ichwd_methods[] = {
547 DEVMETHOD(device_identify, ichwd_identify),
548 DEVMETHOD(device_probe, ichwd_probe),
549 DEVMETHOD(device_attach, ichwd_attach),
550 DEVMETHOD(device_detach, ichwd_detach),
551 DEVMETHOD(device_shutdown, ichwd_detach),
555 static driver_t ichwd_driver = {
558 sizeof(struct ichwd_softc),
562 ichwd_modevent(module_t mode, int type, void *data)
568 printf("ichwd module loaded\n");
571 printf("ichwd module unloaded\n");
574 printf("ichwd module shutting down\n");
580 DRIVER_MODULE(ichwd, isa, ichwd_driver, ichwd_devclass, ichwd_modevent, NULL);