2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2004 Texas A&M University
7 * Developer: Wm. Daryl Hawkins
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * Intel ICH Watchdog Timer (WDT) driver
34 * Originally developed by Wm. Daryl Hawkins of Texas A&M
35 * Heavily modified by <des@FreeBSD.org>
37 * This is a tricky one. The ICH WDT can't be treated as a regular PCI
38 * device as it's actually an integrated function of the ICH LPC interface
39 * bridge. Detection is also awkward, because we can only infer the
40 * presence of the watchdog timer from the fact that the machine has an
41 * ICH chipset, or, on ACPI 2.x systems, by the presence of the 'WDDT'
42 * ACPI table (although this driver does not support the ACPI detection
45 * There is one slight problem on non-ACPI or ACPI 1.x systems: we have no
46 * way of knowing if the WDT is permanently disabled (either by the BIOS
49 * The WDT is programmed through I/O registers in the ACPI I/O space.
50 * Intel swears it's always at offset 0x60, so we use that.
52 * For details about the ICH WDT, see Intel Application Note AP-725
53 * (document no. 292273-001). The WDT is also described in the individual
54 * chipset datasheets, e.g. Intel82801EB ICH5 / 82801ER ICH5R Datasheet
55 * (document no. 252516-001) sections 9.10 and 9.11.
57 * ICH6/7/8 support by Takeharu KATO <takeharu1219@ybb.ne.jp>
58 * SoC PMC support by Denir Li <denir.li@cas-well.com>
61 #include <sys/cdefs.h>
62 __FBSDID("$FreeBSD$");
64 #include <sys/param.h>
65 #include <sys/eventhandler.h>
66 #include <sys/kernel.h>
67 #include <sys/module.h>
68 #include <sys/systm.h>
70 #include <machine/bus.h>
72 #include <machine/resource.h>
73 #include <sys/watchdog.h>
75 #include <isa/isavar.h>
76 #include <dev/pci/pcivar.h>
78 #include <dev/ichwd/ichwd.h>
80 #include <x86/pci_cfgreg.h>
81 #include <dev/pci/pcivar.h>
82 #include <dev/pci/pci_private.h>
84 static struct ichwd_device ichwd_devices[] = {
85 { DEVICEID_82801AA, "Intel 82801AA watchdog timer", 1, 1 },
86 { DEVICEID_82801AB, "Intel 82801AB watchdog timer", 1, 1 },
87 { DEVICEID_82801BA, "Intel 82801BA watchdog timer", 2, 1 },
88 { DEVICEID_82801BAM, "Intel 82801BAM watchdog timer", 2, 1 },
89 { DEVICEID_82801CA, "Intel 82801CA watchdog timer", 3, 1 },
90 { DEVICEID_82801CAM, "Intel 82801CAM watchdog timer", 3, 1 },
91 { DEVICEID_82801DB, "Intel 82801DB watchdog timer", 4, 1 },
92 { DEVICEID_82801DBM, "Intel 82801DBM watchdog timer", 4, 1 },
93 { DEVICEID_82801E, "Intel 82801E watchdog timer", 5, 1 },
94 { DEVICEID_82801EB, "Intel 82801EB watchdog timer", 5, 1 },
95 { DEVICEID_82801EBR, "Intel 82801EB/ER watchdog timer", 5, 1 },
96 { DEVICEID_6300ESB, "Intel 6300ESB watchdog timer", 5, 1 },
97 { DEVICEID_82801FBR, "Intel 82801FB/FR watchdog timer", 6, 2 },
98 { DEVICEID_ICH6M, "Intel ICH6M watchdog timer", 6, 2 },
99 { DEVICEID_ICH6W, "Intel ICH6W watchdog timer", 6, 2 },
100 { DEVICEID_ICH7, "Intel ICH7 watchdog timer", 7, 2 },
101 { DEVICEID_ICH7DH, "Intel ICH7DH watchdog timer", 7, 2 },
102 { DEVICEID_ICH7M, "Intel ICH7M watchdog timer", 7, 2 },
103 { DEVICEID_ICH7MDH, "Intel ICH7MDH watchdog timer", 7, 2 },
104 { DEVICEID_NM10, "Intel NM10 watchdog timer", 7, 2 },
105 { DEVICEID_ICH8, "Intel ICH8 watchdog timer", 8, 2 },
106 { DEVICEID_ICH8DH, "Intel ICH8DH watchdog timer", 8, 2 },
107 { DEVICEID_ICH8DO, "Intel ICH8DO watchdog timer", 8, 2 },
108 { DEVICEID_ICH8M, "Intel ICH8M watchdog timer", 8, 2 },
109 { DEVICEID_ICH8ME, "Intel ICH8M-E watchdog timer", 8, 2 },
110 { DEVICEID_63XXESB, "Intel 63XXESB watchdog timer", 8, 2 },
111 { DEVICEID_ICH9, "Intel ICH9 watchdog timer", 9, 2 },
112 { DEVICEID_ICH9DH, "Intel ICH9DH watchdog timer", 9, 2 },
113 { DEVICEID_ICH9DO, "Intel ICH9DO watchdog timer", 9, 2 },
114 { DEVICEID_ICH9M, "Intel ICH9M watchdog timer", 9, 2 },
115 { DEVICEID_ICH9ME, "Intel ICH9M-E watchdog timer", 9, 2 },
116 { DEVICEID_ICH9R, "Intel ICH9R watchdog timer", 9, 2 },
117 { DEVICEID_ICH10, "Intel ICH10 watchdog timer", 10, 2 },
118 { DEVICEID_ICH10D, "Intel ICH10D watchdog timer", 10, 2 },
119 { DEVICEID_ICH10DO, "Intel ICH10DO watchdog timer", 10, 2 },
120 { DEVICEID_ICH10R, "Intel ICH10R watchdog timer", 10, 2 },
121 { DEVICEID_PCH, "Intel PCH watchdog timer", 10, 2 },
122 { DEVICEID_PCHM, "Intel PCH watchdog timer", 10, 2 },
123 { DEVICEID_P55, "Intel P55 watchdog timer", 10, 2 },
124 { DEVICEID_PM55, "Intel PM55 watchdog timer", 10, 2 },
125 { DEVICEID_H55, "Intel H55 watchdog timer", 10, 2 },
126 { DEVICEID_QM57, "Intel QM57 watchdog timer", 10, 2 },
127 { DEVICEID_H57, "Intel H57 watchdog timer", 10, 2 },
128 { DEVICEID_HM55, "Intel HM55 watchdog timer", 10, 2 },
129 { DEVICEID_Q57, "Intel Q57 watchdog timer", 10, 2 },
130 { DEVICEID_HM57, "Intel HM57 watchdog timer", 10, 2 },
131 { DEVICEID_PCHMSFF, "Intel PCHMSFF watchdog timer", 10, 2 },
132 { DEVICEID_QS57, "Intel QS57 watchdog timer", 10, 2 },
133 { DEVICEID_3400, "Intel 3400 watchdog timer", 10, 2 },
134 { DEVICEID_3420, "Intel 3420 watchdog timer", 10, 2 },
135 { DEVICEID_3450, "Intel 3450 watchdog timer", 10, 2 },
136 { DEVICEID_CPT0, "Intel Cougar Point watchdog timer", 10, 2 },
137 { DEVICEID_CPT1, "Intel Cougar Point watchdog timer", 10, 2 },
138 { DEVICEID_CPT2, "Intel Cougar Point watchdog timer", 10, 2 },
139 { DEVICEID_CPT3, "Intel Cougar Point watchdog timer", 10, 2 },
140 { DEVICEID_CPT4, "Intel Cougar Point watchdog timer", 10, 2 },
141 { DEVICEID_CPT5, "Intel Cougar Point watchdog timer", 10, 2 },
142 { DEVICEID_CPT6, "Intel Cougar Point watchdog timer", 10, 2 },
143 { DEVICEID_CPT7, "Intel Cougar Point watchdog timer", 10, 2 },
144 { DEVICEID_CPT8, "Intel Cougar Point watchdog timer", 10, 2 },
145 { DEVICEID_CPT9, "Intel Cougar Point watchdog timer", 10, 2 },
146 { DEVICEID_CPT10, "Intel Cougar Point watchdog timer", 10, 2 },
147 { DEVICEID_CPT11, "Intel Cougar Point watchdog timer", 10, 2 },
148 { DEVICEID_CPT12, "Intel Cougar Point watchdog timer", 10, 2 },
149 { DEVICEID_CPT13, "Intel Cougar Point watchdog timer", 10, 2 },
150 { DEVICEID_CPT14, "Intel Cougar Point watchdog timer", 10, 2 },
151 { DEVICEID_CPT15, "Intel Cougar Point watchdog timer", 10, 2 },
152 { DEVICEID_CPT16, "Intel Cougar Point watchdog timer", 10, 2 },
153 { DEVICEID_CPT17, "Intel Cougar Point watchdog timer", 10, 2 },
154 { DEVICEID_CPT18, "Intel Cougar Point watchdog timer", 10, 2 },
155 { DEVICEID_CPT19, "Intel Cougar Point watchdog timer", 10, 2 },
156 { DEVICEID_CPT20, "Intel Cougar Point watchdog timer", 10, 2 },
157 { DEVICEID_CPT21, "Intel Cougar Point watchdog timer", 10, 2 },
158 { DEVICEID_CPT22, "Intel Cougar Point watchdog timer", 10, 2 },
159 { DEVICEID_CPT23, "Intel Cougar Point watchdog timer", 10, 2 },
160 { DEVICEID_CPT24, "Intel Cougar Point watchdog timer", 10, 2 },
161 { DEVICEID_CPT25, "Intel Cougar Point watchdog timer", 10, 2 },
162 { DEVICEID_CPT26, "Intel Cougar Point watchdog timer", 10, 2 },
163 { DEVICEID_CPT27, "Intel Cougar Point watchdog timer", 10, 2 },
164 { DEVICEID_CPT28, "Intel Cougar Point watchdog timer", 10, 2 },
165 { DEVICEID_CPT29, "Intel Cougar Point watchdog timer", 10, 2 },
166 { DEVICEID_CPT30, "Intel Cougar Point watchdog timer", 10, 2 },
167 { DEVICEID_CPT31, "Intel Cougar Point watchdog timer", 10, 2 },
168 { DEVICEID_PATSBURG_LPC1, "Intel Patsburg watchdog timer", 10, 2 },
169 { DEVICEID_PATSBURG_LPC2, "Intel Patsburg watchdog timer", 10, 2 },
170 { DEVICEID_PPT0, "Intel Panther Point watchdog timer", 10, 2 },
171 { DEVICEID_PPT1, "Intel Panther Point watchdog timer", 10, 2 },
172 { DEVICEID_PPT2, "Intel Panther Point watchdog timer", 10, 2 },
173 { DEVICEID_PPT3, "Intel Panther Point watchdog timer", 10, 2 },
174 { DEVICEID_PPT4, "Intel Panther Point watchdog timer", 10, 2 },
175 { DEVICEID_PPT5, "Intel Panther Point watchdog timer", 10, 2 },
176 { DEVICEID_PPT6, "Intel Panther Point watchdog timer", 10, 2 },
177 { DEVICEID_PPT7, "Intel Panther Point watchdog timer", 10, 2 },
178 { DEVICEID_PPT8, "Intel Panther Point watchdog timer", 10, 2 },
179 { DEVICEID_PPT9, "Intel Panther Point watchdog timer", 10, 2 },
180 { DEVICEID_PPT10, "Intel Panther Point watchdog timer", 10, 2 },
181 { DEVICEID_PPT11, "Intel Panther Point watchdog timer", 10, 2 },
182 { DEVICEID_PPT12, "Intel Panther Point watchdog timer", 10, 2 },
183 { DEVICEID_PPT13, "Intel Panther Point watchdog timer", 10, 2 },
184 { DEVICEID_PPT14, "Intel Panther Point watchdog timer", 10, 2 },
185 { DEVICEID_PPT15, "Intel Panther Point watchdog timer", 10, 2 },
186 { DEVICEID_PPT16, "Intel Panther Point watchdog timer", 10, 2 },
187 { DEVICEID_PPT17, "Intel Panther Point watchdog timer", 10, 2 },
188 { DEVICEID_PPT18, "Intel Panther Point watchdog timer", 10, 2 },
189 { DEVICEID_PPT19, "Intel Panther Point watchdog timer", 10, 2 },
190 { DEVICEID_PPT20, "Intel Panther Point watchdog timer", 10, 2 },
191 { DEVICEID_PPT21, "Intel Panther Point watchdog timer", 10, 2 },
192 { DEVICEID_PPT22, "Intel Panther Point watchdog timer", 10, 2 },
193 { DEVICEID_PPT23, "Intel Panther Point watchdog timer", 10, 2 },
194 { DEVICEID_PPT24, "Intel Panther Point watchdog timer", 10, 2 },
195 { DEVICEID_PPT25, "Intel Panther Point watchdog timer", 10, 2 },
196 { DEVICEID_PPT26, "Intel Panther Point watchdog timer", 10, 2 },
197 { DEVICEID_PPT27, "Intel Panther Point watchdog timer", 10, 2 },
198 { DEVICEID_PPT28, "Intel Panther Point watchdog timer", 10, 2 },
199 { DEVICEID_PPT29, "Intel Panther Point watchdog timer", 10, 2 },
200 { DEVICEID_PPT30, "Intel Panther Point watchdog timer", 10, 2 },
201 { DEVICEID_PPT31, "Intel Panther Point watchdog timer", 10, 2 },
202 { DEVICEID_LPT0, "Intel Lynx Point watchdog timer", 10, 2 },
203 { DEVICEID_LPT1, "Intel Lynx Point watchdog timer", 10, 2 },
204 { DEVICEID_LPT2, "Intel Lynx Point watchdog timer", 10, 2 },
205 { DEVICEID_LPT3, "Intel Lynx Point watchdog timer", 10, 2 },
206 { DEVICEID_LPT4, "Intel Lynx Point watchdog timer", 10, 2 },
207 { DEVICEID_LPT5, "Intel Lynx Point watchdog timer", 10, 2 },
208 { DEVICEID_LPT6, "Intel Lynx Point watchdog timer", 10, 2 },
209 { DEVICEID_LPT7, "Intel Lynx Point watchdog timer", 10, 2 },
210 { DEVICEID_LPT8, "Intel Lynx Point watchdog timer", 10, 2 },
211 { DEVICEID_LPT9, "Intel Lynx Point watchdog timer", 10, 2 },
212 { DEVICEID_LPT10, "Intel Lynx Point watchdog timer", 10, 2 },
213 { DEVICEID_LPT11, "Intel Lynx Point watchdog timer", 10, 2 },
214 { DEVICEID_LPT12, "Intel Lynx Point watchdog timer", 10, 2 },
215 { DEVICEID_LPT13, "Intel Lynx Point watchdog timer", 10, 2 },
216 { DEVICEID_LPT14, "Intel Lynx Point watchdog timer", 10, 2 },
217 { DEVICEID_LPT15, "Intel Lynx Point watchdog timer", 10, 2 },
218 { DEVICEID_LPT16, "Intel Lynx Point watchdog timer", 10, 2 },
219 { DEVICEID_LPT17, "Intel Lynx Point watchdog timer", 10, 2 },
220 { DEVICEID_LPT18, "Intel Lynx Point watchdog timer", 10, 2 },
221 { DEVICEID_LPT19, "Intel Lynx Point watchdog timer", 10, 2 },
222 { DEVICEID_LPT20, "Intel Lynx Point watchdog timer", 10, 2 },
223 { DEVICEID_LPT21, "Intel Lynx Point watchdog timer", 10, 2 },
224 { DEVICEID_LPT22, "Intel Lynx Point watchdog timer", 10, 2 },
225 { DEVICEID_LPT23, "Intel Lynx Point watchdog timer", 10, 2 },
226 { DEVICEID_LPT24, "Intel Lynx Point watchdog timer", 10, 2 },
227 { DEVICEID_LPT25, "Intel Lynx Point watchdog timer", 10, 2 },
228 { DEVICEID_LPT26, "Intel Lynx Point watchdog timer", 10, 2 },
229 { DEVICEID_LPT27, "Intel Lynx Point watchdog timer", 10, 2 },
230 { DEVICEID_LPT28, "Intel Lynx Point watchdog timer", 10, 2 },
231 { DEVICEID_LPT29, "Intel Lynx Point watchdog timer", 10, 2 },
232 { DEVICEID_LPT30, "Intel Lynx Point watchdog timer", 10, 2 },
233 { DEVICEID_LPT31, "Intel Lynx Point watchdog timer", 10, 2 },
234 { DEVICEID_WCPT1, "Intel Wildcat Point watchdog timer", 10, 2 },
235 { DEVICEID_WCPT2, "Intel Wildcat Point watchdog timer", 10, 2 },
236 { DEVICEID_WCPT3, "Intel Wildcat Point watchdog timer", 10, 2 },
237 { DEVICEID_WCPT4, "Intel Wildcat Point watchdog timer", 10, 2 },
238 { DEVICEID_WCPT6, "Intel Wildcat Point watchdog timer", 10, 2 },
239 { DEVICEID_WBG0, "Intel Wellsburg watchdog timer", 10, 2 },
240 { DEVICEID_WBG1, "Intel Wellsburg watchdog timer", 10, 2 },
241 { DEVICEID_WBG2, "Intel Wellsburg watchdog timer", 10, 2 },
242 { DEVICEID_WBG3, "Intel Wellsburg watchdog timer", 10, 2 },
243 { DEVICEID_WBG4, "Intel Wellsburg watchdog timer", 10, 2 },
244 { DEVICEID_WBG5, "Intel Wellsburg watchdog timer", 10, 2 },
245 { DEVICEID_WBG6, "Intel Wellsburg watchdog timer", 10, 2 },
246 { DEVICEID_WBG7, "Intel Wellsburg watchdog timer", 10, 2 },
247 { DEVICEID_WBG8, "Intel Wellsburg watchdog timer", 10, 2 },
248 { DEVICEID_WBG9, "Intel Wellsburg watchdog timer", 10, 2 },
249 { DEVICEID_WBG10, "Intel Wellsburg watchdog timer", 10, 2 },
250 { DEVICEID_WBG11, "Intel Wellsburg watchdog timer", 10, 2 },
251 { DEVICEID_WBG12, "Intel Wellsburg watchdog timer", 10, 2 },
252 { DEVICEID_WBG13, "Intel Wellsburg watchdog timer", 10, 2 },
253 { DEVICEID_WBG14, "Intel Wellsburg watchdog timer", 10, 2 },
254 { DEVICEID_WBG15, "Intel Wellsburg watchdog timer", 10, 2 },
255 { DEVICEID_WBG16, "Intel Wellsburg watchdog timer", 10, 2 },
256 { DEVICEID_WBG17, "Intel Wellsburg watchdog timer", 10, 2 },
257 { DEVICEID_WBG18, "Intel Wellsburg watchdog timer", 10, 2 },
258 { DEVICEID_WBG19, "Intel Wellsburg watchdog timer", 10, 2 },
259 { DEVICEID_WBG20, "Intel Wellsburg watchdog timer", 10, 2 },
260 { DEVICEID_WBG21, "Intel Wellsburg watchdog timer", 10, 2 },
261 { DEVICEID_WBG22, "Intel Wellsburg watchdog timer", 10, 2 },
262 { DEVICEID_WBG23, "Intel Wellsburg watchdog timer", 10, 2 },
263 { DEVICEID_WBG24, "Intel Wellsburg watchdog timer", 10, 2 },
264 { DEVICEID_WBG25, "Intel Wellsburg watchdog timer", 10, 2 },
265 { DEVICEID_WBG26, "Intel Wellsburg watchdog timer", 10, 2 },
266 { DEVICEID_WBG27, "Intel Wellsburg watchdog timer", 10, 2 },
267 { DEVICEID_WBG28, "Intel Wellsburg watchdog timer", 10, 2 },
268 { DEVICEID_WBG29, "Intel Wellsburg watchdog timer", 10, 2 },
269 { DEVICEID_WBG30, "Intel Wellsburg watchdog timer", 10, 2 },
270 { DEVICEID_WBG31, "Intel Wellsburg watchdog timer", 10, 2 },
271 { DEVICEID_LPT_LP0, "Intel Lynx Point-LP watchdog timer", 10, 2 },
272 { DEVICEID_LPT_LP1, "Intel Lynx Point-LP watchdog timer", 10, 2 },
273 { DEVICEID_LPT_LP2, "Intel Lynx Point-LP watchdog timer", 10, 2 },
274 { DEVICEID_LPT_LP3, "Intel Lynx Point-LP watchdog timer", 10, 2 },
275 { DEVICEID_LPT_LP4, "Intel Lynx Point-LP watchdog timer", 10, 2 },
276 { DEVICEID_LPT_LP5, "Intel Lynx Point-LP watchdog timer", 10, 2 },
277 { DEVICEID_LPT_LP6, "Intel Lynx Point-LP watchdog timer", 10, 2 },
278 { DEVICEID_LPT_LP7, "Intel Lynx Point-LP watchdog timer", 10, 2 },
279 { DEVICEID_WCPT_LP1, "Intel Wildcat Point-LP watchdog timer", 10, 2 },
280 { DEVICEID_WCPT_LP2, "Intel Wildcat Point-LP watchdog timer", 10, 2 },
281 { DEVICEID_WCPT_LP3, "Intel Wildcat Point-LP watchdog timer", 10, 2 },
282 { DEVICEID_WCPT_LP5, "Intel Wildcat Point-LP watchdog timer", 10, 2 },
283 { DEVICEID_WCPT_LP6, "Intel Wildcat Point-LP watchdog timer", 10, 2 },
284 { DEVICEID_WCPT_LP7, "Intel Wildcat Point-LP watchdog timer", 10, 2 },
285 { DEVICEID_WCPT_LP9, "Intel Wildcat Point-LP watchdog timer", 10, 2 },
286 { DEVICEID_DH89XXCC_LPC, "Intel DH89xxCC watchdog timer", 10, 2 },
287 { DEVICEID_COLETOCRK_LPC, "Intel Coleto Creek watchdog timer", 10, 2 },
288 { DEVICEID_AVN0, "Intel Avoton/Rangeley SoC watchdog timer",10, 3 },
289 { DEVICEID_AVN1, "Intel Avoton/Rangeley SoC watchdog timer",10, 3 },
290 { DEVICEID_AVN2, "Intel Avoton/Rangeley SoC watchdog timer",10, 3 },
291 { DEVICEID_AVN3, "Intel Avoton/Rangeley SoC watchdog timer",10, 3 },
292 { DEVICEID_BAYTRAIL, "Intel Bay Trail SoC watchdog timer", 10, 3 },
293 { DEVICEID_BRASWELL, "Intel Braswell SoC watchdog timer", 10, 3 },
297 static struct ichwd_device ichwd_smb_devices[] = {
298 { DEVICEID_LEWISBURG_SMB, "Lewisburg watchdog timer", 10, 4 },
299 { DEVICEID_SRPTLP_SMB, "Sunrise Point-LP watchdog timer", 10, 4 },
303 static devclass_t ichwd_devclass;
305 #define ichwd_read_tco_1(sc, off) \
306 bus_read_1((sc)->tco_res, (off))
307 #define ichwd_read_tco_2(sc, off) \
308 bus_read_2((sc)->tco_res, (off))
309 #define ichwd_read_tco_4(sc, off) \
310 bus_read_4((sc)->tco_res, (off))
311 #define ichwd_read_smi_4(sc, off) \
312 bus_read_4((sc)->smi_res, (off))
313 #define ichwd_read_gcs_4(sc, off) \
314 bus_read_4((sc)->gcs_res, (off))
315 /* NB: TCO version 3 devices use the gcs_res resource for the PMC register. */
316 #define ichwd_read_pmc_4(sc, off) \
317 bus_read_4((sc)->gcs_res, (off))
318 #define ichwd_read_gc_4(sc, off) \
319 bus_read_4((sc)->gc_res, (off))
321 #define ichwd_write_tco_1(sc, off, val) \
322 bus_write_1((sc)->tco_res, (off), (val))
323 #define ichwd_write_tco_2(sc, off, val) \
324 bus_write_2((sc)->tco_res, (off), (val))
325 #define ichwd_write_tco_4(sc, off, val) \
326 bus_write_4((sc)->tco_res, (off), (val))
327 #define ichwd_write_smi_4(sc, off, val) \
328 bus_write_4((sc)->smi_res, (off), (val))
329 #define ichwd_write_gcs_4(sc, off, val) \
330 bus_write_4((sc)->gcs_res, (off), (val))
331 /* NB: TCO version 3 devices use the gcs_res resource for the PMC register. */
332 #define ichwd_write_pmc_4(sc, off, val) \
333 bus_write_4((sc)->gcs_res, (off), (val))
334 #define ichwd_write_gc_4(sc, off, val) \
335 bus_write_4((sc)->gc_res, (off), (val))
337 #define ichwd_verbose_printf(dev, ...) \
340 device_printf(dev, __VA_ARGS__);\
344 * Disable the watchdog timeout SMI handler.
346 * Apparently, some BIOSes install handlers that reset or disable the
347 * watchdog timer instead of resetting the system, so we disable the SMI
348 * (by clearing the SMI_TCO_EN bit of the SMI_EN register) to prevent this
352 ichwd_smi_disable(struct ichwd_softc *sc)
354 ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) & ~SMI_TCO_EN);
358 * Enable the watchdog timeout SMI handler. See above for details.
361 ichwd_smi_enable(struct ichwd_softc *sc)
363 ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) | SMI_TCO_EN);
367 * Check if the watchdog SMI triggering is enabled.
370 ichwd_smi_is_enabled(struct ichwd_softc *sc)
372 return ((ichwd_read_smi_4(sc, SMI_EN) & SMI_TCO_EN) != 0);
376 * Reset the watchdog status bits.
379 ichwd_sts_reset(struct ichwd_softc *sc)
382 * The watchdog status bits are set to 1 by the hardware to
383 * indicate various conditions. They can be cleared by software
384 * by writing a 1, not a 0.
386 ichwd_write_tco_2(sc, TCO1_STS, TCO_TIMEOUT);
388 * According to Intel's docs, clearing SECOND_TO_STS and BOOT_STS must
389 * be done in two separate operations.
391 ichwd_write_tco_2(sc, TCO2_STS, TCO_SECOND_TO_STS);
392 if (sc->tco_version < 4)
393 ichwd_write_tco_2(sc, TCO2_STS, TCO_BOOT_STS);
397 * Enable the watchdog timer by clearing the TCO_TMR_HALT bit in the
398 * TCO1_CNT register. This is complicated by the need to preserve bit 9
399 * of that same register, and the requirement that all other bits must be
400 * written back as zero.
403 ichwd_tmr_enable(struct ichwd_softc *sc)
407 cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE;
408 ichwd_write_tco_2(sc, TCO1_CNT, cnt & ~TCO_TMR_HALT);
410 ichwd_verbose_printf(sc->device, "timer enabled\n");
414 * Disable the watchdog timer. See above for details.
417 ichwd_tmr_disable(struct ichwd_softc *sc)
421 cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE;
422 ichwd_write_tco_2(sc, TCO1_CNT, cnt | TCO_TMR_HALT);
424 ichwd_verbose_printf(sc->device, "timer disabled\n");
428 * Reload the watchdog timer: writing anything to any of the lower five
429 * bits of the TCO_RLD register reloads the timer from the last value
430 * written to TCO_TMR.
433 ichwd_tmr_reload(struct ichwd_softc *sc)
435 if (sc->tco_version == 1)
436 ichwd_write_tco_1(sc, TCO_RLD, 1);
438 ichwd_write_tco_2(sc, TCO_RLD, 1);
442 * Set the initial timeout value. Note that this must always be followed
446 ichwd_tmr_set(struct ichwd_softc *sc, unsigned int timeout)
449 if (timeout < TCO_RLD_TMR_MIN)
450 timeout = TCO_RLD_TMR_MIN;
452 if (sc->tco_version == 1) {
453 uint8_t tmr_val8 = ichwd_read_tco_1(sc, TCO_TMR1);
455 tmr_val8 &= (~TCO_RLD1_TMR_MAX & 0xff);
456 if (timeout > TCO_RLD1_TMR_MAX)
457 timeout = TCO_RLD1_TMR_MAX;
459 ichwd_write_tco_1(sc, TCO_TMR1, tmr_val8);
461 uint16_t tmr_val16 = ichwd_read_tco_2(sc, TCO_TMR2);
463 tmr_val16 &= (~TCO_RLD2_TMR_MAX & 0xffff);
464 if (timeout > TCO_RLD2_TMR_MAX)
465 timeout = TCO_RLD2_TMR_MAX;
466 tmr_val16 |= timeout;
467 ichwd_write_tco_2(sc, TCO_TMR2, tmr_val16);
470 sc->timeout = timeout;
472 ichwd_verbose_printf(sc->device, "timeout set to %u ticks\n", timeout);
476 ichwd_clear_noreboot(struct ichwd_softc *sc)
481 /* try to clear the NO_REBOOT bit */
482 switch (sc->tco_version) {
484 status = pci_read_config(sc->ich, ICH_GEN_STA, 1);
485 status &= ~ICH_GEN_STA_NO_REBOOT;
486 pci_write_config(sc->ich, ICH_GEN_STA, status, 1);
487 status = pci_read_config(sc->ich, ICH_GEN_STA, 1);
488 if (status & ICH_GEN_STA_NO_REBOOT)
492 status = ichwd_read_gcs_4(sc, 0);
493 status &= ~ICH_GCS_NO_REBOOT;
494 ichwd_write_gcs_4(sc, 0, status);
495 status = ichwd_read_gcs_4(sc, 0);
496 if (status & ICH_GCS_NO_REBOOT)
500 status = ichwd_read_pmc_4(sc, 0);
501 status &= ~ICH_PMC_NO_REBOOT;
502 ichwd_write_pmc_4(sc, 0, status);
503 status = ichwd_read_pmc_4(sc, 0);
504 if (status & ICH_PMC_NO_REBOOT)
508 status = ichwd_read_gc_4(sc, 0);
509 status &= ~SMB_GC_NO_REBOOT;
510 ichwd_write_gc_4(sc, 0, status);
511 status = ichwd_read_gc_4(sc, 0);
512 if (status & SMB_GC_NO_REBOOT)
516 ichwd_verbose_printf(sc->device,
517 "Unknown TCO Version: %d, can't set NO_REBOOT.\n",
523 device_printf(sc->device,
524 "ICH WDT present but disabled in BIOS or hardware\n");
530 * Watchdog event handler - called by the framework to enable or disable
531 * the watchdog or change the initial timeout value.
534 ichwd_event(void *arg, unsigned int cmd, int *error)
536 struct ichwd_softc *sc = arg;
537 unsigned int timeout;
539 /* convert from power-of-two-ns to WDT ticks */
542 if (sc->tco_version == 3) {
543 timeout = ((uint64_t)1 << cmd) / ICHWD_TCO_V3_TICK;
545 timeout = ((uint64_t)1 << cmd) / ICHWD_TICK;
550 ichwd_tmr_enable(sc);
551 if (timeout != sc->timeout)
552 ichwd_tmr_set(sc, timeout);
553 ichwd_tmr_reload(sc);
557 ichwd_tmr_disable(sc);
562 ichwd_find_ich_lpc_bridge(device_t isa, struct ichwd_device **id_p)
564 struct ichwd_device *id;
568 /* Check whether parent ISA bridge looks familiar. */
569 isab = device_get_parent(isa);
570 pci = device_get_parent(isab);
571 if (pci == NULL || device_get_devclass(pci) != devclass_find("pci"))
573 if (pci_get_vendor(isab) != VENDORID_INTEL)
575 devid = pci_get_device(isab);
576 for (id = ichwd_devices; id->desc != NULL; ++id) {
577 if (devid == id->device) {
588 ichwd_find_smb_dev(device_t isa, struct ichwd_device **id_p)
590 struct ichwd_device *id;
595 * Check if SMBus controller provides TCO configuration.
596 * The controller's device and function are fixed and we expect
597 * it to be on the same bus as ISA bridge.
599 isab = device_get_parent(isa);
600 smb = pci_find_dbsf(pci_get_domain(isab), pci_get_bus(isab), 31, 4);
603 if (pci_get_vendor(smb) != VENDORID_INTEL)
605 devid = pci_get_device(smb);
606 for (id = ichwd_smb_devices; id->desc != NULL; ++id) {
607 if (devid == id->device) {
618 * Look for an ICH LPC interface bridge. If one is found, register an
619 * ichwd device. There can be only one.
622 ichwd_identify(driver_t *driver, device_t parent)
624 struct ichwd_device *id_p;
627 uint64_t base_address64;
628 uint32_t base_address;
632 ich = ichwd_find_ich_lpc_bridge(parent, &id_p);
634 smb = ichwd_find_smb_dev(parent, &id_p);
639 KASSERT(id_p->tco_version >= 1,
640 ("unexpected TCO version %d", id_p->tco_version));
641 KASSERT(id_p->tco_version != 4 || smb != NULL,
642 ("could not find PCI SMBus device for TCOv4"));
643 KASSERT(id_p->tco_version >= 4 || ich != NULL,
644 ("could not find PCI LPC bridge device for TCOv1-3"));
646 /* good, add child to bus */
647 if ((dev = device_find_child(parent, driver->name, 0)) == NULL)
648 dev = BUS_ADD_CHILD(parent, 0, driver->name, 0);
653 switch (id_p->tco_version) {
657 /* get RCBA (root complex base address) */
658 base_address = pci_read_config(ich, ICH_RCBA, 4);
659 rc = bus_set_resource(ich, SYS_RES_MEMORY, 0,
660 (base_address & 0xffffc000) + ICH_GCS_OFFSET,
663 ichwd_verbose_printf(dev,
664 "Can not set TCO v%d memory resource for RCBA\n",
668 /* get PBASE (Power Management Controller base address) */
669 base_address = pci_read_config(ich, ICH_PBASE, 4);
670 rc = bus_set_resource(ich, SYS_RES_MEMORY, 0,
671 (base_address & 0xfffffe00) + ICH_PMC_OFFSET,
674 ichwd_verbose_printf(dev,
675 "Can not set TCO v%d memory resource for PBASE\n",
679 /* Get TCO base address. */
680 ctl = pci_read_config(smb, ICH_TCOCTL, 4);
681 if ((ctl & ICH_TCOCTL_TCO_BASE_EN) == 0) {
682 ichwd_verbose_printf(dev,
683 "TCO v%d decoding is not enabled\n",
687 base_address = pci_read_config(smb, ICH_TCOBASE, 4);
688 rc = bus_set_resource(dev, SYS_RES_IOPORT, 0,
689 base_address & ICH_TCOBASE_ADDRMASK, ICH_TCOBASE_SIZE);
691 ichwd_verbose_printf(dev,
692 "Can not set TCO v%d I/O resource (err = %d)\n",
693 id_p->tco_version, rc);
697 * Unhide Primary to Sideband Bridge (P2SB) PCI device, so that
698 * we can discover the base address of Private Configuration
699 * Space via the bridge's BAR.
700 * Then hide back the bridge.
702 pci_cfgregwrite(0, 31, 1, 0xe1, 0, 1);
703 base_address64 = pci_cfgregread(0, 31, 1, SBREG_BAR + 4, 4);
704 base_address64 <<= 32;
705 base_address64 |= pci_cfgregread(0, 31, 1, SBREG_BAR, 4);
706 base_address64 &= ~0xfull;
707 pci_cfgregwrite(0, 31, 1, 0xe1, 1, 1);
710 * No Reboot bit is in General Control register, offset 0xc,
711 * within the SMBus target port, ID 0xc6.
713 base_address64 += PCR_REG_OFF(SMB_PORT_ID, SMB_GC_REG);
714 rc = bus_set_resource(dev, SYS_RES_MEMORY, 1, base_address64,
717 ichwd_verbose_printf(dev,
718 "Can not set TCO v%d PCR I/O resource (err = %d)\n",
719 id_p->tco_version, rc);
724 ichwd_verbose_printf(dev,
725 "Can not set unknown TCO v%d memory resource for unknown base address\n",
732 ichwd_probe(device_t dev)
734 struct ichwd_device *id_p;
736 /* Do not claim some ISA PnP device by accident. */
737 if (isa_get_logicalid(dev) != 0)
740 if (ichwd_find_ich_lpc_bridge(device_get_parent(dev), &id_p) == NULL &&
741 ichwd_find_smb_dev(device_get_parent(dev), &id_p) == NULL)
744 device_set_desc_copy(dev, id_p->desc);
749 ichwd_smb_attach(device_t dev)
751 struct ichwd_softc *sc;
752 struct ichwd_device *id_p;
753 device_t isab, pmdev;
757 sc = device_get_softc(dev);
758 smb = ichwd_find_smb_dev(device_get_parent(dev), &id_p);
762 sc->ich_version = id_p->ich_version;
763 sc->tco_version = id_p->tco_version;
765 /* Allocate TCO control I/O register space. */
767 sc->tco_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->tco_rid,
768 RF_ACTIVE | RF_SHAREABLE);
769 if (sc->tco_res == NULL) {
770 device_printf(dev, "unable to reserve TCO registers\n");
775 * Allocate General Control I/O register in PCH
776 * Private Configuration Space (PCR).
779 sc->gc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->gc_rid,
780 RF_ACTIVE | RF_SHAREABLE);
781 if (sc->gc_res == NULL) {
782 device_printf(dev, "unable to reserve hidden P2SB registers\n");
786 /* Get ACPI base address. */
787 isab = device_get_parent(device_get_parent(dev));
788 pmdev = pci_find_dbsf(pci_get_domain(isab), pci_get_bus(isab), 31, 2);
790 device_printf(dev, "unable to find Power Management device\n");
793 acpi_base = pci_read_config(pmdev, ICH_PMBASE, 4) & 0xffffff00;
794 if (acpi_base == 0) {
795 device_printf(dev, "ACPI base address is not set\n");
799 /* Allocate SMI control I/O register space. */
801 sc->smi_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->smi_rid,
802 acpi_base + SMI_BASE, acpi_base + SMI_BASE + SMI_LEN - 1, SMI_LEN,
803 RF_ACTIVE | RF_SHAREABLE);
804 if (sc->smi_res == NULL) {
805 device_printf(dev, "unable to reserve SMI registers\n");
813 ichwd_lpc_attach(device_t dev)
815 struct ichwd_softc *sc;
816 struct ichwd_device *id_p;
818 unsigned int pmbase = 0;
820 sc = device_get_softc(dev);
822 ich = ichwd_find_ich_lpc_bridge(device_get_parent(dev), &id_p);
827 sc->ich_version = id_p->ich_version;
828 sc->tco_version = id_p->tco_version;
830 /* get ACPI base address */
831 pmbase = pci_read_config(ich, ICH_PMBASE, 2) & ICH_PMBASE_MASK;
833 device_printf(dev, "ICH PMBASE register is empty\n");
837 /* allocate I/O register space */
839 sc->smi_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->smi_rid,
840 pmbase + SMI_BASE, pmbase + SMI_BASE + SMI_LEN - 1, SMI_LEN,
841 RF_ACTIVE | RF_SHAREABLE);
842 if (sc->smi_res == NULL) {
843 device_printf(dev, "unable to reserve SMI registers\n");
848 sc->tco_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->tco_rid,
849 pmbase + TCO_BASE, pmbase + TCO_BASE + TCO_LEN - 1, TCO_LEN,
850 RF_ACTIVE | RF_SHAREABLE);
851 if (sc->tco_res == NULL) {
852 device_printf(dev, "unable to reserve TCO registers\n");
857 if (sc->tco_version >= 2) {
858 sc->gcs_res = bus_alloc_resource_any(ich, SYS_RES_MEMORY,
859 &sc->gcs_rid, RF_ACTIVE|RF_SHAREABLE);
860 if (sc->gcs_res == NULL) {
861 device_printf(dev, "unable to reserve GCS registers\n");
870 ichwd_attach(device_t dev)
872 struct ichwd_softc *sc;
874 sc = device_get_softc(dev);
877 if (ichwd_lpc_attach(dev) != 0 && ichwd_smb_attach(dev) != 0)
880 if (ichwd_clear_noreboot(sc) != 0)
884 * Determine if we are coming up after a watchdog-induced reset. Some
885 * BIOSes may clear this bit at bootup, preventing us from reporting
886 * this case on such systems. We clear this bit in ichwd_sts_reset().
888 if ((ichwd_read_tco_2(sc, TCO2_STS) & TCO_SECOND_TO_STS) != 0)
890 "resuming after hardware watchdog timeout\n");
892 /* reset the watchdog status registers */
895 /* make sure the WDT starts out inactive */
896 ichwd_tmr_disable(sc);
898 /* register the watchdog event handler */
899 sc->ev_tag = EVENTHANDLER_REGISTER(watchdog_list, ichwd_event, sc, 0);
901 /* disable the SMI handler */
902 sc->smi_enabled = ichwd_smi_is_enabled(sc);
903 ichwd_smi_disable(sc);
907 sc = device_get_softc(dev);
908 if (sc->tco_res != NULL)
909 bus_release_resource(dev, SYS_RES_IOPORT,
910 sc->tco_rid, sc->tco_res);
911 if (sc->smi_res != NULL)
912 bus_release_resource(dev, SYS_RES_IOPORT,
913 sc->smi_rid, sc->smi_res);
914 if (sc->gcs_res != NULL)
915 bus_release_resource(sc->ich, SYS_RES_MEMORY,
916 sc->gcs_rid, sc->gcs_res);
917 if (sc->gc_res != NULL)
918 bus_release_resource(dev, SYS_RES_MEMORY,
919 sc->gc_rid, sc->gc_res);
925 ichwd_detach(device_t dev)
927 struct ichwd_softc *sc;
929 sc = device_get_softc(dev);
931 /* halt the watchdog timer */
933 ichwd_tmr_disable(sc);
935 /* enable the SMI handler */
936 if (sc->smi_enabled != 0)
937 ichwd_smi_enable(sc);
939 /* deregister event handler */
940 if (sc->ev_tag != NULL)
941 EVENTHANDLER_DEREGISTER(watchdog_list, sc->ev_tag);
944 /* reset the watchdog status registers */
947 /* deallocate I/O register space */
948 bus_release_resource(dev, SYS_RES_IOPORT, sc->tco_rid, sc->tco_res);
949 bus_release_resource(dev, SYS_RES_IOPORT, sc->smi_rid, sc->smi_res);
951 /* deallocate memory resource */
953 bus_release_resource(sc->ich, SYS_RES_MEMORY, sc->gcs_rid,
956 bus_release_resource(dev, SYS_RES_MEMORY, sc->gc_rid,
962 static device_method_t ichwd_methods[] = {
963 DEVMETHOD(device_identify, ichwd_identify),
964 DEVMETHOD(device_probe, ichwd_probe),
965 DEVMETHOD(device_attach, ichwd_attach),
966 DEVMETHOD(device_detach, ichwd_detach),
967 DEVMETHOD(device_shutdown, ichwd_detach),
971 static driver_t ichwd_driver = {
974 sizeof(struct ichwd_softc),
977 DRIVER_MODULE(ichwd, isa, ichwd_driver, ichwd_devclass, NULL, NULL);