2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2004 Texas A&M University
7 * Developer: Wm. Daryl Hawkins
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
39 unsigned int ich_version;
40 unsigned int tco_version;
54 struct resource *smi_res;
57 struct resource *tco_res;
60 struct resource *gcs_res;
63 struct resource *gc_res;
65 eventhandler_tag ev_tag;
68 #define VENDORID_INTEL 0x8086
69 #define DEVICEID_BAYTRAIL 0x0f1c
70 #define DEVICEID_CPT0 0x1c40
71 #define DEVICEID_CPT1 0x1c41
72 #define DEVICEID_CPT2 0x1c42
73 #define DEVICEID_CPT3 0x1c43
74 #define DEVICEID_CPT4 0x1c44
75 #define DEVICEID_CPT5 0x1c45
76 #define DEVICEID_CPT6 0x1c46
77 #define DEVICEID_CPT7 0x1c47
78 #define DEVICEID_CPT8 0x1c48
79 #define DEVICEID_CPT9 0x1c49
80 #define DEVICEID_CPT10 0x1c4a
81 #define DEVICEID_CPT11 0x1c4b
82 #define DEVICEID_CPT12 0x1c4c
83 #define DEVICEID_CPT13 0x1c4d
84 #define DEVICEID_CPT14 0x1c4e
85 #define DEVICEID_CPT15 0x1c4f
86 #define DEVICEID_CPT16 0x1c50
87 #define DEVICEID_CPT17 0x1c51
88 #define DEVICEID_CPT18 0x1c52
89 #define DEVICEID_CPT19 0x1c53
90 #define DEVICEID_CPT20 0x1c54
91 #define DEVICEID_CPT21 0x1c55
92 #define DEVICEID_CPT22 0x1c56
93 #define DEVICEID_CPT23 0x1c57
94 #define DEVICEID_CPT24 0x1c58
95 #define DEVICEID_CPT25 0x1c59
96 #define DEVICEID_CPT26 0x1c5a
97 #define DEVICEID_CPT27 0x1c5b
98 #define DEVICEID_CPT28 0x1c5c
99 #define DEVICEID_CPT29 0x1c5d
100 #define DEVICEID_CPT30 0x1c5e
101 #define DEVICEID_CPT31 0x1c5f
102 #define DEVICEID_PATSBURG_LPC1 0x1d40
103 #define DEVICEID_PATSBURG_LPC2 0x1d41
104 #define DEVICEID_PPT0 0x1e40
105 #define DEVICEID_PPT1 0x1e41
106 #define DEVICEID_PPT2 0x1e42
107 #define DEVICEID_PPT3 0x1e43
108 #define DEVICEID_PPT4 0x1e44
109 #define DEVICEID_PPT5 0x1e45
110 #define DEVICEID_PPT6 0x1e46
111 #define DEVICEID_PPT7 0x1e47
112 #define DEVICEID_PPT8 0x1e48
113 #define DEVICEID_PPT9 0x1e49
114 #define DEVICEID_PPT10 0x1e4a
115 #define DEVICEID_PPT11 0x1e4b
116 #define DEVICEID_PPT12 0x1e4c
117 #define DEVICEID_PPT13 0x1e4d
118 #define DEVICEID_PPT14 0x1e4e
119 #define DEVICEID_PPT15 0x1e4f
120 #define DEVICEID_PPT16 0x1e50
121 #define DEVICEID_PPT17 0x1e51
122 #define DEVICEID_PPT18 0x1e52
123 #define DEVICEID_PPT19 0x1e53
124 #define DEVICEID_PPT20 0x1e54
125 #define DEVICEID_PPT21 0x1e55
126 #define DEVICEID_PPT22 0x1e56
127 #define DEVICEID_PPT23 0x1e57
128 #define DEVICEID_PPT24 0x1e58
129 #define DEVICEID_PPT25 0x1e59
130 #define DEVICEID_PPT26 0x1e5a
131 #define DEVICEID_PPT27 0x1e5b
132 #define DEVICEID_PPT28 0x1e5c
133 #define DEVICEID_PPT29 0x1e5d
134 #define DEVICEID_PPT30 0x1e5e
135 #define DEVICEID_PPT31 0x1e5f
136 #define DEVICEID_AVN0 0x1f38
137 #define DEVICEID_AVN1 0x1f39
138 #define DEVICEID_AVN2 0x1f3a
139 #define DEVICEID_AVN3 0x1f3b
140 #define DEVICEID_BRASWELL 0x229c
141 #define DEVICEID_DH89XXCC_LPC 0x2310
142 #define DEVICEID_COLETOCRK_LPC 0x2390
143 #define DEVICEID_82801AA 0x2410
144 #define DEVICEID_82801AB 0x2420
145 #define DEVICEID_82801BA 0x2440
146 #define DEVICEID_82801BAM 0x244c
147 #define DEVICEID_82801CA 0x2480
148 #define DEVICEID_82801CAM 0x248c
149 #define DEVICEID_82801DB 0x24c0
150 #define DEVICEID_82801DBM 0x24cc
151 #define DEVICEID_82801E 0x2450
152 #define DEVICEID_82801EB 0x24dc
153 #define DEVICEID_82801EBR 0x24d0
154 #define DEVICEID_6300ESB 0x25a1
155 #define DEVICEID_82801FBR 0x2640
156 #define DEVICEID_ICH6M 0x2641
157 #define DEVICEID_ICH6W 0x2642
158 #define DEVICEID_63XXESB 0x2670
159 #define DEVICEID_ICH7 0x27b8
160 #define DEVICEID_ICH7DH 0x27b0
161 #define DEVICEID_ICH7M 0x27b9
162 #define DEVICEID_NM10 0x27bc
163 #define DEVICEID_ICH7MDH 0x27bd
164 #define DEVICEID_ICH8 0x2810
165 #define DEVICEID_ICH8DH 0x2812
166 #define DEVICEID_ICH8DO 0x2814
167 #define DEVICEID_ICH8M 0x2815
168 #define DEVICEID_ICH8ME 0x2811
169 #define DEVICEID_ICH9 0x2918
170 #define DEVICEID_ICH9DH 0x2912
171 #define DEVICEID_ICH9DO 0x2914
172 #define DEVICEID_ICH9M 0x2919
173 #define DEVICEID_ICH9ME 0x2917
174 #define DEVICEID_ICH9R 0x2916
175 #define DEVICEID_ICH10 0x3a18
176 #define DEVICEID_ICH10D 0x3a1a
177 #define DEVICEID_ICH10DO 0x3a14
178 #define DEVICEID_ICH10R 0x3a16
179 #define DEVICEID_PCH 0x3b00
180 #define DEVICEID_PCHM 0x3b01
181 #define DEVICEID_P55 0x3b02
182 #define DEVICEID_PM55 0x3b03
183 #define DEVICEID_H55 0x3b06
184 #define DEVICEID_QM57 0x3b07
185 #define DEVICEID_H57 0x3b08
186 #define DEVICEID_HM55 0x3b09
187 #define DEVICEID_Q57 0x3b0a
188 #define DEVICEID_HM57 0x3b0b
189 #define DEVICEID_PCHMSFF 0x3b0d
190 #define DEVICEID_QS57 0x3b0f
191 #define DEVICEID_3400 0x3b12
192 #define DEVICEID_3420 0x3b14
193 #define DEVICEID_3450 0x3b16
194 #define DEVICEID_LPT0 0x8c40
195 #define DEVICEID_LPT1 0x8c41
196 #define DEVICEID_LPT2 0x8c42
197 #define DEVICEID_LPT3 0x8c43
198 #define DEVICEID_LPT4 0x8c44
199 #define DEVICEID_LPT5 0x8c45
200 #define DEVICEID_LPT6 0x8c46
201 #define DEVICEID_LPT7 0x8c47
202 #define DEVICEID_LPT8 0x8c48
203 #define DEVICEID_LPT9 0x8c49
204 #define DEVICEID_LPT10 0x8c4a
205 #define DEVICEID_LPT11 0x8c4b
206 #define DEVICEID_LPT12 0x8c4c
207 #define DEVICEID_LPT13 0x8c4d
208 #define DEVICEID_LPT14 0x8c4e
209 #define DEVICEID_LPT15 0x8c4f
210 #define DEVICEID_LPT16 0x8c50
211 #define DEVICEID_LPT17 0x8c51
212 #define DEVICEID_LPT18 0x8c52
213 #define DEVICEID_LPT19 0x8c53
214 #define DEVICEID_LPT20 0x8c54
215 #define DEVICEID_LPT21 0x8c55
216 #define DEVICEID_LPT22 0x8c56
217 #define DEVICEID_LPT23 0x8c57
218 #define DEVICEID_LPT24 0x8c58
219 #define DEVICEID_LPT25 0x8c59
220 #define DEVICEID_LPT26 0x8c5a
221 #define DEVICEID_LPT27 0x8c5b
222 #define DEVICEID_LPT28 0x8c5c
223 #define DEVICEID_LPT29 0x8c5d
224 #define DEVICEID_LPT30 0x8c5e
225 #define DEVICEID_LPT31 0x8c5f
226 #define DEVICEID_WCPT1 0x8cc1
227 #define DEVICEID_WCPT2 0x8cc2
228 #define DEVICEID_WCPT3 0x8cc3
229 #define DEVICEID_WCPT4 0x8cc4
230 #define DEVICEID_WCPT6 0x8cc6
231 #define DEVICEID_WBG0 0x8d40
232 #define DEVICEID_WBG1 0x8d41
233 #define DEVICEID_WBG2 0x8d42
234 #define DEVICEID_WBG3 0x8d43
235 #define DEVICEID_WBG4 0x8d44
236 #define DEVICEID_WBG5 0x8d45
237 #define DEVICEID_WBG6 0x8d46
238 #define DEVICEID_WBG7 0x8d47
239 #define DEVICEID_WBG8 0x8d48
240 #define DEVICEID_WBG9 0x8d49
241 #define DEVICEID_WBG10 0x8d4a
242 #define DEVICEID_WBG11 0x8d4b
243 #define DEVICEID_WBG12 0x8d4c
244 #define DEVICEID_WBG13 0x8d4d
245 #define DEVICEID_WBG14 0x8d4e
246 #define DEVICEID_WBG15 0x8d4f
247 #define DEVICEID_WBG16 0x8d50
248 #define DEVICEID_WBG17 0x8d51
249 #define DEVICEID_WBG18 0x8d52
250 #define DEVICEID_WBG19 0x8d53
251 #define DEVICEID_WBG20 0x8d54
252 #define DEVICEID_WBG21 0x8d55
253 #define DEVICEID_WBG22 0x8d56
254 #define DEVICEID_WBG23 0x8d57
255 #define DEVICEID_WBG24 0x8d58
256 #define DEVICEID_WBG25 0x8d59
257 #define DEVICEID_WBG26 0x8d5a
258 #define DEVICEID_WBG27 0x8d5b
259 #define DEVICEID_WBG28 0x8d5c
260 #define DEVICEID_WBG29 0x8d5d
261 #define DEVICEID_WBG30 0x8d5e
262 #define DEVICEID_WBG31 0x8d5f
263 #define DEVICEID_LPT_LP0 0x9c40
264 #define DEVICEID_LPT_LP1 0x9c41
265 #define DEVICEID_LPT_LP2 0x9c42
266 #define DEVICEID_LPT_LP3 0x9c43
267 #define DEVICEID_LPT_LP4 0x9c44
268 #define DEVICEID_LPT_LP5 0x9c45
269 #define DEVICEID_LPT_LP6 0x9c46
270 #define DEVICEID_LPT_LP7 0x9c47
271 #define DEVICEID_WCPT_LP1 0x9cc1
272 #define DEVICEID_WCPT_LP2 0x9cc2
273 #define DEVICEID_WCPT_LP3 0x9cc3
274 #define DEVICEID_WCPT_LP5 0x9cc5
275 #define DEVICEID_WCPT_LP6 0x9cc6
276 #define DEVICEID_WCPT_LP7 0x9cc7
277 #define DEVICEID_WCPT_LP9 0x9cc9
278 #define DEVICEID_LEWISBURG_SMB 0xa1a3
279 #define DEVICEID_SRPTLP_SMB 0x9d23
281 /* ICH LPC Interface Bridge Registers (ICH5 and older) */
282 #define ICH_GEN_STA 0xd4
283 #define ICH_GEN_STA_NO_REBOOT 0x02
284 #define ICH_PMBASE 0x40 /* ACPI base address register */
285 #define ICH_PMBASE_MASK 0x7f80 /* bits 7-15 */
287 /* ICH Chipset Configuration Registers (ICH6 and newer) */
288 #define ICH_RCBA 0xf0
289 #define ICH_GCS_OFFSET 0x3410
290 #define ICH_GCS_SIZE 0x4
291 #define ICH_GCS_NO_REBOOT 0x20
293 /* SoC Power Management Configuration Registers */
294 #define ICH_PBASE 0x44
295 #define ICH_PMC_OFFSET 0x08
296 #define ICH_PMC_SIZE 0x4
297 #define ICH_PMC_NO_REBOOT 0x10
299 /* Lewisburg configration registers in SMBus controller. */
300 #define ICH_TCOBASE 0x50 /* TCO Base Addr */
301 #define ICH_TCOBASE_ADDRMASK 0xffe0
302 #define ICH_TCOBASE_SIZE 32
303 #define ICH_TCOCTL 0x54 /* TCO Control */
304 #define ICH_TCOCTL_TCO_BASE_EN 0x0100 /* TCO Base decoding enabled */
305 #define ICH_TCOCTL_TCO_BASE_LOCK 0x0001 /* TCOBASE is locked */
308 * Configuration registers in Sunrise Point and Lewisburg PCH Sideband Interface
309 * and Private Configuration Space.
311 #define SBREG_BAR 0x10
312 #define SMB_GC_REG 0xc
313 #define SMB_GC_SIZE 4
314 #define SMB_GC_NO_REBOOT 0x2
315 #define SMB_PORT_ID 0xc6
316 #define PCR_PORTID_SHIFT 16
317 #define PCR_REG_OFF(pid, reg) (((pid) << PCR_PORTID_SHIFT) | (reg))
319 /* register names and locations (relative to PMBASE) */
320 #define SMI_BASE 0x30 /* base address for SMI registers */
322 #define SMI_EN 0x00 /* SMI Control and Enable Register */
323 #define SMI_STS 0x04 /* SMI Status Register */
324 #define TCO_BASE 0x60 /* base address for TCO registers */
326 #define TCO_RLD 0x00 /* TCO Reload and Current Value */
327 #define TCO_TMR1 0x01 /* TCO Timer Initial Value
328 (ICH5 and older, 8 bits) */
329 #define TCO_TMR2 0x12 /* TCO Timer Initial Value
330 (ICH6 and newer, 16 bits) */
331 #define TCO_DAT_IN 0x02 /* TCO Data In (DO NOT USE) */
332 #define TCO_DAT_OUT 0x03 /* TCO Data Out (DO NOT USE) */
333 #define TCO1_STS 0x04 /* TCO Status 1 */
334 #define TCO2_STS 0x06 /* TCO Status 2 */
335 #define TCO1_CNT 0x08 /* TCO Control 1 */
336 #define TCO2_CNT 0x08 /* TCO Control 2 */
337 #define TCO_MESSAGE1 0x0c /* TCO Message 1 */
338 #define TCO_MESSAGE2 0x0d /* TCO Message 2 */
339 #define TCO_WDSTATUS 0x0e /* TCO Watchdog status */
340 #define TCO_TMR 0x12 /* TCP Reload value */
342 /* bit definitions for SMI_EN and SMI_STS */
343 #define SMI_TCO_EN 0x2000
344 #define SMI_TCO_STS 0x2000
345 #define SMI_GBL_EN 0x0001
347 /* timer value mask for TCO_RLD and TCO_TMR */
348 #define TCO_TIMER_MASK 0x1f
349 #define TCO_TIMER_MASK2 0x2f
351 /* status bits for TCO1_STS */
352 #define TCO_SLVSEL 0x2000 /* TCO Slave Select Soft Strap */
353 #define TCO_CPUSERR_STS 0x1000
354 #define TCO_CPUSMI_STS 0x0400
355 #define TCO_CPUSCI_STS 0x0200
356 #define TCO_BIOSWR_STS 0x0100
357 #define TCO_NEWCENTURY 0x0080 /* set for RTC year roll over
359 #define TCO_TIMEOUT 0x0008 /* timed out */
360 #define TCO_INT_STS 0x0004 /* data out (DO NOT USE) */
361 #define TCO_SMI_STS 0x0002 /* data in (DO NOT USE) */
362 #define TCO_NMI2SMI_STS 0x0001
364 /* status bits for TCO2_STS */
365 #define TCO_SMLINK_SLAVE_SMI 0x0010
366 #define TCO_BOOT_STS 0x0004 /* failed to come out of reset */
367 #define TCO_SECOND_TO_STS 0x0002 /* ran down twice */
368 #define TCO_INTRD_DET 0x0001
370 /* control bits for TCO1_CNT */
371 #define TCO_LOCK 0x1000 /* SMI_BASE.TCO_EN locked */
372 #define TCO_TMR_HALT 0x0800 /* clear to enable WDT */
373 #define TCO_NMI2SMI_EN 0x0200 /* convert NMIs to SMIs */
374 #define TCO_CNT_PRESERVE TCO_NMI2SMI_EN /* preserve these bits */
375 #define TCO_NMI_NOW 0x0100 /* trigger an NMI */
377 /* control bits for TCO2_CNT */
378 #define TCO_OS_POLICY 0x0030 /* mask */
379 #define TCO_OS_POLICY_BOOT 0x0000
380 #define TCO_OS_POLICY_SHUTD 0x0010
381 #define TCO_OS_POLICY_NOLOAD 0x0020
382 #define TCO_SMB_ALERT_DISABLE 0x0008
383 #define TCO_INTRD_SEL 0x0003 /* mask */
384 #define TCO_INTRD_SEL_SILENT 0x0000
385 #define TCO_INTRD_SEL_INTR 0x0001
386 #define TCO_INTRD_SEL_SMI 0x0002
389 * Masks for the TCO timer value field in TCO_RLD.
390 * If the datasheets are to be believed, the minimum value actually varies
391 * from chipset to chipset - 4 for ICH5 and 2 for all other chipsets.
392 * I suspect this is a bug in the ICH5 datasheet and that the minimum is
393 * uniformly 2, but I'd rather err on the side of caution.
395 #define TCO_RLD_TMR_MIN 0x0004
396 #define TCO_RLD1_TMR_MAX 0x003f
397 #define TCO_RLD2_TMR_MAX 0x03ff
400 * Approximate length in nanoseconds of one WDT tick (about 0.6 sec)
403 #define ICHWD_TICK 600000000
405 * Approximate length in nanoseconds of one WDT tick (about 1.0 sec)
408 #define ICHWD_TCO_V3_TICK 1000000000