sys/dev/if_wg/module/crypto/zinc/poly1305/poly1305-x86_64-glue.c

   1 // SPDX-License-Identifier: GPL-2.0 OR MIT
   2 /*
   3  * Copyright (C) 2015-2019 Jason A. Donenfeld <Jason@zx2c4.com>. All Rights Reserved.
   4  */
   5
   6 #ifdef __linux__
   7 #include <asm/cpufeature.h>
   8 #include <asm/processor.h>
   9 #include <asm/intel-family.h>
  10 #else
  11 #include <sys/simd-x86_64.h>
  12 #endif
  13
  14 asmlinkage void poly1305_init_x86_64(void *ctx,
  15                                      const u8 key[POLY1305_KEY_SIZE]);
  16 asmlinkage void poly1305_blocks_x86_64(void *ctx, const u8 *inp,
  17                                        const size_t len, const u32 padbit);
  18 asmlinkage void poly1305_emit_x86_64(void *ctx, u8 mac[POLY1305_MAC_SIZE],
  19                                      const u32 nonce[4]);
  20 asmlinkage void poly1305_emit_avx(void *ctx, u8 mac[POLY1305_MAC_SIZE],
  21                                   const u32 nonce[4]);
  22 asmlinkage void poly1305_blocks_avx(void *ctx, const u8 *inp, const size_t len,
  23                                     const u32 padbit);
  24 asmlinkage void poly1305_blocks_avx2(void *ctx, const u8 *inp, const size_t len,
  25                                      const u32 padbit);
  26 asmlinkage void poly1305_blocks_avx512(void *ctx, const u8 *inp,
  27                                        const size_t len, const u32 padbit);
  28
  29 static bool poly1305_use_avx __ro_after_init;
  30 static bool poly1305_use_avx2 __ro_after_init;
  31 static bool poly1305_use_avx512 __ro_after_init;
  32 static bool *const poly1305_nobs[] __initconst = {
  33         &poly1305_use_avx, &poly1305_use_avx2, &poly1305_use_avx512 };
  34
  35 static void __init poly1305_fpu_init(void)
  36 {
  37 #ifdef __linux__
  38         poly1305_use_avx =
  39                 boot_cpu_has(X86_FEATURE_AVX) &&
  40                 cpu_has_xfeatures(XFEATURE_MASK_SSE | XFEATURE_MASK_YMM, NULL);
  41         poly1305_use_avx2 =
  42                 boot_cpu_has(X86_FEATURE_AVX) &&
  43                 boot_cpu_has(X86_FEATURE_AVX2) &&
  44                 cpu_has_xfeatures(XFEATURE_MASK_SSE | XFEATURE_MASK_YMM, NULL);
  45 #ifndef COMPAT_CANNOT_USE_AVX512
  46         poly1305_use_avx512 =
  47                 boot_cpu_has(X86_FEATURE_AVX) &&
  48                 boot_cpu_has(X86_FEATURE_AVX2) &&
  49                 boot_cpu_has(X86_FEATURE_AVX512F) &&
  50                 cpu_has_xfeatures(XFEATURE_MASK_SSE | XFEATURE_MASK_YMM |
  51                                   XFEATURE_MASK_AVX512, NULL) &&
  52                 /* Skylake downclocks unacceptably much when using zmm. */
  53                 boot_cpu_data.x86_model != INTEL_FAM6_SKYLAKE_X;
  54 #endif
  55 #else
  56
  57         poly1305_use_avx = !!(cpu_feature2 & CPUID2_AVX) &&
  58                 __ymm_enabled();
  59         poly1305_use_avx2 = poly1305_use_avx &&
  60                 !!(cpu_stdext_feature & CPUID_STDEXT_AVX2);
  61         poly1305_use_avx512 = poly1305_use_avx2 &&
  62                 !!(cpu_stdext_feature & CPUID_STDEXT_AVX512F)  &&
  63                 __zmm_enabled();
  64 #endif
  65 }
  66
  67 static inline bool poly1305_init_arch(void *ctx,
  68                                       const u8 key[POLY1305_KEY_SIZE])
  69 {
  70         poly1305_init_x86_64(ctx, key);
  71         return true;
  72 }
  73
  74 struct poly1305_arch_internal {
  75         union {
  76                 struct {
  77                         u32 h[5];
  78                         u32 is_base2_26;
  79                 };
  80                 u64 hs[3];
  81         };
  82         u64 r[2];
  83         u64 pad;
  84         struct { u32 r2, r1, r4, r3; } rn[9];
  85 };
  86
  87 /* The AVX code uses base 2^26, while the scalar code uses base 2^64. If we hit
  88  * the unfortunate situation of using AVX and then having to go back to scalar
  89  * -- because the user is silly and has called the update function from two
  90  * separate contexts -- then we need to convert back to the original base before
  91  * proceeding. It is possible to reason that the initial reduction below is
  92  * sufficient given the implementation invariants. However, for an avoidance of
  93  * doubt and because this is not performance critical, we do the full reduction
  94  * anyway.
  95  */
  96 static void convert_to_base2_64(void *ctx)
  97 {
  98         struct poly1305_arch_internal *state = ctx;
  99         u32 cy;
 100
 101         if (!state->is_base2_26)
 102                 return;
 103
 104         cy = state->h[0] >> 26; state->h[0] &= 0x3ffffff; state->h[1] += cy;
 105         cy = state->h[1] >> 26; state->h[1] &= 0x3ffffff; state->h[2] += cy;
 106         cy = state->h[2] >> 26; state->h[2] &= 0x3ffffff; state->h[3] += cy;
 107         cy = state->h[3] >> 26; state->h[3] &= 0x3ffffff; state->h[4] += cy;
 108         state->hs[0] = ((u64)state->h[2] << 52) | ((u64)state->h[1] << 26) | state->h[0];
 109         state->hs[1] = ((u64)state->h[4] << 40) | ((u64)state->h[3] << 14) | (state->h[2] >> 12);
 110         state->hs[2] = state->h[4] >> 24;
 111 #define ULT(a, b) ((a ^ ((a ^ b) | ((a - b) ^ b))) >> (sizeof(a) * 8 - 1))
 112         cy = (state->hs[2] >> 2) + (state->hs[2] & ~3ULL);
 113         state->hs[2] &= 3;
 114         state->hs[0] += cy;
 115         state->hs[1] += (cy = ULT(state->hs[0], cy));
 116         state->hs[2] += ULT(state->hs[1], cy);
 117 #undef ULT
 118         state->is_base2_26 = 0;
 119 }
 120
 121 static inline bool poly1305_blocks_arch(void *ctx, const u8 *inp,
 122                                         size_t len, const u32 padbit,
 123                                         simd_context_t *simd_context)
 124 {
 125         struct poly1305_arch_internal *state = ctx;
 126
 127         /* SIMD disables preemption, so relax after processing each page. */
 128         BUILD_BUG_ON(PAGE_SIZE < POLY1305_BLOCK_SIZE ||
 129                      PAGE_SIZE % POLY1305_BLOCK_SIZE);
 130
 131         if (!poly1305_use_avx ||
 132             (len < (POLY1305_BLOCK_SIZE * 18) && !state->is_base2_26) ||
 133             !simd_use(simd_context)) {
 134                 convert_to_base2_64(ctx);
 135                 poly1305_blocks_x86_64(ctx, inp, len, padbit);
 136                 return true;
 137         }
 138
 139         for (;;) {
 140                 const size_t bytes = min_t(size_t, len, PAGE_SIZE);
 141
 142                 if (poly1305_use_avx512)
 143                         poly1305_blocks_avx512(ctx, inp, bytes, padbit);
 144                 else if (poly1305_use_avx2)
 145                         poly1305_blocks_avx2(ctx, inp, bytes, padbit);
 146                 else
 147                         poly1305_blocks_avx(ctx, inp, bytes, padbit);
 148                 len -= bytes;
 149                 if (!len)
 150                         break;
 151                 inp += bytes;
 152                 simd_relax(simd_context);
 153         }
 154
 155         return true;
 156 }
 157
 158 static inline bool poly1305_emit_arch(void *ctx, u8 mac[POLY1305_MAC_SIZE],
 159                                       const u32 nonce[4],
 160                                       simd_context_t *simd_context)
 161 {
 162         struct poly1305_arch_internal *state = ctx;
 163
 164         if (!IS_ENABLED(CONFIG_AS_AVX) || !poly1305_use_avx ||
 165             !state->is_base2_26 || !simd_use(simd_context)) {
 166                 convert_to_base2_64(ctx);
 167                 poly1305_emit_x86_64(ctx, mac, nonce);
 168         } else
 169                 poly1305_emit_avx(ctx, mac, nonce);
 170         return true;
 171 }