2 * Copyright 2021 Intel Corp
3 * Copyright 2021 Rubicon Communications, LLC (Netgate)
4 * SPDX-License-Identifier: BSD-3-Clause
12 /* forward declaration */
13 s32 igc_init_hw_base(struct igc_hw *hw);
14 void igc_power_down_phy_copper_base(struct igc_hw *hw);
15 extern void igc_rx_fifo_flush_base(struct igc_hw *hw);
16 s32 igc_acquire_phy_base(struct igc_hw *hw);
17 void igc_release_phy_base(struct igc_hw *hw);
19 /* Transmit Descriptor - Advanced */
20 union igc_adv_tx_desc {
22 __le64 buffer_addr; /* Address of descriptor's data buf */
27 __le64 rsvd; /* Reserved */
33 /* Context descriptors */
34 struct igc_adv_tx_context_desc {
35 __le32 vlan_macip_lens;
40 __le32 type_tucmd_mlhl;
44 /* Adv Transmit Descriptor Config Masks */
45 #define IGC_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */
46 #define IGC_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */
47 #define IGC_ADVTXD_DCMD_EOP 0x01000000 /* End of Packet */
48 #define IGC_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
49 #define IGC_ADVTXD_DCMD_RS 0x08000000 /* Report Status */
50 #define IGC_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */
51 #define IGC_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */
52 #define IGC_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */
53 #define IGC_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
54 #define IGC_ADVTXD_MAC_LINKSEC 0x00040000 /* Apply LinkSec on pkt */
55 #define IGC_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE1588 Timestamp pkt */
56 #define IGC_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED prsnt in WB */
57 #define IGC_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */
58 #define IGC_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */
59 #define IGC_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */
60 #define IGC_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */
61 /* 1st & Last TSO-full iSCSI PDU*/
62 #define IGC_ADVTXD_POPTS_ISCO_FULL 0x00001800
63 #define IGC_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */
64 #define IGC_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
66 /* Advanced Transmit Context Descriptor Config */
67 #define IGC_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
68 #define IGC_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */
69 #define IGC_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */
70 #define IGC_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */
71 #define IGC_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */
72 #define IGC_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
73 #define IGC_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */
74 #define IGC_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */
75 /* IPSec Encrypt Enable for ESP */
76 #define IGC_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000
77 /* Req requires Markers and CRC */
78 #define IGC_ADVTXD_TUCMD_MKRREQ 0x00002000
79 #define IGC_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
80 #define IGC_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
81 /* Adv ctxt IPSec SA IDX mask */
82 #define IGC_ADVTXD_IPSEC_SA_INDEX_MASK 0x000000FF
83 /* Adv ctxt IPSec ESP len mask */
84 #define IGC_ADVTXD_IPSEC_ESP_LEN_MASK 0x000000FF
86 #define IGC_RAR_ENTRIES_BASE 16
88 /* Receive Descriptor - Advanced */
89 union igc_adv_rx_desc {
91 __le64 pkt_addr; /* Packet buffer address */
92 __le64 hdr_addr; /* Header buffer address */
99 __le16 pkt_info; /*RSS type, Pkt type*/
100 /* Split Header, header buffer len */
105 __le32 rss; /* RSS Hash */
107 __le16 ip_id; /* IP id */
108 __le16 csum; /* Packet Checksum */
113 __le32 status_error; /* ext status/error */
114 __le16 length; /* Packet length */
115 __le16 vlan; /* VLAN tag */
117 } wb; /* writeback */
120 /* Additional Transmit Descriptor Control definitions */
121 #define IGC_TXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Tx Queue */
123 /* Additional Receive Descriptor Control definitions */
124 #define IGC_RXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Rx Queue */
126 /* SRRCTL bit definitions */
127 #define IGC_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */
128 #define IGC_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */
129 #define IGC_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
131 #endif /* _IGC_BASE_H_ */