2 * Copyright 2021 Intel Corp
3 * Copyright 2021 Rubicon Communications, LLC (Netgate)
4 * SPDX-License-Identifier: BSD-3-Clause
12 #include "igc_osdep.h"
14 #include "igc_defines.h"
18 #define IGC_DEV_ID_I225_LM 0x15F2
19 #define IGC_DEV_ID_I225_V 0x15F3
20 #define IGC_DEV_ID_I225_K 0x3100
21 #define IGC_DEV_ID_I225_I 0x15F8
22 #define IGC_DEV_ID_I220_V 0x15F7
23 #define IGC_DEV_ID_I225_K2 0x3101
24 #define IGC_DEV_ID_I225_LMVP 0x5502
25 #define IGC_DEV_ID_I226_K 0x5504
26 #define IGC_DEV_ID_I225_IT 0x0D9F
27 #define IGC_DEV_ID_I226_LM 0x125B
28 #define IGC_DEV_ID_I226_V 0x125C
29 #define IGC_DEV_ID_I226_IT 0x125D
30 #define IGC_DEV_ID_I221_V 0x125E
31 #define IGC_DEV_ID_I226_BLANK_NVM 0x125F
32 #define IGC_DEV_ID_I225_BLANK_NVM 0x15FD
34 #define IGC_REVISION_0 0
35 #define IGC_REVISION_1 1
36 #define IGC_REVISION_2 2
37 #define IGC_REVISION_3 3
38 #define IGC_REVISION_4 4
42 #define IGC_ALT_MAC_ADDRESS_OFFSET_LAN0 0
43 #define IGC_ALT_MAC_ADDRESS_OFFSET_LAN1 3
48 igc_num_macs /* List is 1-based, so subtract 1 for TRUE count. */
52 igc_media_type_unknown = 0,
53 igc_media_type_copper = 1,
71 igc_bus_type_unknown = 0,
74 igc_bus_type_pci_express,
79 igc_bus_speed_unknown = 0,
87 igc_bus_speed_reserved
91 igc_bus_width_unknown = 0,
92 igc_bus_width_pcie_x1,
93 igc_bus_width_pcie_x2,
94 igc_bus_width_pcie_x4 = 4,
95 igc_bus_width_pcie_x8 = 8,
98 igc_bus_width_reserved
106 igc_fc_default = 0xFF
110 igc_ms_hw_default = 0,
116 enum igc_smart_speed {
117 igc_smart_speed_default = 0,
125 /* Receive Descriptor */
127 __le64 buffer_addr; /* Address of the descriptor's data buffer */
128 __le16 length; /* Length of data DMAed into data buffer */
129 __le16 csum; /* Packet checksum */
130 u8 status; /* Descriptor status */
131 u8 errors; /* Descriptor Errors */
135 /* Receive Descriptor - Extended */
136 union igc_rx_desc_extended {
143 __le32 mrq; /* Multiple Rx Queues */
145 __le32 rss; /* RSS Hash */
147 __le16 ip_id; /* IP id */
148 __le16 csum; /* Packet Checksum */
153 __le32 status_error; /* ext status/error */
155 __le16 vlan; /* VLAN tag */
157 } wb; /* writeback */
160 #define MAX_PS_BUFFERS 4
162 /* Number of packet split data buffers (not including the header buffer) */
163 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
165 /* Receive Descriptor - Packet Split */
166 union igc_rx_desc_packet_split {
168 /* one buffer for protocol header(s), three data buffers */
169 __le64 buffer_addr[MAX_PS_BUFFERS];
173 __le32 mrq; /* Multiple Rx Queues */
175 __le32 rss; /* RSS Hash */
177 __le16 ip_id; /* IP id */
178 __le16 csum; /* Packet Checksum */
183 __le32 status_error; /* ext status/error */
184 __le16 length0; /* length of buffer 0 */
185 __le16 vlan; /* VLAN tag */
188 __le16 header_status;
189 /* length of buffers 1-3 */
190 __le16 length[PS_PAGE_BUFFERS];
193 } wb; /* writeback */
196 /* Transmit Descriptor */
198 __le64 buffer_addr; /* Address of the descriptor's data buffer */
202 __le16 length; /* Data buffer length */
203 u8 cso; /* Checksum offset */
204 u8 cmd; /* Descriptor control */
210 u8 status; /* Descriptor status */
211 u8 css; /* Checksum start */
217 /* Offload Context Descriptor */
218 struct igc_context_desc {
222 u8 ipcss; /* IP checksum start */
223 u8 ipcso; /* IP checksum offset */
224 __le16 ipcse; /* IP checksum end */
230 u8 tucss; /* TCP checksum start */
231 u8 tucso; /* TCP checksum offset */
232 __le16 tucse; /* TCP checksum end */
235 __le32 cmd_and_length;
239 u8 status; /* Descriptor status */
240 u8 hdr_len; /* Header length */
241 __le16 mss; /* Maximum segment size */
246 /* Offload data descriptor */
247 struct igc_data_desc {
248 __le64 buffer_addr; /* Address of the descriptor's buffer address */
252 __le16 length; /* Data buffer length */
260 u8 status; /* Descriptor status */
261 u8 popts; /* Packet Options */
267 /* Statistics counters collected by the MAC */
268 struct igc_hw_stats {
344 /* Function pointers for the MAC. */
345 struct igc_mac_operations {
346 s32 (*init_params)(struct igc_hw *);
347 s32 (*check_for_link)(struct igc_hw *);
348 void (*clear_hw_cntrs)(struct igc_hw *);
349 void (*clear_vfta)(struct igc_hw *);
350 s32 (*get_bus_info)(struct igc_hw *);
351 void (*set_lan_id)(struct igc_hw *);
352 s32 (*get_link_up_info)(struct igc_hw *, u16 *, u16 *);
353 void (*update_mc_addr_list)(struct igc_hw *, u8 *, u32);
354 s32 (*reset_hw)(struct igc_hw *);
355 s32 (*init_hw)(struct igc_hw *);
356 s32 (*setup_link)(struct igc_hw *);
357 s32 (*setup_physical_interface)(struct igc_hw *);
358 void (*write_vfta)(struct igc_hw *, u32, u32);
359 void (*config_collision_dist)(struct igc_hw *);
360 int (*rar_set)(struct igc_hw *, u8*, u32);
361 s32 (*read_mac_addr)(struct igc_hw *);
362 s32 (*validate_mdi_setting)(struct igc_hw *);
363 s32 (*acquire_swfw_sync)(struct igc_hw *, u16);
364 void (*release_swfw_sync)(struct igc_hw *, u16);
367 /* When to use various PHY register access functions:
370 * Function Does Does When to use
371 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
372 * X_reg L,P,A n/a for simple PHY reg accesses
373 * X_reg_locked P,A L for multiple accesses of different regs
375 * X_reg_page A L,P for multiple accesses of different regs
378 * Where X=[read|write], L=locking, P=sets page, A=register access
381 struct igc_phy_operations {
382 s32 (*init_params)(struct igc_hw *);
383 s32 (*acquire)(struct igc_hw *);
384 s32 (*check_reset_block)(struct igc_hw *);
385 s32 (*commit)(struct igc_hw *);
386 s32 (*force_speed_duplex)(struct igc_hw *);
387 s32 (*get_info)(struct igc_hw *);
388 s32 (*set_page)(struct igc_hw *, u16);
389 s32 (*read_reg)(struct igc_hw *, u32, u16 *);
390 s32 (*read_reg_locked)(struct igc_hw *, u32, u16 *);
391 s32 (*read_reg_page)(struct igc_hw *, u32, u16 *);
392 void (*release)(struct igc_hw *);
393 s32 (*reset)(struct igc_hw *);
394 s32 (*set_d0_lplu_state)(struct igc_hw *, bool);
395 s32 (*set_d3_lplu_state)(struct igc_hw *, bool);
396 s32 (*write_reg)(struct igc_hw *, u32, u16);
397 s32 (*write_reg_locked)(struct igc_hw *, u32, u16);
398 s32 (*write_reg_page)(struct igc_hw *, u32, u16);
399 void (*power_up)(struct igc_hw *);
400 void (*power_down)(struct igc_hw *);
403 /* Function pointers for the NVM. */
404 struct igc_nvm_operations {
405 s32 (*init_params)(struct igc_hw *);
406 s32 (*acquire)(struct igc_hw *);
407 s32 (*read)(struct igc_hw *, u16, u16, u16 *);
408 void (*release)(struct igc_hw *);
409 void (*reload)(struct igc_hw *);
410 s32 (*update)(struct igc_hw *);
411 s32 (*validate)(struct igc_hw *);
412 s32 (*write)(struct igc_hw *, u16, u16, u16 *);
416 s32 (*get_invariants)(struct igc_hw *hw);
417 struct igc_mac_operations *mac_ops;
418 const struct igc_phy_operations *phy_ops;
419 struct igc_nvm_operations *nvm_ops;
422 extern const struct igc_info igc_i225_info;
424 struct igc_mac_info {
425 struct igc_mac_operations ops;
426 u8 addr[ETH_ADDR_LEN];
427 u8 perm_addr[ETH_ADDR_LEN];
429 enum igc_mac_type type;
441 /* Maximum size of the MTA register table in all supported adapters */
442 #define MAX_MTA_REG 128
443 u32 mta_shadow[MAX_MTA_REG];
446 u8 forced_speed_duplex;
448 bool asf_firmware_present;
450 bool get_link_status;
454 struct igc_phy_info {
455 struct igc_phy_operations ops;
456 enum igc_phy_type type;
458 enum igc_smart_speed smart_speed;
462 u32 reset_delay_us; /* in usec */
465 enum igc_media_type media_type;
467 u16 autoneg_advertised;
472 bool polarity_correction;
473 bool speed_downgraded;
474 bool autoneg_wait_to_complete;
477 struct igc_nvm_info {
478 struct igc_nvm_operations ops;
479 enum igc_nvm_type type;
488 struct igc_bus_info {
489 enum igc_bus_type type;
490 enum igc_bus_speed speed;
491 enum igc_bus_width width;
498 u32 high_water; /* Flow control high-water mark */
499 u32 low_water; /* Flow control low-water mark */
500 u16 pause_time; /* Flow control pause timer */
501 u16 refresh_time; /* Flow control refresh timer */
502 bool send_xon; /* Flow control send XON */
503 bool strict_ieee; /* Strict IEEE mode */
504 enum igc_fc_mode current_mode; /* FC mode in effect */
505 enum igc_fc_mode requested_mode; /* FC mode requested by caller */
508 struct igc_dev_spec_i225 {
510 bool clear_semaphore_once;
519 unsigned long io_base;
521 struct igc_mac_info mac;
522 struct igc_fc_info fc;
523 struct igc_phy_info phy;
524 struct igc_nvm_info nvm;
525 struct igc_bus_info bus;
528 struct igc_dev_spec_i225 _i225;
532 u16 subsystem_vendor_id;
533 u16 subsystem_device_id;
539 #include "igc_i225.h"
540 #include "igc_base.h"
542 /* These functions must be implemented by drivers */
543 s32 igc_read_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value);
544 s32 igc_write_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value);
545 void igc_read_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value);
546 void igc_write_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value);