2 * Copyright 2021 Intel Corp
3 * Copyright 2021 Rubicon Communications, LLC (Netgate)
4 * SPDX-License-Identifier: BSD-3-Clause
12 static s32 igc_init_nvm_params_i225(struct igc_hw *hw);
13 static s32 igc_init_mac_params_i225(struct igc_hw *hw);
14 static s32 igc_init_phy_params_i225(struct igc_hw *hw);
15 static s32 igc_reset_hw_i225(struct igc_hw *hw);
16 static s32 igc_acquire_nvm_i225(struct igc_hw *hw);
17 static void igc_release_nvm_i225(struct igc_hw *hw);
18 static s32 igc_get_hw_semaphore_i225(struct igc_hw *hw);
19 static s32 __igc_write_nvm_srwr(struct igc_hw *hw, u16 offset, u16 words,
21 static s32 igc_pool_flash_update_done_i225(struct igc_hw *hw);
24 * igc_init_nvm_params_i225 - Init NVM func ptrs.
25 * @hw: pointer to the HW structure
27 static s32 igc_init_nvm_params_i225(struct igc_hw *hw)
29 struct igc_nvm_info *nvm = &hw->nvm;
30 u32 eecd = IGC_READ_REG(hw, IGC_EECD);
33 DEBUGFUNC("igc_init_nvm_params_i225");
35 size = (u16)((eecd & IGC_EECD_SIZE_EX_MASK) >>
36 IGC_EECD_SIZE_EX_SHIFT);
38 * Added to a constant, "size" becomes the left-shift value
39 * for setting word_size.
41 size += NVM_WORD_SIZE_BASE_SHIFT;
43 /* Just in case size is out of range, cap it to the largest
44 * EEPROM size supported
49 nvm->word_size = 1 << size;
52 nvm->type = igc_nvm_eeprom_spi;
55 nvm->page_size = eecd & IGC_EECD_ADDR_BITS ? 32 : 8;
56 nvm->address_bits = eecd & IGC_EECD_ADDR_BITS ?
59 if (nvm->word_size == (1 << 15))
62 nvm->ops.acquire = igc_acquire_nvm_i225;
63 nvm->ops.release = igc_release_nvm_i225;
64 if (igc_get_flash_presence_i225(hw)) {
65 hw->nvm.type = igc_nvm_flash_hw;
66 nvm->ops.read = igc_read_nvm_srrd_i225;
67 nvm->ops.write = igc_write_nvm_srwr_i225;
68 nvm->ops.validate = igc_validate_nvm_checksum_i225;
69 nvm->ops.update = igc_update_nvm_checksum_i225;
71 hw->nvm.type = igc_nvm_invm;
72 nvm->ops.write = igc_null_write_nvm;
73 nvm->ops.validate = igc_null_ops_generic;
74 nvm->ops.update = igc_null_ops_generic;
81 * igc_init_mac_params_i225 - Init MAC func ptrs.
82 * @hw: pointer to the HW structure
84 static s32 igc_init_mac_params_i225(struct igc_hw *hw)
86 struct igc_mac_info *mac = &hw->mac;
87 struct igc_dev_spec_i225 *dev_spec = &hw->dev_spec._i225;
89 DEBUGFUNC("igc_init_mac_params_i225");
91 /* Initialize function pointer */
92 igc_init_mac_ops_generic(hw);
95 hw->phy.media_type = igc_media_type_copper;
96 /* Set mta register count */
97 mac->mta_reg_count = 128;
98 /* Set rar entry count */
99 mac->rar_entry_count = IGC_RAR_ENTRIES_BASE;
102 mac->ops.reset_hw = igc_reset_hw_i225;
103 /* hw initialization */
104 mac->ops.init_hw = igc_init_hw_i225;
106 mac->ops.setup_link = igc_setup_link_generic;
108 mac->ops.check_for_link = igc_check_for_link_i225;
110 mac->ops.get_link_up_info = igc_get_speed_and_duplex_copper_generic;
111 /* acquire SW_FW sync */
112 mac->ops.acquire_swfw_sync = igc_acquire_swfw_sync_i225;
113 /* release SW_FW sync */
114 mac->ops.release_swfw_sync = igc_release_swfw_sync_i225;
116 /* Allow a single clear of the SW semaphore on I225 */
117 dev_spec->clear_semaphore_once = true;
118 mac->ops.setup_physical_interface = igc_setup_copper_link_i225;
120 /* Set if part includes ASF firmware */
121 mac->asf_firmware_present = true;
123 /* multicast address update */
124 mac->ops.update_mc_addr_list = igc_update_mc_addr_list_generic;
126 mac->ops.write_vfta = igc_write_vfta_generic;
132 * igc_init_phy_params_i225 - Init PHY func ptrs.
133 * @hw: pointer to the HW structure
135 static s32 igc_init_phy_params_i225(struct igc_hw *hw)
137 struct igc_phy_info *phy = &hw->phy;
138 s32 ret_val = IGC_SUCCESS;
141 DEBUGFUNC("igc_init_phy_params_i225");
144 if (hw->phy.media_type != igc_media_type_copper) {
145 phy->type = igc_phy_none;
149 phy->ops.power_up = igc_power_up_phy_copper;
150 phy->ops.power_down = igc_power_down_phy_copper_base;
152 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT_2500;
154 phy->reset_delay_us = 100;
156 phy->ops.acquire = igc_acquire_phy_base;
157 phy->ops.check_reset_block = igc_check_reset_block_generic;
158 phy->ops.commit = igc_phy_sw_reset_generic;
159 phy->ops.release = igc_release_phy_base;
161 ctrl_ext = IGC_READ_REG(hw, IGC_CTRL_EXT);
163 /* Make sure the PHY is in a good state. Several people have reported
164 * firmware leaving the PHY's page select register set to something
165 * other than the default of zero, which causes the PHY ID read to
166 * access something other than the intended register.
168 ret_val = hw->phy.ops.reset(hw);
172 IGC_WRITE_REG(hw, IGC_CTRL_EXT, ctrl_ext);
173 phy->ops.read_reg = igc_read_phy_reg_gpy;
174 phy->ops.write_reg = igc_write_phy_reg_gpy;
176 ret_val = igc_get_phy_id(hw);
177 /* Verify phy id and set remaining function pointers */
180 phy->type = igc_phy_i225;
181 phy->ops.set_d0_lplu_state = igc_set_d0_lplu_state_i225;
182 phy->ops.set_d3_lplu_state = igc_set_d3_lplu_state_i225;
183 /* TODO - complete with GPY PHY information */
186 ret_val = -IGC_ERR_PHY;
195 * igc_reset_hw_i225 - Reset hardware
196 * @hw: pointer to the HW structure
198 * This resets the hardware into a known state.
200 static s32 igc_reset_hw_i225(struct igc_hw *hw)
205 DEBUGFUNC("igc_reset_hw_i225");
208 * Prevent the PCI-E bus from sticking if there is no TLP connection
209 * on the last TLP read/write transaction when MAC is reset.
211 ret_val = igc_disable_pcie_master_generic(hw);
213 DEBUGOUT("PCI-E Master disable polling has failed.\n");
215 DEBUGOUT("Masking off all interrupts\n");
216 IGC_WRITE_REG(hw, IGC_IMC, 0xffffffff);
218 IGC_WRITE_REG(hw, IGC_RCTL, 0);
219 IGC_WRITE_REG(hw, IGC_TCTL, IGC_TCTL_PSP);
224 ctrl = IGC_READ_REG(hw, IGC_CTRL);
226 DEBUGOUT("Issuing a global reset to MAC\n");
227 IGC_WRITE_REG(hw, IGC_CTRL, ctrl | IGC_CTRL_DEV_RST);
229 ret_val = igc_get_auto_rd_done_generic(hw);
232 * When auto config read does not complete, do not
233 * return with an error. This can happen in situations
234 * where there is no eeprom and prevents getting link.
236 DEBUGOUT("Auto Read Done did not complete\n");
239 /* Clear any pending interrupt events. */
240 IGC_WRITE_REG(hw, IGC_IMC, 0xffffffff);
241 IGC_READ_REG(hw, IGC_ICR);
243 /* Install any alternate MAC address into RAR0 */
244 ret_val = igc_check_alt_mac_addr_generic(hw);
249 /* igc_acquire_nvm_i225 - Request for access to EEPROM
250 * @hw: pointer to the HW structure
252 * Acquire the necessary semaphores for exclusive access to the EEPROM.
253 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
254 * Return successful if access grant bit set, else clear the request for
255 * EEPROM access and return -IGC_ERR_NVM (-1).
257 static s32 igc_acquire_nvm_i225(struct igc_hw *hw)
261 DEBUGFUNC("igc_acquire_nvm_i225");
263 ret_val = igc_acquire_swfw_sync_i225(hw, IGC_SWFW_EEP_SM);
268 /* igc_release_nvm_i225 - Release exclusive access to EEPROM
269 * @hw: pointer to the HW structure
271 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
272 * then release the semaphores acquired.
274 static void igc_release_nvm_i225(struct igc_hw *hw)
276 DEBUGFUNC("igc_release_nvm_i225");
278 igc_release_swfw_sync_i225(hw, IGC_SWFW_EEP_SM);
281 /* igc_acquire_swfw_sync_i225 - Acquire SW/FW semaphore
282 * @hw: pointer to the HW structure
283 * @mask: specifies which semaphore to acquire
285 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
286 * will also specify which port we're acquiring the lock for.
288 s32 igc_acquire_swfw_sync_i225(struct igc_hw *hw, u16 mask)
292 u32 fwmask = mask << 16;
293 s32 ret_val = IGC_SUCCESS;
294 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
296 DEBUGFUNC("igc_acquire_swfw_sync_i225");
298 while (i < timeout) {
299 if (igc_get_hw_semaphore_i225(hw)) {
300 ret_val = -IGC_ERR_SWFW_SYNC;
304 swfw_sync = IGC_READ_REG(hw, IGC_SW_FW_SYNC);
305 if (!(swfw_sync & (fwmask | swmask)))
308 /* Firmware currently using resource (fwmask)
309 * or other software thread using resource (swmask)
311 igc_put_hw_semaphore_generic(hw);
317 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
318 ret_val = -IGC_ERR_SWFW_SYNC;
323 IGC_WRITE_REG(hw, IGC_SW_FW_SYNC, swfw_sync);
325 igc_put_hw_semaphore_generic(hw);
331 /* igc_release_swfw_sync_i225 - Release SW/FW semaphore
332 * @hw: pointer to the HW structure
333 * @mask: specifies which semaphore to acquire
335 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
336 * will also specify which port we're releasing the lock for.
338 void igc_release_swfw_sync_i225(struct igc_hw *hw, u16 mask)
342 DEBUGFUNC("igc_release_swfw_sync_i225");
344 while (igc_get_hw_semaphore_i225(hw) != IGC_SUCCESS)
347 swfw_sync = IGC_READ_REG(hw, IGC_SW_FW_SYNC);
349 IGC_WRITE_REG(hw, IGC_SW_FW_SYNC, swfw_sync);
351 igc_put_hw_semaphore_generic(hw);
355 * igc_setup_copper_link_i225 - Configure copper link settings
356 * @hw: pointer to the HW structure
358 * Configures the link for auto-neg or forced speed and duplex. Then we check
359 * for link, once link is established calls to configure collision distance
360 * and flow control are called.
362 s32 igc_setup_copper_link_i225(struct igc_hw *hw)
368 DEBUGFUNC("igc_setup_copper_link_i225");
370 ctrl = IGC_READ_REG(hw, IGC_CTRL);
371 ctrl |= IGC_CTRL_SLU;
372 ctrl &= ~(IGC_CTRL_FRCSPD | IGC_CTRL_FRCDPX);
373 IGC_WRITE_REG(hw, IGC_CTRL, ctrl);
375 phpm_reg = IGC_READ_REG(hw, IGC_I225_PHPM);
376 phpm_reg &= ~IGC_I225_PHPM_GO_LINKD;
377 IGC_WRITE_REG(hw, IGC_I225_PHPM, phpm_reg);
379 ret_val = igc_setup_copper_link_generic(hw);
384 /* igc_get_hw_semaphore_i225 - Acquire hardware semaphore
385 * @hw: pointer to the HW structure
387 * Acquire the HW semaphore to access the PHY or NVM
389 static s32 igc_get_hw_semaphore_i225(struct igc_hw *hw)
392 s32 timeout = hw->nvm.word_size + 1;
395 DEBUGFUNC("igc_get_hw_semaphore_i225");
397 /* Get the SW semaphore */
398 while (i < timeout) {
399 swsm = IGC_READ_REG(hw, IGC_SWSM);
400 if (!(swsm & IGC_SWSM_SMBI))
408 /* In rare circumstances, the SW semaphore may already be held
409 * unintentionally. Clear the semaphore once before giving up.
411 if (hw->dev_spec._i225.clear_semaphore_once) {
412 hw->dev_spec._i225.clear_semaphore_once = false;
413 igc_put_hw_semaphore_generic(hw);
414 for (i = 0; i < timeout; i++) {
415 swsm = IGC_READ_REG(hw, IGC_SWSM);
416 if (!(swsm & IGC_SWSM_SMBI))
423 /* If we do not have the semaphore here, we have to give up. */
425 DEBUGOUT("Driver can't access device -\n");
426 DEBUGOUT("SMBI bit is set.\n");
431 /* Get the FW semaphore. */
432 for (i = 0; i < timeout; i++) {
433 swsm = IGC_READ_REG(hw, IGC_SWSM);
434 IGC_WRITE_REG(hw, IGC_SWSM, swsm | IGC_SWSM_SWESMBI);
436 /* Semaphore acquired if bit latched */
437 if (IGC_READ_REG(hw, IGC_SWSM) & IGC_SWSM_SWESMBI)
444 /* Release semaphores */
445 igc_put_hw_semaphore_generic(hw);
446 DEBUGOUT("Driver can't access the NVM\n");
453 /* igc_read_nvm_srrd_i225 - Reads Shadow Ram using EERD register
454 * @hw: pointer to the HW structure
455 * @offset: offset of word in the Shadow Ram to read
456 * @words: number of words to read
457 * @data: word read from the Shadow Ram
459 * Reads a 16 bit word from the Shadow Ram using the EERD register.
460 * Uses necessary synchronization semaphores.
462 s32 igc_read_nvm_srrd_i225(struct igc_hw *hw, u16 offset, u16 words,
465 s32 status = IGC_SUCCESS;
468 DEBUGFUNC("igc_read_nvm_srrd_i225");
470 /* We cannot hold synchronization semaphores for too long,
471 * because of forceful takeover procedure. However it is more efficient
472 * to read in bursts than synchronizing access for each word.
474 for (i = 0; i < words; i += IGC_EERD_EEWR_MAX_COUNT) {
475 count = (words - i) / IGC_EERD_EEWR_MAX_COUNT > 0 ?
476 IGC_EERD_EEWR_MAX_COUNT : (words - i);
477 if (hw->nvm.ops.acquire(hw) == IGC_SUCCESS) {
478 status = igc_read_nvm_eerd(hw, offset, count,
480 hw->nvm.ops.release(hw);
482 status = IGC_ERR_SWFW_SYNC;
485 if (status != IGC_SUCCESS)
492 /* igc_write_nvm_srwr_i225 - Write to Shadow RAM using EEWR
493 * @hw: pointer to the HW structure
494 * @offset: offset within the Shadow RAM to be written to
495 * @words: number of words to write
496 * @data: 16 bit word(s) to be written to the Shadow RAM
498 * Writes data to Shadow RAM at offset using EEWR register.
500 * If igc_update_nvm_checksum is not called after this function , the
501 * data will not be committed to FLASH and also Shadow RAM will most likely
502 * contain an invalid checksum.
504 * If error code is returned, data and Shadow RAM may be inconsistent - buffer
507 s32 igc_write_nvm_srwr_i225(struct igc_hw *hw, u16 offset, u16 words,
510 s32 status = IGC_SUCCESS;
513 DEBUGFUNC("igc_write_nvm_srwr_i225");
515 /* We cannot hold synchronization semaphores for too long,
516 * because of forceful takeover procedure. However it is more efficient
517 * to write in bursts than synchronizing access for each word.
519 for (i = 0; i < words; i += IGC_EERD_EEWR_MAX_COUNT) {
520 count = (words - i) / IGC_EERD_EEWR_MAX_COUNT > 0 ?
521 IGC_EERD_EEWR_MAX_COUNT : (words - i);
522 if (hw->nvm.ops.acquire(hw) == IGC_SUCCESS) {
523 status = __igc_write_nvm_srwr(hw, offset, count,
525 hw->nvm.ops.release(hw);
527 status = IGC_ERR_SWFW_SYNC;
530 if (status != IGC_SUCCESS)
537 /* __igc_write_nvm_srwr - Write to Shadow Ram using EEWR
538 * @hw: pointer to the HW structure
539 * @offset: offset within the Shadow Ram to be written to
540 * @words: number of words to write
541 * @data: 16 bit word(s) to be written to the Shadow Ram
543 * Writes data to Shadow Ram at offset using EEWR register.
545 * If igc_update_nvm_checksum is not called after this function , the
546 * Shadow Ram will most likely contain an invalid checksum.
548 static s32 __igc_write_nvm_srwr(struct igc_hw *hw, u16 offset, u16 words,
551 struct igc_nvm_info *nvm = &hw->nvm;
553 u32 attempts = 100000;
554 s32 ret_val = IGC_SUCCESS;
556 DEBUGFUNC("__igc_write_nvm_srwr");
558 /* A check for invalid values: offset too large, too many words,
559 * too many words for the offset, and not enough words.
561 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
563 DEBUGOUT("nvm parameter(s) out of bounds\n");
564 ret_val = -IGC_ERR_NVM;
568 for (i = 0; i < words; i++) {
569 eewr = ((offset + i) << IGC_NVM_RW_ADDR_SHIFT) |
570 (data[i] << IGC_NVM_RW_REG_DATA) |
571 IGC_NVM_RW_REG_START;
573 IGC_WRITE_REG(hw, IGC_SRWR, eewr);
575 for (k = 0; k < attempts; k++) {
576 if (IGC_NVM_RW_REG_DONE &
577 IGC_READ_REG(hw, IGC_SRWR)) {
578 ret_val = IGC_SUCCESS;
584 if (ret_val != IGC_SUCCESS) {
585 DEBUGOUT("Shadow RAM write EEWR timed out\n");
594 /* igc_validate_nvm_checksum_i225 - Validate EEPROM checksum
595 * @hw: pointer to the HW structure
597 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
598 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
600 s32 igc_validate_nvm_checksum_i225(struct igc_hw *hw)
602 s32 status = IGC_SUCCESS;
603 s32 (*read_op_ptr)(struct igc_hw *, u16, u16, u16 *);
605 DEBUGFUNC("igc_validate_nvm_checksum_i225");
607 if (hw->nvm.ops.acquire(hw) == IGC_SUCCESS) {
608 /* Replace the read function with semaphore grabbing with
609 * the one that skips this for a while.
610 * We have semaphore taken already here.
612 read_op_ptr = hw->nvm.ops.read;
613 hw->nvm.ops.read = igc_read_nvm_eerd;
615 status = igc_validate_nvm_checksum_generic(hw);
617 /* Revert original read operation. */
618 hw->nvm.ops.read = read_op_ptr;
620 hw->nvm.ops.release(hw);
622 status = IGC_ERR_SWFW_SYNC;
628 /* igc_update_nvm_checksum_i225 - Update EEPROM checksum
629 * @hw: pointer to the HW structure
631 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
632 * up to the checksum. Then calculates the EEPROM checksum and writes the
633 * value to the EEPROM. Next commit EEPROM data onto the Flash.
635 s32 igc_update_nvm_checksum_i225(struct igc_hw *hw)
641 DEBUGFUNC("igc_update_nvm_checksum_i225");
643 /* Read the first word from the EEPROM. If this times out or fails, do
644 * not continue or we could be in for a very long wait while every
647 ret_val = igc_read_nvm_eerd(hw, 0, 1, &nvm_data);
648 if (ret_val != IGC_SUCCESS) {
649 DEBUGOUT("EEPROM read failed\n");
653 if (hw->nvm.ops.acquire(hw) == IGC_SUCCESS) {
654 /* Do not use hw->nvm.ops.write, hw->nvm.ops.read
655 * because we do not want to take the synchronization
656 * semaphores twice here.
659 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
660 ret_val = igc_read_nvm_eerd(hw, i, 1, &nvm_data);
662 hw->nvm.ops.release(hw);
663 DEBUGOUT("NVM Read Error while updating\n");
664 DEBUGOUT("checksum.\n");
667 checksum += nvm_data;
669 checksum = (u16)NVM_SUM - checksum;
670 ret_val = __igc_write_nvm_srwr(hw, NVM_CHECKSUM_REG, 1,
672 if (ret_val != IGC_SUCCESS) {
673 hw->nvm.ops.release(hw);
674 DEBUGOUT("NVM Write Error while updating checksum.\n");
678 hw->nvm.ops.release(hw);
680 ret_val = igc_update_flash_i225(hw);
682 ret_val = IGC_ERR_SWFW_SYNC;
688 /* igc_get_flash_presence_i225 - Check if flash device is detected.
689 * @hw: pointer to the HW structure
691 bool igc_get_flash_presence_i225(struct igc_hw *hw)
694 bool ret_val = false;
696 DEBUGFUNC("igc_get_flash_presence_i225");
698 eec = IGC_READ_REG(hw, IGC_EECD);
700 if (eec & IGC_EECD_FLASH_DETECTED_I225)
706 /* igc_set_flsw_flash_burst_counter_i225 - sets FLSW NVM Burst
707 * Counter in FLSWCNT register.
709 * @hw: pointer to the HW structure
710 * @burst_counter: size in bytes of the Flash burst to read or write
712 s32 igc_set_flsw_flash_burst_counter_i225(struct igc_hw *hw,
715 s32 ret_val = IGC_SUCCESS;
717 DEBUGFUNC("igc_set_flsw_flash_burst_counter_i225");
719 /* Validate input data */
720 if (burst_counter < IGC_I225_SHADOW_RAM_SIZE) {
721 /* Write FLSWCNT - burst counter */
722 IGC_WRITE_REG(hw, IGC_I225_FLSWCNT, burst_counter);
724 ret_val = IGC_ERR_INVALID_ARGUMENT;
730 /* igc_write_erase_flash_command_i225 - write/erase to a sector
731 * region on a given address.
733 * @hw: pointer to the HW structure
734 * @opcode: opcode to be used for the write command
735 * @address: the offset to write into the FLASH image
737 s32 igc_write_erase_flash_command_i225(struct igc_hw *hw, u32 opcode,
741 s32 timeout = IGC_NVM_GRANT_ATTEMPTS;
742 s32 ret_val = IGC_SUCCESS;
744 DEBUGFUNC("igc_write_erase_flash_command_i225");
746 flswctl = IGC_READ_REG(hw, IGC_I225_FLSWCTL);
747 /* Polling done bit on FLSWCTL register */
749 if (flswctl & IGC_FLSWCTL_DONE)
752 flswctl = IGC_READ_REG(hw, IGC_I225_FLSWCTL);
757 DEBUGOUT("Flash transaction was not done\n");
761 /* Build and issue command on FLSWCTL register */
762 flswctl = address | opcode;
763 IGC_WRITE_REG(hw, IGC_I225_FLSWCTL, flswctl);
765 /* Check if issued command is valid on FLSWCTL register */
766 flswctl = IGC_READ_REG(hw, IGC_I225_FLSWCTL);
767 if (!(flswctl & IGC_FLSWCTL_CMDV)) {
768 DEBUGOUT("Write flash command failed\n");
769 ret_val = IGC_ERR_INVALID_ARGUMENT;
775 /* igc_update_flash_i225 - Commit EEPROM to the flash
776 * if fw_valid_bit is set, FW is active. setting FLUPD bit in EEC
777 * register makes the FW load the internal shadow RAM into the flash.
778 * Otherwise, fw_valid_bit is 0. if FL_SECU.block_prtotected_sw = 0
779 * then FW is not active so the SW is responsible shadow RAM dump.
781 * @hw: pointer to the HW structure
783 s32 igc_update_flash_i225(struct igc_hw *hw)
785 u16 current_offset_data = 0;
786 u32 block_sw_protect = 1;
787 u16 base_address = 0x0;
793 DEBUGFUNC("igc_update_flash_i225");
795 block_sw_protect = IGC_READ_REG(hw, IGC_I225_FLSECU) &
796 IGC_FLSECU_BLK_SW_ACCESS_I225;
797 fw_valid_bit = IGC_READ_REG(hw, IGC_FWSM) &
798 IGC_FWSM_FW_VALID_I225;
800 ret_val = igc_pool_flash_update_done_i225(hw);
801 if (ret_val == -IGC_ERR_NVM) {
802 DEBUGOUT("Flash update time out\n");
806 flup = IGC_READ_REG(hw, IGC_EECD) | IGC_EECD_FLUPD_I225;
807 IGC_WRITE_REG(hw, IGC_EECD, flup);
809 ret_val = igc_pool_flash_update_done_i225(hw);
810 if (ret_val == IGC_SUCCESS)
811 DEBUGOUT("Flash update complete\n");
813 DEBUGOUT("Flash update time out\n");
814 } else if (!block_sw_protect) {
815 /* FW is not active and security protection is disabled.
816 * therefore, SW is in charge of shadow RAM dump.
817 * Check which sector is valid. if sector 0 is valid,
818 * base address remains 0x0. otherwise, sector 1 is
819 * valid and it's base address is 0x1000
821 if (IGC_READ_REG(hw, IGC_EECD) & IGC_EECD_SEC1VAL_I225)
822 base_address = 0x1000;
824 /* Valid sector erase */
825 ret_val = igc_write_erase_flash_command_i225(hw,
826 IGC_I225_ERASE_CMD_OPCODE,
829 DEBUGOUT("Sector erase failed\n");
833 current_offset = base_address;
836 for (i = 0; i < IGC_I225_SHADOW_RAM_SIZE / 2; i++) {
837 /* Set burst write length */
838 ret_val = igc_set_flsw_flash_burst_counter_i225(hw,
840 if (ret_val != IGC_SUCCESS)
843 /* Set address and opcode */
844 ret_val = igc_write_erase_flash_command_i225(hw,
845 IGC_I225_WRITE_CMD_OPCODE,
847 if (ret_val != IGC_SUCCESS)
850 ret_val = igc_read_nvm_eerd(hw, current_offset,
851 1, ¤t_offset_data);
853 DEBUGOUT("Failed to read from EEPROM\n");
857 /* Write CurrentOffseData to FLSWDATA register */
858 IGC_WRITE_REG(hw, IGC_I225_FLSWDATA,
859 current_offset_data);
862 /* Wait till operation has finished */
863 ret_val = igc_poll_eerd_eewr_done(hw,
875 /* igc_pool_flash_update_done_i225 - Pool FLUDONE status.
876 * @hw: pointer to the HW structure
878 s32 igc_pool_flash_update_done_i225(struct igc_hw *hw)
880 s32 ret_val = -IGC_ERR_NVM;
883 DEBUGFUNC("igc_pool_flash_update_done_i225");
885 for (i = 0; i < IGC_FLUDONE_ATTEMPTS; i++) {
886 reg = IGC_READ_REG(hw, IGC_EECD);
887 if (reg & IGC_EECD_FLUDONE_I225) {
888 ret_val = IGC_SUCCESS;
897 /* igc_set_ltr_i225 - Set Latency Tolerance Reporting thresholds.
898 * @hw: pointer to the HW structure
899 * @link: bool indicating link status
901 * Set the LTR thresholds based on the link speed (Mbps), EEE, and DMAC
902 * settings, otherwise specify that there is no LTR requirement.
904 static s32 igc_set_ltr_i225(struct igc_hw *hw, bool link)
907 u32 tw_system, ltrc, ltrv, ltr_min, ltr_max, scale_min, scale_max;
910 DEBUGFUNC("igc_set_ltr_i225");
912 /* If we do not have link, LTR thresholds are zero. */
914 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
916 /* Check if using copper interface with EEE enabled or if the
917 * link speed is 10 Mbps.
919 if ((hw->phy.media_type == igc_media_type_copper) &&
920 !(hw->dev_spec._i225.eee_disable) &&
921 (speed != SPEED_10)) {
922 /* EEE enabled, so send LTRMAX threshold. */
923 ltrc = IGC_READ_REG(hw, IGC_LTRC) |
925 IGC_WRITE_REG(hw, IGC_LTRC, ltrc);
927 /* Calculate tw_system (nsec). */
928 if (speed == SPEED_100) {
929 tw_system = ((IGC_READ_REG(hw, IGC_EEE_SU) &
930 IGC_TW_SYSTEM_100_MASK) >>
931 IGC_TW_SYSTEM_100_SHIFT) * 500;
933 tw_system = (IGC_READ_REG(hw, IGC_EEE_SU) &
934 IGC_TW_SYSTEM_1000_MASK) * 500;
940 /* Get the Rx packet buffer size. */
941 size = IGC_READ_REG(hw, IGC_RXPBS) &
942 IGC_RXPBS_SIZE_I225_MASK;
944 /* Calculations vary based on DMAC settings. */
945 if (IGC_READ_REG(hw, IGC_DMACR) & IGC_DMACR_DMAC_EN) {
946 size -= (IGC_READ_REG(hw, IGC_DMACR) &
947 IGC_DMACR_DMACTHR_MASK) >>
948 IGC_DMACR_DMACTHR_SHIFT;
949 /* Convert size to bits. */
952 /* Convert size to bytes, subtract the MTU, and then
953 * convert the size to bits.
956 size -= hw->dev_spec._i225.mtu;
961 DEBUGOUT1("Invalid effective Rx buffer size %d\n",
963 return -IGC_ERR_CONFIG;
966 /* Calculate the thresholds. Since speed is in Mbps, simplify
967 * the calculation by multiplying size/speed by 1000 for result
968 * to be in nsec before dividing by the scale in nsec. Set the
969 * scale such that the LTR threshold fits in the register.
971 ltr_min = (1000 * size) / speed;
972 ltr_max = ltr_min + tw_system;
973 scale_min = (ltr_min / 1024) < 1024 ? IGC_LTRMINV_SCALE_1024 :
974 IGC_LTRMINV_SCALE_32768;
975 scale_max = (ltr_max / 1024) < 1024 ? IGC_LTRMAXV_SCALE_1024 :
976 IGC_LTRMAXV_SCALE_32768;
977 ltr_min /= scale_min == IGC_LTRMINV_SCALE_1024 ? 1024 : 32768;
978 ltr_max /= scale_max == IGC_LTRMAXV_SCALE_1024 ? 1024 : 32768;
980 /* Only write the LTR thresholds if they differ from before. */
981 ltrv = IGC_READ_REG(hw, IGC_LTRMINV);
982 if (ltr_min != (ltrv & IGC_LTRMINV_LTRV_MASK)) {
983 ltrv = IGC_LTRMINV_LSNP_REQ | ltr_min |
984 (scale_min << IGC_LTRMINV_SCALE_SHIFT);
985 IGC_WRITE_REG(hw, IGC_LTRMINV, ltrv);
988 ltrv = IGC_READ_REG(hw, IGC_LTRMAXV);
989 if (ltr_max != (ltrv & IGC_LTRMAXV_LTRV_MASK)) {
990 ltrv = IGC_LTRMAXV_LSNP_REQ | ltr_max |
991 (scale_min << IGC_LTRMAXV_SCALE_SHIFT);
992 IGC_WRITE_REG(hw, IGC_LTRMAXV, ltrv);
999 /* igc_check_for_link_i225 - Check for link
1000 * @hw: pointer to the HW structure
1002 * Checks to see of the link status of the hardware has changed. If a
1003 * change in link status has been detected, then we read the PHY registers
1004 * to get the current speed/duplex if link exists.
1006 s32 igc_check_for_link_i225(struct igc_hw *hw)
1008 struct igc_mac_info *mac = &hw->mac;
1012 DEBUGFUNC("igc_check_for_link_i225");
1014 /* We only want to go out to the PHY registers to see if
1015 * Auto-Neg has completed and/or if our link status has
1016 * changed. The get_link_status flag is set upon receiving
1017 * a Link Status Change or Rx Sequence Error interrupt.
1019 if (!mac->get_link_status) {
1020 ret_val = IGC_SUCCESS;
1024 /* First we want to see if the MII Status Register reports
1025 * link. If so, then we want to get the current speed/duplex
1028 ret_val = igc_phy_has_link_generic(hw, 1, 0, &link);
1033 goto out; /* No link detected */
1035 /* First we want to see if the MII Status Register reports
1036 * link. If so, then we want to get the current speed/duplex
1039 ret_val = igc_phy_has_link_generic(hw, 1, 0, &link);
1044 goto out; /* No link detected */
1046 mac->get_link_status = false;
1048 /* Check if there was DownShift, must be checked
1049 * immediately after link-up
1051 igc_check_downshift_generic(hw);
1053 /* If we are forcing speed/duplex, then we simply return since
1054 * we have already determined whether we have link or not.
1059 /* Auto-Neg is enabled. Auto Speed Detection takes care
1060 * of MAC speed/duplex configuration. So we only need to
1061 * configure Collision Distance in the MAC.
1063 mac->ops.config_collision_dist(hw);
1065 /* Configure Flow Control now that Auto-Neg has completed.
1066 * First, we need to restore the desired flow control
1067 * settings because we may have had to re-autoneg with a
1068 * different link partner.
1070 ret_val = igc_config_fc_after_link_up_generic(hw);
1072 DEBUGOUT("Error configuring flow control\n");
1074 /* Now that we are aware of our link settings, we can set the LTR
1077 ret_val = igc_set_ltr_i225(hw, link);
1082 /* igc_init_function_pointers_i225 - Init func ptrs.
1083 * @hw: pointer to the HW structure
1085 * Called to initialize all function pointers and parameters.
1087 void igc_init_function_pointers_i225(struct igc_hw *hw)
1089 igc_init_mac_ops_generic(hw);
1090 igc_init_phy_ops_generic(hw);
1091 igc_init_nvm_ops_generic(hw);
1092 hw->mac.ops.init_params = igc_init_mac_params_i225;
1093 hw->nvm.ops.init_params = igc_init_nvm_params_i225;
1094 hw->phy.ops.init_params = igc_init_phy_params_i225;
1097 /* igc_init_hw_i225 - Init hw for I225
1098 * @hw: pointer to the HW structure
1100 * Called to initialize hw for i225 hw family.
1102 s32 igc_init_hw_i225(struct igc_hw *hw)
1106 DEBUGFUNC("igc_init_hw_i225");
1108 ret_val = igc_init_hw_base(hw);
1113 * igc_set_d0_lplu_state_i225 - Set Low-Power-Link-Up (LPLU) D0 state
1114 * @hw: pointer to the HW structure
1115 * @active: true to enable LPLU, false to disable
1117 * Note: since I225 does not actually support LPLU, this function
1118 * simply enables/disables 1G and 2.5G speeds in D0.
1120 s32 igc_set_d0_lplu_state_i225(struct igc_hw *hw, bool active)
1124 DEBUGFUNC("igc_set_d0_lplu_state_i225");
1126 data = IGC_READ_REG(hw, IGC_I225_PHPM);
1129 data |= IGC_I225_PHPM_DIS_1000;
1130 data |= IGC_I225_PHPM_DIS_2500;
1132 data &= ~IGC_I225_PHPM_DIS_1000;
1133 data &= ~IGC_I225_PHPM_DIS_2500;
1136 IGC_WRITE_REG(hw, IGC_I225_PHPM, data);
1141 * igc_set_d3_lplu_state_i225 - Set Low-Power-Link-Up (LPLU) D3 state
1142 * @hw: pointer to the HW structure
1143 * @active: true to enable LPLU, false to disable
1145 * Note: since I225 does not actually support LPLU, this function
1146 * simply enables/disables 100M, 1G and 2.5G speeds in D3.
1148 s32 igc_set_d3_lplu_state_i225(struct igc_hw *hw, bool active)
1152 DEBUGFUNC("igc_set_d3_lplu_state_i225");
1154 data = IGC_READ_REG(hw, IGC_I225_PHPM);
1157 data |= IGC_I225_PHPM_DIS_100_D3;
1158 data |= IGC_I225_PHPM_DIS_1000_D3;
1159 data |= IGC_I225_PHPM_DIS_2500_D3;
1161 data &= ~IGC_I225_PHPM_DIS_100_D3;
1162 data &= ~IGC_I225_PHPM_DIS_1000_D3;
1163 data &= ~IGC_I225_PHPM_DIS_2500_D3;
1166 IGC_WRITE_REG(hw, IGC_I225_PHPM, data);
1171 * igc_set_eee_i225 - Enable/disable EEE support
1172 * @hw: pointer to the HW structure
1173 * @adv2p5G: boolean flag enabling 2.5G EEE advertisement
1174 * @adv1G: boolean flag enabling 1G EEE advertisement
1175 * @adv100M: boolean flag enabling 100M EEE advertisement
1177 * Enable/disable EEE based on setting in dev_spec structure.
1180 s32 igc_set_eee_i225(struct igc_hw *hw, bool adv2p5G, bool adv1G,
1185 DEBUGFUNC("igc_set_eee_i225");
1187 if (hw->mac.type != igc_i225 ||
1188 hw->phy.media_type != igc_media_type_copper)
1190 ipcnfg = IGC_READ_REG(hw, IGC_IPCNFG);
1191 eeer = IGC_READ_REG(hw, IGC_EEER);
1193 /* enable or disable per user setting */
1194 if (!(hw->dev_spec._i225.eee_disable)) {
1195 u32 eee_su = IGC_READ_REG(hw, IGC_EEE_SU);
1198 ipcnfg |= IGC_IPCNFG_EEE_100M_AN;
1200 ipcnfg &= ~IGC_IPCNFG_EEE_100M_AN;
1203 ipcnfg |= IGC_IPCNFG_EEE_1G_AN;
1205 ipcnfg &= ~IGC_IPCNFG_EEE_1G_AN;
1208 ipcnfg |= IGC_IPCNFG_EEE_2_5G_AN;
1210 ipcnfg &= ~IGC_IPCNFG_EEE_2_5G_AN;
1212 eeer |= (IGC_EEER_TX_LPI_EN | IGC_EEER_RX_LPI_EN |
1215 /* This bit should not be set in normal operation. */
1216 if (eee_su & IGC_EEE_SU_LPI_CLK_STP)
1217 DEBUGOUT("LPI Clock Stop Bit should not be set!\n");
1219 ipcnfg &= ~(IGC_IPCNFG_EEE_2_5G_AN | IGC_IPCNFG_EEE_1G_AN |
1220 IGC_IPCNFG_EEE_100M_AN);
1221 eeer &= ~(IGC_EEER_TX_LPI_EN | IGC_EEER_RX_LPI_EN |
1224 IGC_WRITE_REG(hw, IGC_IPCNFG, ipcnfg);
1225 IGC_WRITE_REG(hw, IGC_EEER, eeer);
1226 IGC_READ_REG(hw, IGC_IPCNFG);
1227 IGC_READ_REG(hw, IGC_EEER);