sys/dev/igc/igc_i225.h

   1 /*-
   2  * Copyright 2021 Intel Corp
   3  * Copyright 2021 Rubicon Communications, LLC (Netgate)
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  *
   6  * $FreeBSD$
   7  */
   8
   9 #ifndef _IGC_I225_H_
  10 #define _IGC_I225_H_
  11
  12 bool igc_get_flash_presence_i225(struct igc_hw *hw);
  13 s32 igc_update_flash_i225(struct igc_hw *hw);
  14 s32 igc_update_nvm_checksum_i225(struct igc_hw *hw);
  15 s32 igc_validate_nvm_checksum_i225(struct igc_hw *hw);
  16 s32 igc_write_nvm_srwr_i225(struct igc_hw *hw, u16 offset,
  17                               u16 words, u16 *data);
  18 s32 igc_read_nvm_srrd_i225(struct igc_hw *hw, u16 offset,
  19                              u16 words, u16 *data);
  20 s32 igc_set_flsw_flash_burst_counter_i225(struct igc_hw *hw,
  21                                             u32 burst_counter);
  22 s32 igc_write_erase_flash_command_i225(struct igc_hw *hw, u32 opcode,
  23                                          u32 address);
  24 s32 igc_check_for_link_i225(struct igc_hw *hw);
  25 s32 igc_acquire_swfw_sync_i225(struct igc_hw *hw, u16 mask);
  26 void igc_release_swfw_sync_i225(struct igc_hw *hw, u16 mask);
  27 s32 igc_init_hw_i225(struct igc_hw *hw);
  28 s32 igc_setup_copper_link_i225(struct igc_hw *hw);
  29 s32 igc_set_d0_lplu_state_i225(struct igc_hw *hw, bool active);
  30 s32 igc_set_d3_lplu_state_i225(struct igc_hw *hw, bool active);
  31 s32 igc_set_eee_i225(struct igc_hw *hw, bool adv2p5G, bool adv1G,
  32                        bool adv100M);
  33
  34 #define ID_LED_DEFAULT_I225             ((ID_LED_OFF1_ON2  << 8) | \
  35                                          (ID_LED_DEF1_DEF2 <<  4) | \
  36                                          (ID_LED_OFF1_OFF2))
  37 #define ID_LED_DEFAULT_I225_SERDES      ((ID_LED_DEF1_DEF2 << 8) | \
  38                                          (ID_LED_DEF1_DEF2 <<  4) | \
  39                                          (ID_LED_OFF1_ON2))
  40
  41 /* NVM offset defaults for I225 devices */
  42 #define NVM_INIT_CTRL_2_DEFAULT_I225    0X7243
  43 #define NVM_INIT_CTRL_4_DEFAULT_I225    0x00C1
  44 #define NVM_LED_1_CFG_DEFAULT_I225      0x0184
  45 #define NVM_LED_0_2_CFG_DEFAULT_I225    0x200C
  46
  47 #define IGC_MRQC_ENABLE_RSS_4Q          0x00000002
  48 #define IGC_MRQC_ENABLE_VMDQ                    0x00000003
  49 #define IGC_MRQC_ENABLE_VMDQ_RSS_2Q             0x00000005
  50 #define IGC_MRQC_RSS_FIELD_IPV4_UDP             0x00400000
  51 #define IGC_MRQC_RSS_FIELD_IPV6_UDP             0x00800000
  52 #define IGC_MRQC_RSS_FIELD_IPV6_UDP_EX  0x01000000
  53 #define IGC_I225_SHADOW_RAM_SIZE                4096
  54 #define IGC_I225_ERASE_CMD_OPCODE               0x02000000
  55 #define IGC_I225_WRITE_CMD_OPCODE               0x01000000
  56 #define IGC_FLSWCTL_DONE                        0x40000000
  57 #define IGC_FLSWCTL_CMDV                        0x10000000
  58
  59 /* SRRCTL bit definitions */
  60 #define IGC_SRRCTL_BSIZEHDRSIZE_MASK            0x00000F00
  61 #define IGC_SRRCTL_DESCTYPE_LEGACY              0x00000000
  62 #define IGC_SRRCTL_DESCTYPE_HDR_SPLIT           0x04000000
  63 #define IGC_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS    0x0A000000
  64 #define IGC_SRRCTL_DESCTYPE_HDR_REPLICATION     0x06000000
  65 #define IGC_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
  66 #define IGC_SRRCTL_DESCTYPE_MASK                0x0E000000
  67 #define IGC_SRRCTL_DROP_EN                      0x80000000
  68 #define IGC_SRRCTL_BSIZEPKT_MASK                0x0000007F
  69 #define IGC_SRRCTL_BSIZEHDR_MASK                0x00003F00
  70
  71 #define IGC_RXDADV_RSSTYPE_MASK 0x0000000F
  72 #define IGC_RXDADV_RSSTYPE_SHIFT        12
  73 #define IGC_RXDADV_HDRBUFLEN_MASK       0x7FE0
  74 #define IGC_RXDADV_HDRBUFLEN_SHIFT      5
  75 #define IGC_RXDADV_SPLITHEADER_EN       0x00001000
  76 #define IGC_RXDADV_SPH          0x8000
  77 #define IGC_RXDADV_STAT_TS              0x10000 /* Pkt was time stamped */
  78 #define IGC_RXDADV_ERR_HBO              0x00800000
  79
  80 /* RSS Hash results */
  81 #define IGC_RXDADV_RSSTYPE_NONE 0x00000000
  82 #define IGC_RXDADV_RSSTYPE_IPV4_TCP     0x00000001
  83 #define IGC_RXDADV_RSSTYPE_IPV4 0x00000002
  84 #define IGC_RXDADV_RSSTYPE_IPV6_TCP     0x00000003
  85 #define IGC_RXDADV_RSSTYPE_IPV6_EX      0x00000004
  86 #define IGC_RXDADV_RSSTYPE_IPV6 0x00000005
  87 #define IGC_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006
  88 #define IGC_RXDADV_RSSTYPE_IPV4_UDP     0x00000007
  89 #define IGC_RXDADV_RSSTYPE_IPV6_UDP     0x00000008
  90 #define IGC_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009
  91
  92 /* RSS Packet Types as indicated in the receive descriptor */
  93 #define IGC_RXDADV_PKTTYPE_ILMASK       0x000000F0
  94 #define IGC_RXDADV_PKTTYPE_TLMASK       0x00000F00
  95 #define IGC_RXDADV_PKTTYPE_NONE 0x00000000
  96 #define IGC_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPV4 hdr present */
  97 #define IGC_RXDADV_PKTTYPE_IPV4_EX      0x00000020 /* IPV4 hdr + extensions */
  98 #define IGC_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPV6 hdr present */
  99 #define IGC_RXDADV_PKTTYPE_IPV6_EX      0x00000080 /* IPV6 hdr + extensions */
 100 #define IGC_RXDADV_PKTTYPE_TCP  0x00000100 /* TCP hdr present */
 101 #define IGC_RXDADV_PKTTYPE_UDP  0x00000200 /* UDP hdr present */
 102 #define IGC_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */
 103 #define IGC_RXDADV_PKTTYPE_NFS  0x00000800 /* NFS hdr present */
 104
 105 #define IGC_RXDADV_PKTTYPE_IPSEC_ESP    0x00001000 /* IPSec ESP */
 106 #define IGC_RXDADV_PKTTYPE_IPSEC_AH     0x00002000 /* IPSec AH */
 107 #define IGC_RXDADV_PKTTYPE_LINKSEC      0x00004000 /* LinkSec Encap */
 108 #define IGC_RXDADV_PKTTYPE_ETQF 0x00008000 /* PKTTYPE is ETQF index */
 109 #define IGC_RXDADV_PKTTYPE_ETQF_MASK    0x00000070 /* ETQF has 8 indices */
 110 #define IGC_RXDADV_PKTTYPE_ETQF_SHIFT   4 /* Right-shift 4 bits */
 111
 112 #endif