2 * Copyright 2021 Intel Corp
3 * Copyright 2021 Rubicon Communications, LLC (Netgate)
4 * SPDX-License-Identifier: BSD-3-Clause
12 static void igc_config_collision_dist_generic(struct igc_hw *hw);
15 * igc_init_mac_ops_generic - Initialize MAC function pointers
16 * @hw: pointer to the HW structure
18 * Setups up the function pointers to no-op functions
20 void igc_init_mac_ops_generic(struct igc_hw *hw)
22 struct igc_mac_info *mac = &hw->mac;
23 DEBUGFUNC("igc_init_mac_ops_generic");
26 mac->ops.init_params = igc_null_ops_generic;
27 mac->ops.config_collision_dist = igc_config_collision_dist_generic;
28 mac->ops.rar_set = igc_rar_set_generic;
32 * igc_null_ops_generic - No-op function, returns 0
33 * @hw: pointer to the HW structure
35 s32 igc_null_ops_generic(struct igc_hw IGC_UNUSEDARG *hw)
37 DEBUGFUNC("igc_null_ops_generic");
42 * igc_null_mac_generic - No-op function, return void
43 * @hw: pointer to the HW structure
45 void igc_null_mac_generic(struct igc_hw IGC_UNUSEDARG *hw)
47 DEBUGFUNC("igc_null_mac_generic");
52 * igc_null_link_info - No-op function, return 0
53 * @hw: pointer to the HW structure
57 s32 igc_null_link_info(struct igc_hw IGC_UNUSEDARG *hw,
58 u16 IGC_UNUSEDARG *s, u16 IGC_UNUSEDARG *d)
60 DEBUGFUNC("igc_null_link_info");
65 * igc_null_mng_mode - No-op function, return false
66 * @hw: pointer to the HW structure
68 bool igc_null_mng_mode(struct igc_hw IGC_UNUSEDARG *hw)
70 DEBUGFUNC("igc_null_mng_mode");
75 * igc_null_update_mc - No-op function, return void
76 * @hw: pointer to the HW structure
80 void igc_null_update_mc(struct igc_hw IGC_UNUSEDARG *hw,
81 u8 IGC_UNUSEDARG *h, u32 IGC_UNUSEDARG a)
83 DEBUGFUNC("igc_null_update_mc");
88 * igc_null_write_vfta - No-op function, return void
89 * @hw: pointer to the HW structure
93 void igc_null_write_vfta(struct igc_hw IGC_UNUSEDARG *hw,
94 u32 IGC_UNUSEDARG a, u32 IGC_UNUSEDARG b)
96 DEBUGFUNC("igc_null_write_vfta");
101 * igc_null_rar_set - No-op function, return 0
102 * @hw: pointer to the HW structure
106 int igc_null_rar_set(struct igc_hw IGC_UNUSEDARG *hw,
107 u8 IGC_UNUSEDARG *h, u32 IGC_UNUSEDARG a)
109 DEBUGFUNC("igc_null_rar_set");
114 * igc_set_lan_id_single_port - Set LAN id for a single port device
115 * @hw: pointer to the HW structure
117 * Sets the LAN function id to zero for a single port device.
119 void igc_set_lan_id_single_port(struct igc_hw *hw)
121 struct igc_bus_info *bus = &hw->bus;
127 * igc_clear_vfta_generic - Clear VLAN filter table
128 * @hw: pointer to the HW structure
130 * Clears the register array which contains the VLAN filter table by
131 * setting all the values to 0.
133 void igc_clear_vfta_generic(struct igc_hw *hw)
137 DEBUGFUNC("igc_clear_vfta_generic");
139 for (offset = 0; offset < IGC_VLAN_FILTER_TBL_SIZE; offset++) {
140 IGC_WRITE_REG_ARRAY(hw, IGC_VFTA, offset, 0);
146 * igc_write_vfta_generic - Write value to VLAN filter table
147 * @hw: pointer to the HW structure
148 * @offset: register offset in VLAN filter table
149 * @value: register value written to VLAN filter table
151 * Writes value at the given offset in the register array which stores
152 * the VLAN filter table.
154 void igc_write_vfta_generic(struct igc_hw *hw, u32 offset, u32 value)
156 DEBUGFUNC("igc_write_vfta_generic");
158 IGC_WRITE_REG_ARRAY(hw, IGC_VFTA, offset, value);
163 * igc_init_rx_addrs_generic - Initialize receive address's
164 * @hw: pointer to the HW structure
165 * @rar_count: receive address registers
167 * Setup the receive address registers by setting the base receive address
168 * register to the devices MAC address and clearing all the other receive
169 * address registers to 0.
171 void igc_init_rx_addrs_generic(struct igc_hw *hw, u16 rar_count)
174 u8 mac_addr[ETH_ADDR_LEN] = {0};
176 DEBUGFUNC("igc_init_rx_addrs_generic");
178 /* Setup the receive address */
179 DEBUGOUT("Programming MAC Address into RAR[0]\n");
181 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
183 /* Zero out the other (rar_entry_count - 1) receive addresses */
184 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1);
185 for (i = 1; i < rar_count; i++)
186 hw->mac.ops.rar_set(hw, mac_addr, i);
190 * igc_check_alt_mac_addr_generic - Check for alternate MAC addr
191 * @hw: pointer to the HW structure
193 * Checks the nvm for an alternate MAC address. An alternate MAC address
194 * can be setup by pre-boot software and must be treated like a permanent
195 * address and must override the actual permanent MAC address. If an
196 * alternate MAC address is found it is programmed into RAR0, replacing
197 * the permanent address that was installed into RAR0 by the Si on reset.
198 * This function will return SUCCESS unless it encounters an error while
199 * reading the EEPROM.
201 s32 igc_check_alt_mac_addr_generic(struct igc_hw *hw)
205 u16 offset, nvm_alt_mac_addr_offset, nvm_data;
206 u8 alt_mac_addr[ETH_ADDR_LEN];
208 DEBUGFUNC("igc_check_alt_mac_addr_generic");
210 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data);
215 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1,
216 &nvm_alt_mac_addr_offset);
218 DEBUGOUT("NVM Read Error\n");
222 if ((nvm_alt_mac_addr_offset == 0xFFFF) ||
223 (nvm_alt_mac_addr_offset == 0x0000))
224 /* There is no Alternate MAC Address */
227 if (hw->bus.func == IGC_FUNC_1)
228 nvm_alt_mac_addr_offset += IGC_ALT_MAC_ADDRESS_OFFSET_LAN1;
229 for (i = 0; i < ETH_ADDR_LEN; i += 2) {
230 offset = nvm_alt_mac_addr_offset + (i >> 1);
231 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
233 DEBUGOUT("NVM Read Error\n");
237 alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
238 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
241 /* if multicast bit is set, the alternate address will not be used */
242 if (alt_mac_addr[0] & 0x01) {
243 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n");
247 /* We have a valid alternate MAC address, and we want to treat it the
248 * same as the normal permanent MAC address stored by the HW into the
249 * RAR. Do this by mapping this address into RAR0.
251 hw->mac.ops.rar_set(hw, alt_mac_addr, 0);
257 * igc_rar_set_generic - Set receive address register
258 * @hw: pointer to the HW structure
259 * @addr: pointer to the receive address
260 * @index: receive address array register
262 * Sets the receive address array register at index to the address passed
265 int igc_rar_set_generic(struct igc_hw *hw, u8 *addr, u32 index)
267 u32 rar_low, rar_high;
269 DEBUGFUNC("igc_rar_set_generic");
271 /* HW expects these in little endian so we reverse the byte order
272 * from network order (big endian) to little endian
274 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
275 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
277 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
279 /* If MAC address zero, no need to set the AV bit */
280 if (rar_low || rar_high)
281 rar_high |= IGC_RAH_AV;
283 /* Some bridges will combine consecutive 32-bit writes into
284 * a single burst write, which will malfunction on some parts.
285 * The flushes avoid this.
287 IGC_WRITE_REG(hw, IGC_RAL(index), rar_low);
289 IGC_WRITE_REG(hw, IGC_RAH(index), rar_high);
296 * igc_hash_mc_addr_generic - Generate a multicast hash value
297 * @hw: pointer to the HW structure
298 * @mc_addr: pointer to a multicast address
300 * Generates a multicast address hash value which is used to determine
301 * the multicast filter table array address and new table value.
303 u32 igc_hash_mc_addr_generic(struct igc_hw *hw, u8 *mc_addr)
305 u32 hash_value, hash_mask;
308 DEBUGFUNC("igc_hash_mc_addr_generic");
310 /* Register count multiplied by bits per register */
311 hash_mask = (hw->mac.mta_reg_count * 32) - 1;
313 /* For a mc_filter_type of 0, bit_shift is the number of left-shifts
314 * where 0xFF would still fall within the hash mask.
316 while (hash_mask >> bit_shift != 0xFF)
319 /* The portion of the address that is used for the hash table
320 * is determined by the mc_filter_type setting.
321 * The algorithm is such that there is a total of 8 bits of shifting.
322 * The bit_shift for a mc_filter_type of 0 represents the number of
323 * left-shifts where the MSB of mc_addr[5] would still fall within
324 * the hash_mask. Case 0 does this exactly. Since there are a total
325 * of 8 bits of shifting, then mc_addr[4] will shift right the
326 * remaining number of bits. Thus 8 - bit_shift. The rest of the
327 * cases are a variation of this algorithm...essentially raising the
328 * number of bits to shift mc_addr[5] left, while still keeping the
329 * 8-bit shifting total.
331 * For example, given the following Destination MAC Address and an
332 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
333 * we can see that the bit_shift for case 0 is 4. These are the hash
334 * values resulting from each mc_filter_type...
335 * [0] [1] [2] [3] [4] [5]
339 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
340 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
341 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
342 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
344 switch (hw->mac.mc_filter_type) {
359 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
360 (((u16) mc_addr[5]) << bit_shift)));
366 * igc_update_mc_addr_list_generic - Update Multicast addresses
367 * @hw: pointer to the HW structure
368 * @mc_addr_list: array of multicast addresses to program
369 * @mc_addr_count: number of multicast addresses to program
371 * Updates entire Multicast Table Array.
372 * The caller must have a packed mc_addr_list of multicast addresses.
374 void igc_update_mc_addr_list_generic(struct igc_hw *hw,
375 u8 *mc_addr_list, u32 mc_addr_count)
377 u32 hash_value, hash_bit, hash_reg;
380 DEBUGFUNC("igc_update_mc_addr_list_generic");
382 /* clear mta_shadow */
383 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
385 /* update mta_shadow from mc_addr_list */
386 for (i = 0; (u32) i < mc_addr_count; i++) {
387 hash_value = igc_hash_mc_addr_generic(hw, mc_addr_list);
389 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
390 hash_bit = hash_value & 0x1F;
392 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);
393 mc_addr_list += (ETH_ADDR_LEN);
396 /* replace the entire MTA table */
397 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
398 IGC_WRITE_REG_ARRAY(hw, IGC_MTA, i, hw->mac.mta_shadow[i]);
403 * igc_clear_hw_cntrs_base_generic - Clear base hardware counters
404 * @hw: pointer to the HW structure
406 * Clears the base hardware counters by reading the counter registers.
408 void igc_clear_hw_cntrs_base_generic(struct igc_hw *hw)
410 DEBUGFUNC("igc_clear_hw_cntrs_base_generic");
412 IGC_READ_REG(hw, IGC_CRCERRS);
413 IGC_READ_REG(hw, IGC_MPC);
414 IGC_READ_REG(hw, IGC_SCC);
415 IGC_READ_REG(hw, IGC_ECOL);
416 IGC_READ_REG(hw, IGC_MCC);
417 IGC_READ_REG(hw, IGC_LATECOL);
418 IGC_READ_REG(hw, IGC_COLC);
419 IGC_READ_REG(hw, IGC_RERC);
420 IGC_READ_REG(hw, IGC_DC);
421 IGC_READ_REG(hw, IGC_RLEC);
422 IGC_READ_REG(hw, IGC_XONRXC);
423 IGC_READ_REG(hw, IGC_XONTXC);
424 IGC_READ_REG(hw, IGC_XOFFRXC);
425 IGC_READ_REG(hw, IGC_XOFFTXC);
426 IGC_READ_REG(hw, IGC_FCRUC);
427 IGC_READ_REG(hw, IGC_GPRC);
428 IGC_READ_REG(hw, IGC_BPRC);
429 IGC_READ_REG(hw, IGC_MPRC);
430 IGC_READ_REG(hw, IGC_GPTC);
431 IGC_READ_REG(hw, IGC_GORCL);
432 IGC_READ_REG(hw, IGC_GORCH);
433 IGC_READ_REG(hw, IGC_GOTCL);
434 IGC_READ_REG(hw, IGC_GOTCH);
435 IGC_READ_REG(hw, IGC_RNBC);
436 IGC_READ_REG(hw, IGC_RUC);
437 IGC_READ_REG(hw, IGC_RFC);
438 IGC_READ_REG(hw, IGC_ROC);
439 IGC_READ_REG(hw, IGC_RJC);
440 IGC_READ_REG(hw, IGC_TORL);
441 IGC_READ_REG(hw, IGC_TORH);
442 IGC_READ_REG(hw, IGC_TOTL);
443 IGC_READ_REG(hw, IGC_TOTH);
444 IGC_READ_REG(hw, IGC_TPR);
445 IGC_READ_REG(hw, IGC_TPT);
446 IGC_READ_REG(hw, IGC_MPTC);
447 IGC_READ_REG(hw, IGC_BPTC);
448 IGC_READ_REG(hw, IGC_TLPIC);
449 IGC_READ_REG(hw, IGC_RLPIC);
450 IGC_READ_REG(hw, IGC_RXDMTC);
454 * igc_check_for_copper_link_generic - Check for link (Copper)
455 * @hw: pointer to the HW structure
457 * Checks to see of the link status of the hardware has changed. If a
458 * change in link status has been detected, then we read the PHY registers
459 * to get the current speed/duplex if link exists.
461 s32 igc_check_for_copper_link_generic(struct igc_hw *hw)
463 struct igc_mac_info *mac = &hw->mac;
467 DEBUGFUNC("igc_check_for_copper_link");
469 /* We only want to go out to the PHY registers to see if Auto-Neg
470 * has completed and/or if our link status has changed. The
471 * get_link_status flag is set upon receiving a Link Status
472 * Change or Rx Sequence Error interrupt.
474 if (!mac->get_link_status)
477 /* First we want to see if the MII Status Register reports
478 * link. If so, then we want to get the current speed/duplex
481 ret_val = igc_phy_has_link_generic(hw, 1, 0, &link);
486 return IGC_SUCCESS; /* No link detected */
488 mac->get_link_status = false;
490 /* Check if there was DownShift, must be checked
491 * immediately after link-up
493 igc_check_downshift_generic(hw);
495 /* If we are forcing speed/duplex, then we simply return since
496 * we have already determined whether we have link or not.
499 return -IGC_ERR_CONFIG;
501 /* Auto-Neg is enabled. Auto Speed Detection takes care
502 * of MAC speed/duplex configuration. So we only need to
503 * configure Collision Distance in the MAC.
505 mac->ops.config_collision_dist(hw);
507 /* Configure Flow Control now that Auto-Neg has completed.
508 * First, we need to restore the desired flow control
509 * settings because we may have had to re-autoneg with a
510 * different link partner.
512 ret_val = igc_config_fc_after_link_up_generic(hw);
514 DEBUGOUT("Error configuring flow control\n");
520 * igc_setup_link_generic - Setup flow control and link settings
521 * @hw: pointer to the HW structure
523 * Determines which flow control settings to use, then configures flow
524 * control. Calls the appropriate media-specific link configuration
525 * function. Assuming the adapter has a valid link partner, a valid link
526 * should be established. Assumes the hardware has previously been reset
527 * and the transmitter and receiver are not enabled.
529 s32 igc_setup_link_generic(struct igc_hw *hw)
533 DEBUGFUNC("igc_setup_link_generic");
535 /* In the case of the phy reset being blocked, we already have a link.
536 * We do not need to set it up again.
538 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
541 /* If requested flow control is set to default, set flow control
542 * for both 'rx' and 'tx' pause frames.
544 if (hw->fc.requested_mode == igc_fc_default) {
545 hw->fc.requested_mode = igc_fc_full;
548 /* Save off the requested flow control mode for use later. Depending
549 * on the link partner's capabilities, we may or may not use this mode.
551 hw->fc.current_mode = hw->fc.requested_mode;
553 DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
554 hw->fc.current_mode);
556 /* Call the necessary media_type subroutine to configure the link. */
557 ret_val = hw->mac.ops.setup_physical_interface(hw);
561 /* Initialize the flow control address, type, and PAUSE timer
562 * registers to their default values. This is done even if flow
563 * control is disabled, because it does not hurt anything to
564 * initialize these registers.
566 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
567 IGC_WRITE_REG(hw, IGC_FCT, FLOW_CONTROL_TYPE);
568 IGC_WRITE_REG(hw, IGC_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
569 IGC_WRITE_REG(hw, IGC_FCAL, FLOW_CONTROL_ADDRESS_LOW);
571 IGC_WRITE_REG(hw, IGC_FCTTV, hw->fc.pause_time);
573 return igc_set_fc_watermarks_generic(hw);
577 * igc_config_collision_dist_generic - Configure collision distance
578 * @hw: pointer to the HW structure
580 * Configures the collision distance to the default value and is used
583 static void igc_config_collision_dist_generic(struct igc_hw *hw)
587 DEBUGFUNC("igc_config_collision_dist_generic");
589 tctl = IGC_READ_REG(hw, IGC_TCTL);
591 tctl &= ~IGC_TCTL_COLD;
592 tctl |= IGC_COLLISION_DISTANCE << IGC_COLD_SHIFT;
594 IGC_WRITE_REG(hw, IGC_TCTL, tctl);
599 * igc_set_fc_watermarks_generic - Set flow control high/low watermarks
600 * @hw: pointer to the HW structure
602 * Sets the flow control high/low threshold (watermark) registers. If
603 * flow control XON frame transmission is enabled, then set XON frame
604 * transmission as well.
606 s32 igc_set_fc_watermarks_generic(struct igc_hw *hw)
608 u32 fcrtl = 0, fcrth = 0;
610 DEBUGFUNC("igc_set_fc_watermarks_generic");
612 /* Set the flow control receive threshold registers. Normally,
613 * these registers will be set to a default threshold that may be
614 * adjusted later by the driver's runtime code. However, if the
615 * ability to transmit pause frames is not enabled, then these
616 * registers will be set to 0.
618 if (hw->fc.current_mode & igc_fc_tx_pause) {
619 /* We need to set up the Receive Threshold high and low water
620 * marks as well as (optionally) enabling the transmission of
623 fcrtl = hw->fc.low_water;
625 fcrtl |= IGC_FCRTL_XONE;
627 fcrth = hw->fc.high_water;
629 IGC_WRITE_REG(hw, IGC_FCRTL, fcrtl);
630 IGC_WRITE_REG(hw, IGC_FCRTH, fcrth);
636 * igc_force_mac_fc_generic - Force the MAC's flow control settings
637 * @hw: pointer to the HW structure
639 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
640 * device control register to reflect the adapter settings. TFCE and RFCE
641 * need to be explicitly set by software when a copper PHY is used because
642 * autonegotiation is managed by the PHY rather than the MAC. Software must
643 * also configure these bits when link is forced on a fiber connection.
645 s32 igc_force_mac_fc_generic(struct igc_hw *hw)
649 DEBUGFUNC("igc_force_mac_fc_generic");
651 ctrl = IGC_READ_REG(hw, IGC_CTRL);
653 /* Because we didn't get link via the internal auto-negotiation
654 * mechanism (we either forced link or we got link via PHY
655 * auto-neg), we have to manually enable/disable transmit an
656 * receive flow control.
658 * The "Case" statement below enables/disable flow control
659 * according to the "hw->fc.current_mode" parameter.
661 * The possible values of the "fc" parameter are:
662 * 0: Flow control is completely disabled
663 * 1: Rx flow control is enabled (we can receive pause
664 * frames but not send pause frames).
665 * 2: Tx flow control is enabled (we can send pause frames
666 * frames but we do not receive pause frames).
667 * 3: Both Rx and Tx flow control (symmetric) is enabled.
668 * other: No other values should be possible at this point.
670 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode);
672 switch (hw->fc.current_mode) {
674 ctrl &= (~(IGC_CTRL_TFCE | IGC_CTRL_RFCE));
676 case igc_fc_rx_pause:
677 ctrl &= (~IGC_CTRL_TFCE);
678 ctrl |= IGC_CTRL_RFCE;
680 case igc_fc_tx_pause:
681 ctrl &= (~IGC_CTRL_RFCE);
682 ctrl |= IGC_CTRL_TFCE;
685 ctrl |= (IGC_CTRL_TFCE | IGC_CTRL_RFCE);
688 DEBUGOUT("Flow control param set incorrectly\n");
689 return -IGC_ERR_CONFIG;
692 IGC_WRITE_REG(hw, IGC_CTRL, ctrl);
698 * igc_config_fc_after_link_up_generic - Configures flow control after link
699 * @hw: pointer to the HW structure
701 * Checks the status of auto-negotiation after link up to ensure that the
702 * speed and duplex were not forced. If the link needed to be forced, then
703 * flow control needs to be forced also. If auto-negotiation is enabled
704 * and did not fail, then we configure flow control based on our link
707 s32 igc_config_fc_after_link_up_generic(struct igc_hw *hw)
709 struct igc_mac_info *mac = &hw->mac;
710 s32 ret_val = IGC_SUCCESS;
711 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
714 DEBUGFUNC("igc_config_fc_after_link_up_generic");
717 DEBUGOUT("Error forcing flow control settings\n");
721 /* Check for the case where we have copper media and auto-neg is
722 * enabled. In this case, we need to check and see if Auto-Neg
723 * has completed, and if so, how the PHY and link partner has
724 * flow control configured.
727 /* Read the MII Status Register and check to see if AutoNeg
728 * has completed. We read this twice because this reg has
729 * some "sticky" (latched) bits.
731 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
734 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
738 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
739 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n");
743 /* The AutoNeg process has completed, so we now need to
744 * read both the Auto Negotiation Advertisement
745 * Register (Address 4) and the Auto_Negotiation Base
746 * Page Ability Register (Address 5) to determine how
747 * flow control was negotiated.
749 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
753 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,
754 &mii_nway_lp_ability_reg);
758 /* Two bits in the Auto Negotiation Advertisement Register
759 * (Address 4) and two bits in the Auto Negotiation Base
760 * Page Ability Register (Address 5) determine flow control
761 * for both the PHY and the link partner. The following
762 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
763 * 1999, describes these PAUSE resolution bits and how flow
764 * control is determined based upon these settings.
765 * NOTE: DC = Don't Care
767 * LOCAL DEVICE | LINK PARTNER
768 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
769 *-------|---------|-------|---------|--------------------
770 * 0 | 0 | DC | DC | igc_fc_none
771 * 0 | 1 | 0 | DC | igc_fc_none
772 * 0 | 1 | 1 | 0 | igc_fc_none
773 * 0 | 1 | 1 | 1 | igc_fc_tx_pause
774 * 1 | 0 | 0 | DC | igc_fc_none
775 * 1 | DC | 1 | DC | igc_fc_full
776 * 1 | 1 | 0 | 0 | igc_fc_none
777 * 1 | 1 | 0 | 1 | igc_fc_rx_pause
779 * Are both PAUSE bits set to 1? If so, this implies
780 * Symmetric Flow Control is enabled at both ends. The
781 * ASM_DIR bits are irrelevant per the spec.
783 * For Symmetric Flow Control:
785 * LOCAL DEVICE | LINK PARTNER
786 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
787 *-------|---------|-------|---------|--------------------
788 * 1 | DC | 1 | DC | IGC_fc_full
791 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
792 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
793 /* Now we need to check if the user selected Rx ONLY
794 * of pause frames. In this case, we had to advertise
795 * FULL flow control because we could not advertise Rx
796 * ONLY. Hence, we must now check to see if we need to
797 * turn OFF the TRANSMISSION of PAUSE frames.
799 if (hw->fc.requested_mode == igc_fc_full) {
800 hw->fc.current_mode = igc_fc_full;
801 DEBUGOUT("Flow Control = FULL.\n");
803 hw->fc.current_mode = igc_fc_rx_pause;
804 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
807 /* For receiving PAUSE frames ONLY.
809 * LOCAL DEVICE | LINK PARTNER
810 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
811 *-------|---------|-------|---------|--------------------
812 * 0 | 1 | 1 | 1 | igc_fc_tx_pause
814 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
815 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
816 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
817 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
818 hw->fc.current_mode = igc_fc_tx_pause;
819 DEBUGOUT("Flow Control = Tx PAUSE frames only.\n");
821 /* For transmitting PAUSE frames ONLY.
823 * LOCAL DEVICE | LINK PARTNER
824 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
825 *-------|---------|-------|---------|--------------------
826 * 1 | 1 | 0 | 1 | igc_fc_rx_pause
828 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
829 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
830 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
831 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
832 hw->fc.current_mode = igc_fc_rx_pause;
833 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
835 /* Per the IEEE spec, at this point flow control
836 * should be disabled.
838 hw->fc.current_mode = igc_fc_none;
839 DEBUGOUT("Flow Control = NONE.\n");
842 /* Now we need to do one last check... If we auto-
843 * negotiated to HALF DUPLEX, flow control should not be
844 * enabled per IEEE 802.3 spec.
846 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
848 DEBUGOUT("Error getting link speed and duplex\n");
852 if (duplex == HALF_DUPLEX)
853 hw->fc.current_mode = igc_fc_none;
855 /* Now we call a subroutine to actually force the MAC
856 * controller to use the correct flow control settings.
858 ret_val = igc_force_mac_fc_generic(hw);
860 DEBUGOUT("Error forcing flow control settings\n");
869 * igc_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex
870 * @hw: pointer to the HW structure
871 * @speed: stores the current speed
872 * @duplex: stores the current duplex
874 * Read the status register for the current speed/duplex and store the current
875 * speed and duplex for copper connections.
877 s32 igc_get_speed_and_duplex_copper_generic(struct igc_hw *hw, u16 *speed,
882 DEBUGFUNC("igc_get_speed_and_duplex_copper_generic");
884 status = IGC_READ_REG(hw, IGC_STATUS);
885 if (status & IGC_STATUS_SPEED_1000) {
886 /* For I225, STATUS will indicate 1G speed in both 1 Gbps
887 * and 2.5 Gbps link modes. An additional bit is used
888 * to differentiate between 1 Gbps and 2.5 Gbps.
890 if ((hw->mac.type == igc_i225) &&
891 (status & IGC_STATUS_SPEED_2500)) {
893 DEBUGOUT("2500 Mbs, ");
896 DEBUGOUT("1000 Mbs, ");
898 } else if (status & IGC_STATUS_SPEED_100) {
900 DEBUGOUT("100 Mbs, ");
903 DEBUGOUT("10 Mbs, ");
906 if (status & IGC_STATUS_FD) {
907 *duplex = FULL_DUPLEX;
908 DEBUGOUT("Full Duplex\n");
910 *duplex = HALF_DUPLEX;
911 DEBUGOUT("Half Duplex\n");
918 * igc_get_hw_semaphore_generic - Acquire hardware semaphore
919 * @hw: pointer to the HW structure
921 * Acquire the HW semaphore to access the PHY or NVM
923 s32 igc_get_hw_semaphore_generic(struct igc_hw *hw)
926 s32 timeout = hw->nvm.word_size + 1;
929 DEBUGFUNC("igc_get_hw_semaphore_generic");
931 /* Get the SW semaphore */
932 while (i < timeout) {
933 swsm = IGC_READ_REG(hw, IGC_SWSM);
934 if (!(swsm & IGC_SWSM_SMBI))
942 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
946 /* Get the FW semaphore. */
947 for (i = 0; i < timeout; i++) {
948 swsm = IGC_READ_REG(hw, IGC_SWSM);
949 IGC_WRITE_REG(hw, IGC_SWSM, swsm | IGC_SWSM_SWESMBI);
951 /* Semaphore acquired if bit latched */
952 if (IGC_READ_REG(hw, IGC_SWSM) & IGC_SWSM_SWESMBI)
959 /* Release semaphores */
960 igc_put_hw_semaphore_generic(hw);
961 DEBUGOUT("Driver can't access the NVM\n");
969 * igc_put_hw_semaphore_generic - Release hardware semaphore
970 * @hw: pointer to the HW structure
972 * Release hardware semaphore used to access the PHY or NVM
974 void igc_put_hw_semaphore_generic(struct igc_hw *hw)
978 DEBUGFUNC("igc_put_hw_semaphore_generic");
980 swsm = IGC_READ_REG(hw, IGC_SWSM);
982 swsm &= ~(IGC_SWSM_SMBI | IGC_SWSM_SWESMBI);
984 IGC_WRITE_REG(hw, IGC_SWSM, swsm);
988 * igc_get_auto_rd_done_generic - Check for auto read completion
989 * @hw: pointer to the HW structure
991 * Check EEPROM for Auto Read done bit.
993 s32 igc_get_auto_rd_done_generic(struct igc_hw *hw)
997 DEBUGFUNC("igc_get_auto_rd_done_generic");
999 while (i < AUTO_READ_DONE_TIMEOUT) {
1000 if (IGC_READ_REG(hw, IGC_EECD) & IGC_EECD_AUTO_RD)
1006 if (i == AUTO_READ_DONE_TIMEOUT) {
1007 DEBUGOUT("Auto read by HW from NVM has not completed.\n");
1008 return -IGC_ERR_RESET;
1015 * igc_disable_pcie_master_generic - Disables PCI-express master access
1016 * @hw: pointer to the HW structure
1018 * Returns IGC_SUCCESS if successful, else returns -10
1019 * (-IGC_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
1020 * the master requests to be disabled.
1022 * Disables PCI-Express master access and verifies there are no pending
1025 s32 igc_disable_pcie_master_generic(struct igc_hw *hw)
1028 s32 timeout = MASTER_DISABLE_TIMEOUT;
1030 DEBUGFUNC("igc_disable_pcie_master_generic");
1032 ctrl = IGC_READ_REG(hw, IGC_CTRL);
1033 ctrl |= IGC_CTRL_GIO_MASTER_DISABLE;
1034 IGC_WRITE_REG(hw, IGC_CTRL, ctrl);
1037 if (!(IGC_READ_REG(hw, IGC_STATUS) &
1038 IGC_STATUS_GIO_MASTER_ENABLE))
1045 DEBUGOUT("Master requests are pending.\n");
1046 return -IGC_ERR_MASTER_REQUESTS_PENDING;